CN108833204A - A Network-on-Chip Test Encapsulation Based on Bidirectional Transmission Path - Google Patents

Abstract

With the progress of semiconductor fabrication process, the more processor cores of multicore system on chip, reliability is with greater need for being taken seriously.The present invention is a kind of network-on-chip test encapsulation based on bidirectional transmission path.The test is encapsulated using bidirectional transmission path as test object, and bidirectional transmission path is used to replace router and link as the basic component units of network-on-chip, wherein bidirectional transmission path is defined as bi-directional data access and its close control logic circuit of Function Coupling between adjacent network-on-chip resource node.It is encapsulated based on the test, on-line testing can be carried out to network-on-chip idle route, fixed present in detection circuit and bridge type failure, Accurate Diagnosis abort situation will not have a negative impact to the application run in system while Test coverage data path and control logic circuit.The test encapsulates the measurability and observability for effectively improving the multicore system on chip based on network-on-chip, and then improves the reliability of digital display circuit.

Description

A Network-on-Chip Test Encapsulation Based on Bidirectional Transmission Path

technical field

The invention relates to an on-chip network test encapsulation based on a bidirectional transmission path, and belongs to the field of on-chip network test encapsulation.

Background technique

With the advancement of semiconductor manufacturing technology, in order to meet the requirements of high-performance parallel computing, multi-core system-on-chip integrates more resources such as processor cores. The ensuing large amount of traffic demand makes the network on chip become an important interconnection communication structure of the multi-core system. Compared with the bus-based communication structure, the network on chip has a larger address space, allowing multiple data packets to be transmitted at the same time, so it has greater bandwidth and flexibility.

Shrinking feature sizes make modern integrated circuits increasingly sensitive to temperature, voltage, and process variables. In the process of production and use, changes in process parameters, particle impact, aging phenomena, etc. will introduce physical defects to integrated circuits. Detecting these faults early and taking curative measures can make the circuit avoid errors such as short circuit or open circuit, and ultimately avoid failure behaviors such as packet loss, packet corruption, and even deadlock in the network on chip.

Before running multiple applications on a multi-core system-on-chip based on network-on-chip, these applications are usually divided into several tasks and assigned to a series of nodes of the multi-core system-on-chip according to certain mapping rules. Each resource node contains A processor and its adjacent routers. This process is called mapping. Mapping is a means of scheduling system resources on a multi-core chip. After the mapping is completed, there will be a large number of idle links and some idle routers in the network-on-chip. The links between the resource nodes occupied by different applications are idle because they have no communication load; secondly, there are some communication links inside the resource nodes occupied by the same application are idle; while those of the routers not occupied by applications Peripheral links are also idle. This enables in-circuit testing of the network on chip without negative effects.

The current test methods for network-on-chip are mainly router-based and link-based tests. A traditional network-on-chip consists of routers, links, and network-on-chip interfaces. The router-based test method usually needs to occupy a running resource node for testing, or complete testing and fault location through the cooperation of multiple resource nodes. This type of testing can cover the data path and control logic circuits in the network, but can negatively affect the running application. In addition, the link-based test method usually only tests the links between adjacent resource nodes, and cannot cover the control logic circuits located in the router, making the test not comprehensive enough.

Contents of the invention

In order to improve the testability and observability of an on-chip network without negatively affecting applications running on an on-chip network-based multi-core system, the invention proposes an on-chip network test package based on a bidirectional transmission path. The test package uses a bidirectional transmission path instead of a router and a link as the basic unit of the network on chip, and takes the bidirectional transmission path as the test object, where the transmission path is defined as the data path between adjacent network resource nodes and its functional coupling tight control circuit. The content of the test package of the present invention includes the on-chip network structure based on the bidirectional transmission path, the transmission path structure, the packager of the tested circuit, the built-in self-test platform and the test console.

The structure of the network on chip based on the two-way transmission path is shown in Fig. 1 . In this structure, transmission paths are used as the basic building blocks of the on-chip network, and connection points are formed where adjacent transmission paths meet. The network-on-chip of this structure has the same function as the traditional router-based network-on-chip. Controllers such as a processor and a memory are connected to a transmission path through an on-chip network interface (Network Interface, NI), and the transmission path interacts with other transmission paths at the connection point. The functions of the different transmission paths are independent of each other. In addition, in the test package of the present invention, in order to save the area and power consumption of the test circuit, the test components are placed at the connection point and shared by the transmission path connected to the connection point. The test suite includes the built-in self-test platform and the test console.

The overall structure of the present invention is shown in Figure 2. Each transmission path includes an independent data path between adjacent resource nodes and its functionally tightly coupled control logic. As shown in the figure, the transmission path structure can be divided into two ports and links between ports. Each port is divided into a channel control unit and a channel data unit, so that it is convenient to use different test methods to test different units, that is, use the preset test data packet to test the channel data unit, and use the pseudo-random test sequence to test the channel control unit . The hardware structure involved in the data path included in the transmission path is the link between the channel data unit and the port, and the hardware structure involved in the control logic circuit is the channel control unit. The channel data unit has a first-level output register level and an input buffer queue. The channel control unit has a finite state machine (finite state machine, FSM), a routing calculation unit (routing calculation unit, RC), and a virtual channel allocation unit (virtual-channel allocator, VA ), switch allocator (switch allocator, SA) and multiplexer. Among them, FSM is responsible for the transmission control after the current port input data packet, RC is responsible for calculating the routing direction of the most advanced data packet in the current port input buffer queue, VA is responsible for processing the virtual channel allocation request of data packets from other directions of the connection point, and SA is responsible for data packets from other directions. The transmission enable control of data packets in other directions of the connection point, and the multiplexer is responsible for the channel selection of incoming data packets in different directions.

The test packager in the present invention is shown in FIG. 3 . The sub-figure (a) in Fig. 3 shows the test wrapper of the channel data unit. The wrapper mainly consists of a multiplexer that semi-isolates the channel data unit, that is, the output register stage remains directly connected to the input buffer queue at the other end of the transmission path, while the control signals from the local port are isolated. When isolation is enabled, the output register stage accepts the test data packets from the channel data unit’s built-in self-test platform, and the data in the input buffer queue will enter the channel data unit’s built-in self-test platform as a test response, and a fixed signal is used to shield the input Status information of the cache queue. The sub-figure (b) in Fig. 3 shows the test wrapper of the channel control unit. The encapsulator is also composed of a multiplexer, which fully isolates the channel control unit, that is, all input and output signals of the channel control unit will pass through the encapsulator. When the isolation is enabled, the channel control unit accepts the test sequences and control signals from the channel control unit’s built-in self-test platform, and also uses fixed signals to shield responses to other control requests. The enabling sequence and enabling signals of the above wrappers are controlled by the test console, which is the manager of the entire testing process.

The built-in self-test platform of the channel control unit in the present invention is shown in FIG. 4 . The built-in self-test platform is based on the traditional STUMP (Self-Testing Using MISR and Parallel SRSG) structure. The platform uses a linear feedback shift register (LFSR) to generate a series of pseudo-random test sequences based on preset seeds. In order to save the area of the LFSR, the phase shifter is used to advance the phase shift of the pseudo-random sequence to generate more random sequences. In the present invention, multiple scan chains are inserted into the tested circuit, which can save a lot of testing time. At the response capture end of the built-in self-test, use the test response compressor (X-tolerant testresponse compactor) that can accommodate the variable value X to compress the test response, and then input the compressed value to the multiple input signature value register (multiple input signature register, MISR) to generate unique eigenvalues. Finally, in a test response analyzer (Test Response Analyzer, TRA), the actual test response characteristic value is compared with the ideal response characteristic value to judge whether there is a fault in the circuit under test. The entire BIST platform is controlled by an internal BIST controller.

The channel data unit built-in self-test platform uses the state machine to generate preset data packets through shift operations to test the data unit. The data packet generated by the built-in self-test platform of the current channel data unit passes through the output register level of the current port, and is input to the input buffer queue at the other end of the tested path through the data link, and is sent by the built-in self-test platform at the other end with the ideal data The content of the packet is compared to determine whether there is a fault in the current input data path.

Description of drawings

Fig. 1 is an example of the network on chip structure of the present invention.

Fig. 2 is the overall structure of the present invention.

Fig. 3 is a test wrapper of the present invention.

FIG. 4 is a BIST platform of the present invention.

Fig. 5 is the test flow of the present invention.

Detailed ways

FIG. 5 shows the test flow of the present invention, which is represented by the state transition diagram of the finite state machine of the test console in the present invention. The state machine is idle until the test components are initialized. When the test console receives the test enable trigger, it will enter the isolation handshake phase of the test component. First the test wrapper isolates the output register stage of the transmission path under test while waiting for the same operation at the other end of the path under test. Then clear the input buffer of the current port, and wait and confirm whether the component at the other end of the tested path has entered the same stage. The completion of the confirmation at both ends of the tested path indicates that the test synchronization handshake is successful, and then enters the triggering stage of the test. In the trigger test stage, the test console will trigger the built-in self-test platforms of the channel control and data units to test the path under test, and the channel data unit will be tested multiple times to cover intermittent faults. After all the circuits are tested, it enters the test result analysis stage, and finally returns to the idle state, and the tested path returns to the normal operation mode.

Claims (4)

1. a kind of network-on-chip based on bidirectional transmission path tests encapsulation, it is characterised in that the test of network-on-chip is double with one It is minimum test object to transmission path, and using bidirectional transmission path as the basic component units of network-on-chip, using being directed to Property build-in self-test method to transmission path carry out on-line testing.

2. bidirectional transmission path as described in claim 1, it is characterised in that function is mutually indepedent between transmission path, covers The data path and its close control logic circuit of Function Coupling between network-on-chip Adjacent resource node have been covered, and has shared and puts Set the test suite in tie point position.

3. targetedly build-in self-test method as described in claim 1, it is characterised in that draw the port of transmission path It is divided into data cell and control unit, functional test is carried out using the method for default test data packet transmission to data cell, Structural testing is carried out using Pseudo random test sequences to control unit.

4. test suite as described in claim 2, it is characterised in that test suite includes that data cell built-in self-test is flat Platform, control unit built-in self-test platform and test console, and the shared use of the transmission path by being connected to identical tie point, And test process is uniformly controlled by same test console.