CN108831643B - Low-cost high-precision adjustable resistor and control method - Google Patents
Low-cost high-precision adjustable resistor and control method Download PDFInfo
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Abstract
The invention provides a low-cost high-precision adjustable resistor, which comprises an MCU, a short-circuit switch and an adjustable resistor module, wherein the output end of the adjustable resistor module is provided with a group of resistor output interfaces, the short-circuit switch is connected in parallel with the outlet side of the adjustable resistor module, and a group of SOUT switches are connected in series between the short-circuit switch and the resistor output interfaces; the short-circuit switch, the adjustable resistor module and the SOUT switch are all connected with the MCU. The invention also provides a control method corresponding to the adjustable resistor. The invention has the advantages that: the digital adjustable resistor can be realized by adopting common devices, has wide resistance value selectable range and low resistance selecting cost, and can realize ultra-high-precision resistance output.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a low-cost high-precision digital adjustable resistor and a control method.
Background
Currently, an adjustable resistor is required to be used as a test source in the processes of testing the temperature, voltage resistance and the like of a circuit. However, the conventional adjustable resistor has the following defects:
1. the current adjustable resistor (such as TPL 501-1000) generally has 20% precision error, the precision is too low, the withstand voltage is also low (generally only tens of volts), and the current test requirement cannot be met at all; meanwhile, the precision errors of the adjustable resistors of different models are different, and the precision errors are not linear, so that the algorithm cannot be used for compensation;
2. the current digital adjustable resistor is connected in series, so that the resistor is realized by using a precise resistor with multiple resistance values when in use, which causes difficult resistor type selection and higher cost;
3. the current digital adjustable resistor cannot realize the resistance output of the 0Ω resistor;
4. the current digital adjustable resistor cannot realize the resistance output of infinite resistors;
5. most of the current adjustable resistor modules only have one communication interface, and cannot be compatible with various circuits, so that development cost is increased;
6. in the current numerical control adjustable resistor algorithm, resistors in multiple relation are directly subjected to series-parallel operation, and each resistor has a certain error, so that the loading precision is reduced; meanwhile, the conventional numerical control adjustable resistor algorithm does not consider the on-resistance of the switch, so that the loading precision is further reduced, and the loading error value cannot be known.
Disclosure of Invention
One of the technical problems to be solved by the invention is to provide a digital adjustable resistor with low cost and high precision, and the digital adjustable resistor can realize ultra-high precision resistance output.
The invention is realized in the following way: the digital adjustable resistor with low cost and high precision comprises an MCU, a short-circuit switch and an adjustable resistor module, wherein the output end of the adjustable resistor module is provided with a group of resistor output interfaces, the short-circuit switch is connected in parallel with the outlet side of the adjustable resistor module, and a group of SOUT switches are connected in series between the short-circuit switch and the resistor output interfaces; the short-circuit switch, the adjustable resistor module and the SOUT switch are all connected with the MCU.
Further, the adjustable resistance module comprises a plurality of resistors connected in series and a plurality of first-stage switches to a plurality of nth-stage switches; each resistor is connected with a first-stage switch in parallel to form a first-stage regulating unit;
every A1 continuous first-stage regulating unit is connected with a second-stage switch in parallel to form a second-stage regulating unit;
every A2 continuous second-stage regulating units are connected with a third-stage switch in parallel to form a third-stage regulating unit;
and so on;
until every Ai continuous N-1 level regulating unit is connected with an N level switch in parallel to form an N level regulating unit; wherein A1 to Ai are natural numbers greater than or equal to 2; n is a natural number greater than or equal to 3;
the first to nth stage switches are connected with the MCU.
Further, in each of the resistors connected in series, the selection range of the first resistor is between 0.6 and 0.9 times of the maximum resolution of the whole digital adjustable resistor, and the selection range of the resistor positioned at the rear one is between 0.6 and 0.9 times of the selection range of the resistor positioned at the front one; the maximum resolution of the digitally tunable resistor is the sum of the resistance values of all resistors.
The second technical problem to be solved by the invention is to provide a control method of a digital adjustable resistor with low cost and high precision, and the control method is used for improving the loading precision of the resistor.
The invention is realized in the following way: a control method of a digital tunable resistor with low cost and high precision, wherein the control method needs to use the digital tunable resistor, and the control method comprises the following steps:
step S1, calibrating resistance values of the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the N-stage switch;
s2, loading a target output value Res required to be used from external equipment by the MCU;
s3, switching off the short-circuit switch, the SOUT switch and the first-stage switch to the Nth-stage switch;
s4, carrying out minimum resolution output judgment on a target output value Res;
s5, carrying out maximum resolution output judgment on a target output value Res;
s6, compensating the on-resistance of the first-stage switch;
and S7, screening the resistor and the second-stage switch to the Nth-stage switch, and returning the final loading error value to the external equipment.
Further, the step S1 specifically includes:
measuring the resistance value of each resistor by using a universal meter, transmitting the measured resistance value of each resistor to an MCU, and calibrating the resistance value of each resistor by the MCU;
checking or measuring the conduction resistance of the short-circuit switch, transmitting the conduction resistance of the short-circuit switch to the MCU, and calibrating the conduction resistance of the short-circuit switch by the MCU;
checking or measuring the on-resistance of the SOUT switch, transmitting the on-resistance of the SOUT switch to the MCU, and calibrating the on-resistance of the SOUT switch by the MCU;
and checking or measuring the on-resistance of the first-stage switch to the N-stage switch, transmitting the on-resistance of the first-stage switch to the N-stage switch to the MCU, and calibrating the on-resistance of the first-stage switch to the N-stage switch by the MCU.
Further, the step S4 specifically includes:
step S41, judging whether a target output value Res is smaller than a minimum resolution Res_min, wherein the minimum resolution Res_min is the resistance value of the minimum resistance in the adjustable resistor or the sum of the on-resistances of the two SOUT switches, and if yes, executing step S42; if not, executing step S5;
step S42, controlling the short-circuit switch and the two SOUT switches to be closed; and subtracting the conduction impedance of the short-circuit switch from the target output value Res, subtracting the sum of the conduction impedances of the two SOUT switches to obtain a loading error value, and returning the loading error value to the external equipment.
Further, the step S5 specifically includes:
step S51, judging whether a target output value Res is larger than a maximum resolution Res_max and smaller than twice the maximum resolution Res_max, wherein the maximum resolution Res_max is the sum of resistance values of all resistors, and if so, entering step S52; if not, executing step S53;
step S52, controlling the two SOUT switches to be closed, subtracting a target output value Res from the maximum resolution Res_max to obtain a loading error value, and returning the loading error value to the external equipment;
step S53, judging whether the target output value Res is greater than or equal to the maximum resolution Res_max which is two times, if so, controlling the two SOUT switches to be disconnected, wherein the target output value Res is a loading error value, and outputting a resistor which is approximate to infinity to external equipment; if not, step S6 is performed.
Further, the step S6 specifically includes:
and acquiring the conduction impedance of each calibrated first-stage switch, and adding the conduction impedance of each first-stage switch into the target output value Res.
Further, the step S7 specifically includes:
step S71, determine whether m is smaller than n? If yes, go to step S72; if not, returning the target output value Res which is not calculated to the external equipment as a final loading error value; wherein n represents the number of resistors, m represents the number of times of cyclic judgment, and the initial value of m is 1;
step S72, participation judgment is carried out on the mth resistor;
step S73, processing the on-resistance of all the first-stage switches in the single second-stage switch; processing the on-resistance of all second stage switches within a single third stage switch; and so on;
until the on-resistance of all the N-1 level switches in the single N level switch is processed;
step S74, let m=m+1, and execute step S71.
Further, the step S72 specifically includes:
comparing the target output value Res with the resistance value of the mth resistor, and if the target output value Res is greater than or equal to the resistance value of the mth resistor, indicating that the mth resistor needs to participate in resistance adjustment, at the moment, disconnecting a first-stage switch connected in parallel with the mth resistor, marking the first-stage switch as a disconnected state, simultaneously subtracting the resistance value of the mth resistor from the target output value Res, subtracting the on-resistance of the corresponding first-stage switch to obtain a new target output value Res, and then entering step S73;
otherwise, if the target output value Res is smaller than the resistance value of the mth resistor, it is indicated that the mth resistor does not need to participate in the resistance adjustment, at this time, the first-stage switch connected in parallel with the mth resistor is closed, and the first-stage switch is marked as being in a closed state, and then step S73 is performed.
Further, the step S73 specifically includes:
step S731, determining whether A1 is divisible by m, where A1 represents the number of first-stage switches included in each second-stage switch, if A1 is divisible by m, determining the state of the first-stage switch included in the m/A1-th second-stage switch, if the first-stage switches included in the m/A1-th second-stage switch are all in a closed state, closing the m/A1-th second-stage switch, marking the m/A1-th second-stage switch as a closed state, subtracting the sum of on-resistances of the first-stage switches included in the m/A1-th second-stage switch from the target output value Res, and adding the on-resistances of the m/A1-th second-stage switch to obtain a new target output value Res, and then entering step S732; if the first-stage switch included in the m/A1 th second-stage switch is not in the closed state, the m/A1 th second-stage switch is opened, and the m/A1 th second-stage switch is marked as the opened state, and then the step S732 is entered; if A1 is not divisible by m, then step S732 is entered;
step S732, judging whether A2 can be divided by m/A1, wherein A2 represents the number of second-stage switches included in each third-stage switch, if A2 can be divided by m/A1, judging the state of the second-stage switch included in the m/(a 1×a2) third-stage switch, if the second-stage switches included in the m/(a 1×a2) third-stage switch are all in the closed state, closing the m/(a 1×a2) third-stage switch, marking the m/(a 1×a2) third-stage switch as the closed state, subtracting the sum of the on-resistances of the second-stage switches included in the m/(a 1×a2) third-stage switch from the target output value Res, adding the on-resistance of the m/(a 1×a2) third-stage switch to obtain a new target output value Res, and then entering step S733; if the second-stage switch included in the m/(A1 A2) th third-stage switch is not in the closed state, the m/(A1 A2) th third-stage switch is opened, and the m/(A1 A2) th third-stage switch is marked as in the open state, and then step S733 is performed; if A2 is not divisible by m/A1, then step S733 is entered;
and so on;
until step S73i, determining whether Ai is divisible by m/(A1 a 2..a (i-1)), ai represents the number of N-1-th switches included in each N-th switch, determining the state of N-1-th switches included in m/(A1 a 2..a) th switches if Ai is divisible by m/(A1 a 2..a (i-1)), and if m/(A1 a 2..a) th switches are all in the closed state, then closing the m/(A1 a 2) th level switch, marking the m/(A1 a 2) th level switch as closed, subtracting the sum of the on-resistances of the N-1 th level switches included in the m/(A1 a 2) th level switch from the target output value Res, and adding the on-resistances of the m/(A1 a 2) th level switch to obtain a new target output value Res, and then proceeding to step S74; if the N-1 th switch included in the m/(A1 a 2.) th switch is not all in the closed state, turning off the m/(A1 a 2.) th third switch, and marking the m/(A1 a 2.) th switch as the open state, and then proceeding to step S74; if Ai is not divisible by m/(a1.a2..a (i-1)), step S74 is entered.
The invention has the following advantages:
1. the digital adjustable resistor can be realized by adopting common devices, has wide resistance value selectable range and low resistance type selection cost, and can realize ultra-high-precision resistance output;
2. the digital adjustable resistor can easily realize 0 omega resistance output;
3. the digital adjustable resistor can easily realize infinite resistance output;
4. the digital adjustable resistor has various types of switches and resistors, and can easily select the switches and resistors with different voltage withstand grades as devices for designing circuits, so as to meet the voltage withstand requirements of different grades;
5. the digital adjustable resistor is controlled by the MCU, and the MCU can support various communication modes, so that the digital adjustable resistor can be compatible with various circuits, is more flexible to use and is beneficial to reducing development cost;
6. the control method can greatly improve the loading precision of the resistor, has strong applicability, and can acquire the loading error value in real time;
7. the control method of the invention calculates the on-resistance of all the switches, and uses calibration to self-calibrate the switches and the resistors, thereby realizing ultra-high precision resistor output.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a low cost, high precision digital tunable resistor of the present invention.
Fig. 2 is a control schematic block diagram of a low-cost high-precision digital adjustable resistor according to the present invention.
Fig. 3 is a schematic block diagram of a first stage regulator unit according to the present invention.
Fig. 4 is a schematic block diagram of a second stage regulator unit according to the present invention.
Fig. 5 is a schematic block diagram of a third stage regulator unit in accordance with the present invention.
Fig. 6 is a schematic block diagram of an nth stage regulator according to the present invention.
Fig. 7 is a circuit diagram of an embodiment of a low cost high precision digital tunable resistor according to the present invention.
FIG. 8 is a flow chart illustrating an implementation of a method for controlling a low-cost high-precision digital tunable resistor according to the present invention.
Detailed Description
Referring to fig. 1 to 8, a preferred embodiment of a low-cost and high-precision digital adjustable resistor according to the present invention includes an MCU, a short-circuit switch, and an adjustable resistor module, where an output end of the adjustable resistor module is provided with a set of resistor output interfaces; the short-circuit switch is connected in parallel with the outlet side of the adjustable resistance module, and a group of SOUT switches are connected in series between the short-circuit switch and the resistance output interface; the short-circuit switch, the adjustable resistor module and the SOUT switch are all connected with the MCU.
In a specific implementation, the whole digital adjustable resistor is controlled by the MCU, and multiple communication modes (such as SPI, IIC, SMBUS) can be supported due to the circuit mode of the MCU, and the MCU can uniformly process the data received by different communication interfaces, including changing resistance change and other operations. The resistor output interface is used for realizing the output of the resistor value; the short-circuit switch is used for avoiding the loop impedance of the whole adjustable resistor, so that the output of the 0 omega resistor is realized; the SOUT switch is used for realizing the loop disconnection of the whole adjustable resistor, thereby realizing the effect of outputting infinitely large resistance values.
The adjustable resistor module comprises a plurality of resistors (R1-Rn) connected in series, a plurality of first-stage switches and a plurality of N-th-stage switches; each resistor is connected with a first-stage switch in parallel to form a first-stage adjusting unit (namely a minimum adjustable unit); in the implementation, when a certain resistor is needed, the first-stage switch corresponding to the resistor is opened; if not, closing the first-stage switch corresponding to the resistor so as to realize the short-circuit operation of the resistor;
every A1 continuous first-stage regulating unit is connected with a second-stage switch in parallel to form a second-stage regulating unit; in the implementation, when the first-stage switches in a certain A1 continuous first-stage adjusting units are all in a closed state, the corresponding second-stage switches can be closed so as to short-circuit the A1 conducted first-stage switches, thereby achieving the purpose of eliminating the conduction impedance of the first-stage switches;
every A2 continuous second-stage regulating units are connected with a third-stage switch in parallel to form a third-stage regulating unit; in the implementation, when the second-stage switches in a certain A2 continuous second-stage adjusting units are all in a closed state, the corresponding third-stage switch can be closed so as to short-circuit the A2 conducted second-stage switches, thereby achieving the purpose of eliminating the conduction impedance of the second-stage switches;
and so on;
until every Ai continuous N-1 level regulating unit is connected with an N level switch in parallel to form an N level regulating unit; wherein A1 to Ai are natural numbers greater than or equal to 2; n is a natural number greater than or equal to 3; when the N-1 level switch in a certain Ai continuous N-1 level regulating unit is in a closed state, the corresponding N level switch can be closed so as to short the Ai conducted N-1 level switch, thereby achieving the purpose of eliminating the conduction impedance of the N-1 level switch;
the first to nth stage switches are connected to the MCU to control the first to nth stage switches through the MCU.
In each resistor connected in series, the selection range of the first resistor is between 0.6 and 0.9 times of the maximum resolution of the whole digital adjustable resistor, and the selection range of the resistor positioned at the rear one is between 0.6 and 0.9 times of the selection range of the resistor positioned at the front one; the maximum resolution of the digitally tunable resistor is the sum of the resistance values of all resistors. Since each resistor has an accuracy error of about 20%, the accuracy error can be reduced well by setting the selected value range of the resistor located at the rear one to be between 0.6 times and 0.9 times the selected value range of the resistor located at the front one. For example, the maximum resolution of the digitally tunable resistor is X ohms, then the R1 is selected to be between 0.6 and 0.9 times X ohms, the R2 is selected to be between 0.6 and 0.9 times R1, and so on.
The adjustable resistance module of the present invention is further described below with an example of an implementation:
in the digital adjustable resistor of this example, a set of resistor output interfaces are included at the output of the adjustable resistor module; the short-circuit switch M_ss is connected in parallel to the outlet side of the adjustable resistance module, and a group of SOUT switches M_sout are connected in series between the short-circuit switch M_ss and the resistance output interface; the adjustable resistor module comprises resistors R1-R8, first-stage switches SA 1-SA 8, second-stage switches SB 1-SB 4 and third-stage switches SC 1-SC 2. Wherein, the resistors R1-R8 are connected in series; the resistor R1 and the first-stage switch SA1 are connected in parallel to form a first-stage adjusting unit, the resistor R2 and the first-stage switch SA2 are connected in parallel to form a second first-stage adjusting unit, and the resistor R8 and the first-stage switch SA8 are connected in parallel to form an eighth first-stage adjusting unit; the first-stage adjusting unit and the second first-stage adjusting unit are connected with the first second-stage switch SB1 in parallel to form a first second-stage adjusting unit, and the seventh first-stage adjusting unit and the eighth first-stage adjusting unit are connected with the fourth second-stage switch SB4 in parallel to form a fourth second-stage adjusting unit; the first second-stage regulating unit and the second-stage regulating unit are connected with the first third-stage switch SC1 in parallel to form a first third-stage regulating unit, and the third second-stage regulating unit and the fourth second-stage regulating unit are connected with the second third-stage switch SC2 in parallel to form a second third-stage regulating unit.
The preferred embodiment of the control method of the digital adjustable resistor with low cost and high precision of the invention is that the control method needs to use the digital adjustable resistor, and the control method comprises the following steps:
step S1, calibrating resistance values of the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the N-stage switch; the loading error of the system can be well reduced by calibrating the resistance values of the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the Nth-stage switch;
s2, loading a target output value Res required to be used from external equipment by the MCU;
step S3, the short-circuit switch, the SOUT switch, the first-stage switch and the N-stage switch are disconnected, so that the whole system is in an initial state, and all the switches are disconnected by default in the follow-up description; of course, in the implementation, the short-circuit switch, the SOUT switch and the first to nth stage switches may be closed.
S4, carrying out minimum resolution output judgment on a target output value Res;
s5, carrying out maximum resolution output judgment on a target output value Res;
s6, compensating the on-resistance of the first-stage switch;
and S7, screening the resistor and the second-stage switch to the Nth-stage switch, and returning the final loading error value to the external equipment.
The step S1 specifically includes:
measuring the resistance value of each resistor by using a universal meter, transmitting the measured resistance value of each resistor to an MCU, and calibrating the resistance value of each resistor by the MCU;
checking or measuring the conduction resistance of the short-circuit switch, transmitting the conduction resistance of the short-circuit switch to the MCU, and calibrating the conduction resistance of the short-circuit switch by the MCU;
checking or measuring the on-resistance of the SOUT switch, transmitting the on-resistance of the SOUT switch to the MCU, and calibrating the on-resistance of the SOUT switch by the MCU;
and checking or measuring the on-resistance of the first-stage switch to the N-stage switch, transmitting the on-resistance of the first-stage switch to the N-stage switch to the MCU, and calibrating the on-resistance of the first-stage switch to the N-stage switch by the MCU.
After the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the nth-stage switch are calibrated, when the corresponding resistance value or the on-resistance is required to be used, the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the nth-stage switch can be directly obtained from the MCU.
The step S4 specifically includes:
step S41, judging whether a target output value Res is smaller than a minimum resolution Res_min, wherein the minimum resolution Res_min is the resistance value of the minimum resistance in the adjustable resistor or the sum of the on-resistances of the two SOUT switches, and if yes, executing step S42; if not, executing step S5;
step S42, controlling the short-circuit switch and the two SOUT switches to be closed; and subtracting the conduction impedance of the short-circuit switch from the target output value Res, subtracting the sum of the conduction impedances of the two SOUT switches to obtain a loading error value, and returning the loading error value to the external equipment.
For example, the MCU loads a target output value Res of 3 Ω, a minimum resistance value of 2 Ω, and a sum of on-resistances of the two SOUT switches of 1.6 Ω. Since the target output value Res is smaller than the minimum resolution res_min, it is necessary to control the short-circuit switch and the two SOUT switches to be closed and return the loading error value=3Ω -2Ω -1.6Ω= -0.6Ω to the external device.
The step S5 specifically includes:
step S51, judging whether a target output value Res is larger than a maximum resolution Res_max and smaller than twice the maximum resolution Res_max, wherein the maximum resolution Res_max is the sum of resistance values of all resistors, and if so, entering step S52; if not, executing step S53;
step S52, controlling the two SOUT switches to be closed, subtracting a target output value Res from the maximum resolution Res_max to obtain a loading error value, and returning the loading error value to the external equipment;
step S53, judging whether the target output value Res is greater than or equal to the maximum resolution Res_max which is two times, if so, controlling the two SOUT switches to be disconnected, wherein the target output value Res is a loading error value, and outputting a resistor which is approximate to infinity to external equipment; if not, step S6 is performed.
For example, the MCU loads a target output value Res of 3MΩ and a maximum resolution Res_max of 2MΩ. Since the target output value Res is greater than the maximum resolution res_max and less than twice the maximum resolution res_max, it is necessary to control the two SOUT switches to be closed and return the loading error value=3mΩ -2mΩ=1mΩ to the external device. If the target output value Res loaded by the MCU is 5MΩ at this time, the target output value Res is larger than twice the maximum resolution Res_max, so that the two SOUT switches need to be controlled to be turned off, and the system outputs an approximately infinite resistance value.
The step S6 specifically includes:
the method comprises the steps of obtaining the conduction impedance of each calibrated first-stage switch, adding the conduction impedance of each first-stage switch into a target output value Res, namely, adding the conduction impedance of each first-stage switch into the target output value Res uniformly, and compensating the conduction impedance of each first-stage switch to improve the loading precision of the digital adjustable resistor.
The step S7 specifically includes:
step S71, determine whether m is smaller than n? If yes, go to step S72; if not, returning the target output value Res which is not calculated to the external equipment as a final loading error value; wherein n represents the number of resistors, m represents the number of times of cyclic judgment, and the initial value of m is 1;
step S72, the mth resistor is participated in judgment, namely, a resistor participated in regulation is selected from n resistors according to a target output value Res;
step S73, processing the on-resistance of all the first-stage switches in the single second-stage switch; processing the on-resistance of all second stage switches within a single third stage switch; and so on;
until the on-resistance of all the N-1 level switches in the single N level switch is processed;
step S74, let m=m+1, and execute step S71.
The step S72 specifically includes:
comparing the target output value Res with the resistance value of the mth resistor (for example, when the first comparison is performed, the target output value Res needs to be compared with the resistance value of the first resistor), if the target output value Res is greater than or equal to the resistance value of the mth resistor, the mth resistor needs to participate in resistance adjustment, at this time, the first-stage switch connected in parallel with the mth resistor is disconnected, that is, the mth resistor is connected in a loop to participate in adjustment, and the first-stage switch is marked as an off state, meanwhile, the target output value Res is subtracted by the resistance value of the mth resistor first, then the on resistance of the corresponding first-stage switch is subtracted to obtain a new target output value Res, and then step S73 is entered; the subtracting of the resistance value of the mth resistor is to subtract the resistance participating in adjustment, and the subtracting of the on-resistance of the corresponding first-stage switch is to improve the loading accuracy of the system.
Otherwise, if the target output value Res is smaller than the resistance value of the mth resistor, it is indicated that the mth resistor does not need to participate in resistance adjustment, and at this time, the first-stage switch connected in parallel with the mth resistor is closed, that is, the mth resistor is shorted, and the first-stage switch is marked as being in a closed state, and then step S73 is performed.
The step S73 specifically includes:
step S731, determining whether A1 is divisible by m, where A1 represents the number of first-stage switches included in each second-stage switch, if A1 is divisible by m (for example, the value of A1 is 2, the value of m is 6), determining the state of the first-stage switch included in the m/A1-th second-stage switch, if the first-stage switch included in the m/A1-th second-stage switch is in a closed state (the state of the first-stage switch is marked in step S72), closing the m/A1-th second-stage switch, so as to eliminate the on-resistance of the first-stage switch included in the m/A1-th second-stage switch, marking the m/A1-th second-stage switch as a closed state, simultaneously subtracting the sum of the on-resistances of the first-stage switches included in the m/A1-th second-stage switch from the target output value Res, adding the on-resistance of the m/A1-th second-stage switch to obtain a new target output value Res, and entering step S; if the first-stage switch included in the m/A1 th second-stage switch is not in the closed state, the m/A1 th second-stage switch is opened, and the m/A1 th second-stage switch is marked as the opened state, and then the step S732 is entered; if A1 is not divisible by m, then step S732 is entered;
step S732, judging whether A2 can be divided by m/A1, where A2 represents the number of second-stage switches included in each third-stage switch, if A2 can be divided by m/A1 (for example, the value of A1 is 3, the value of A2 is 2, and the value of m is 12), judging the state of the second-stage switch included in the m/(a 1×a2) third-stage switch, and if the second-stage switches included in the m/(a 1×a2) third-stage switch are all in a closed state, closing the m/(a 1×a2) third-stage switches to eliminate the on-resistance of the second-stage switch included in the m/(a 1×a2) third-stage switch, marking the third-stage switch as in a closed state, subtracting the target output value Res from the on-state of each second-stage switch included in the m/(a 1×a2) third-stage switch, and adding the m/(a 1×a2) third-stage switch to the target output value Res to obtain a new on-state impedance, and then entering a step S733; if the second-stage switch included in the m/(A1 A2) th third-stage switch is not in the closed state, the m/(A1 A2) th third-stage switch is opened, and the m/(A1 A2) th third-stage switch is marked as in the open state, and then step S733 is performed; if A2 is not divisible by m/A1, then step S733 is entered;
and so on;
until step S73i, determining whether Ai is divisible by m/(A1 a 2..a (i-1)), ai represents the number of N-1-th switches included in each N-th switch, determining the state of N-1-th switches included in m/(A1 a 2..a) th switches if Ai is divisible by m/(A1 a 2..a (i-1)), and closing m/(A1 a 2..a) th switches if N-1-th switches included in m/(A1 a 2..a) th switches are all closed, the on-resistance of the N-1 th switch included in the m/(A1 a 2) th switch is eliminated, the m/(A1 a 2) th switch is marked as being in a closed state, meanwhile, the target output value Res is subtracted from the sum of the on-resistance of the N-1 th switch included in the m/(A1 a 2) th switch, and the on-resistance of the N-1 th switch is added to the m/(A1 a 2) th switch to obtain a new target output value Res, and then the step S74 is proceeded; if the N-1 th switch included in the m/(A1 a 2.) th switch is not all in the closed state, turning off the m/(A1 a 2.) th third switch, and marking the m/(A1 a 2.) th switch as the open state, and then proceeding to step S74; if Ai is not divisible by m/(a1.a2..a (i-1)), step S74 is entered.
In summary, the invention has the following advantages:
1. the digital adjustable resistor can be realized by adopting common devices, has wide resistance value selectable range and low resistance type selection cost, and can realize ultra-high-precision resistance output;
2. the digital adjustable resistor can easily realize 0 omega resistance output;
3. the digital adjustable resistor can easily realize infinite resistance output;
4. the digital adjustable resistor has various types of switches and resistors, and can easily select the switches and resistors with different voltage withstand grades as devices for designing circuits, so as to meet the voltage withstand requirements of different grades;
5. the digital adjustable resistor is controlled by the MCU, and the MCU can support various communication modes, so that the digital adjustable resistor can be compatible with various circuits, is more flexible to use and is beneficial to reducing development cost;
6. the control method can greatly improve the loading precision of the resistor, has strong applicability, and can acquire the loading error value in real time;
7. the control method of the invention calculates the on-resistance of all the switches, and uses calibration to self-calibrate the switches and the resistors, thereby realizing ultra-high precision resistor output.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (7)
1. A control method of a digital adjustable resistor with low cost and high precision is characterized in that: the control method is characterized in that the control method comprises the following steps of using a low-cost high-precision digital adjustable resistor, comprising an MCU, a short-circuit switch and an adjustable resistor module, wherein the output end of the adjustable resistor module is provided with a group of resistor output interfaces, the short-circuit switch is connected in parallel to the outlet side of the adjustable resistor module, and a group of SOUT switches are connected in series between the short-circuit switch and the resistor output interfaces; the short-circuit switch, the adjustable resistor module and the SOUT switch are all connected with the MCU;
the adjustable resistance module comprises a plurality of resistors connected in series, a plurality of first-stage switches and a plurality of N-th-stage switches; each resistor is connected with a first-stage switch in parallel to form a first-stage regulating unit;
every A1 continuous first-stage regulating unit is connected with a second-stage switch in parallel to form a second-stage regulating unit;
every A2 continuous second-stage regulating units are connected with a third-stage switch in parallel to form a third-stage regulating unit;
and so on;
until every Ai continuous N-1 level regulating unit is connected with an N level switch in parallel to form an N level regulating unit; wherein A1 to Ai are natural numbers greater than or equal to 2; n is a natural number greater than or equal to 3;
the first-stage switches to the N-th-stage switches are connected with the MCU;
in each resistor connected in series, the selection range of the first resistor is between 0.6 and 0.9 times of the maximum resolution of the whole digital adjustable resistor, and the selection range of the resistor positioned at the rear one is between 0.6 and 0.9 times of the selection range of the resistor positioned at the front one; the maximum resolution of the digital adjustable resistor is the sum of the resistance values of all resistors;
the control method comprises the following steps:
step S1, calibrating resistance values of the short-circuit switch, the SOUT switch, the resistor and the first-stage switch to the N-stage switch;
s2, loading a target output value Res required to be used from external equipment by the MCU;
s3, switching off the short-circuit switch, the SOUT switch and the first-stage switch to the Nth-stage switch;
s4, carrying out minimum resolution output judgment on a target output value Res;
s5, carrying out maximum resolution output judgment on a target output value Res;
s6, compensating the on-resistance of the first-stage switch;
and S7, screening the resistor and the second-stage switch to the Nth-stage switch, and returning the final loading error value to the external equipment.
2. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 1, wherein: the step S1 specifically comprises the following steps:
measuring the resistance value of each resistor by using a universal meter, transmitting the measured resistance value of each resistor to an MCU, and calibrating the resistance value of each resistor by the MCU;
checking or measuring the conduction resistance of the short-circuit switch, transmitting the conduction resistance of the short-circuit switch to the MCU, and calibrating the conduction resistance of the short-circuit switch by the MCU;
checking or measuring the on-resistance of the SOUT switch, transmitting the on-resistance of the SOUT switch to the MCU, and calibrating the on-resistance of the SOUT switch by the MCU;
and checking or measuring the on-resistance of the first-stage switch to the N-stage switch, transmitting the on-resistance of the first-stage switch to the N-stage switch to the MCU, and calibrating the on-resistance of the first-stage switch to the N-stage switch by the MCU.
3. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 2, wherein: the step S4 specifically includes:
step S41, judging whether a target output value Res is smaller than a minimum resolution Res_min, wherein the minimum resolution Res_min is the resistance value of the minimum resistance in the adjustable resistor or the sum of the on-resistances of the two SOUT switches, and if yes, executing step S42; if not, executing step S5;
step S42, controlling the short-circuit switch and the two SOUT switches to be closed; and subtracting the conduction impedance of the short-circuit switch from the target output value Res, subtracting the sum of the conduction impedances of the two SOUT switches to obtain a loading error value, and returning the loading error value to the external equipment.
4. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 2, wherein: the step S5 specifically includes:
step S51, judging whether a target output value Res is larger than a maximum resolution Res_max and smaller than twice the maximum resolution Res_max, wherein the maximum resolution Res_max is the sum of resistance values of all resistors, and if so, entering step S52; if not, executing step S53;
step S52, controlling the two SOUT switches to be closed, subtracting a target output value Res from the maximum resolution Res_max to obtain a loading error value, and returning the loading error value to the external equipment;
step S53, judging whether the target output value Res is greater than or equal to the maximum resolution Res_max which is two times, if so, controlling the two SOUT switches to be disconnected, wherein the target output value Res is a loading error value, and outputting a resistor which is approximate to infinity to external equipment; if not, executing step S6;
the step S6 specifically includes:
and acquiring the conduction impedance of each calibrated first-stage switch, and adding the conduction impedance of each first-stage switch into the target output value Res.
5. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 4, wherein: the step S7 specifically includes:
step S71, judging whether m is smaller than n, if yes, executing step S72; if not, returning the target output value Res which is not calculated to the external equipment as a final loading error value; wherein n represents the number of resistors, m represents the number of times of cyclic judgment, and the initial value of m is 1;
step S72, participation judgment is carried out on the mth resistor;
step S73, processing the on-resistance of all the first-stage switches in the single second-stage switch; processing the on-resistance of all second stage switches within a single third stage switch; and so on;
until the on-resistance of all the N-1 level switches in the single N level switch is processed;
step S74, let m=m+1, and execute step S71.
6. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 5, wherein: the step S72 specifically includes:
comparing the target output value Res with the resistance value of the mth resistor, and if the target output value Res is greater than or equal to the resistance value of the mth resistor, indicating that the mth resistor needs to participate in resistance adjustment, at the moment, disconnecting a first-stage switch connected in parallel with the mth resistor, marking the first-stage switch as a disconnected state, simultaneously subtracting the resistance value of the mth resistor from the target output value Res, subtracting the on-resistance of the corresponding first-stage switch to obtain a new target output value Res, and then entering step S73;
otherwise, if the target output value Res is smaller than the resistance value of the mth resistor, it is indicated that the mth resistor does not need to participate in the resistance adjustment, at this time, the first-stage switch connected in parallel with the mth resistor is closed, and the first-stage switch is marked as being in a closed state, and then step S73 is performed.
7. A method of controlling a low cost, high precision, digitally tunable resistor according to claim 5, wherein: the step S73 specifically includes:
step S731, determining whether A1 is divisible by m, where A1 represents the number of first-stage switches included in each second-stage switch, if A1 is divisible by m, determining the state of the first-stage switch included in the m/A1-th second-stage switch, if the first-stage switches included in the m/A1-th second-stage switch are all in a closed state, closing the m/A1-th second-stage switch, marking the m/A1-th second-stage switch as a closed state, subtracting the sum of on-resistances of the first-stage switches included in the m/A1-th second-stage switch from the target output value Res, and adding the on-resistances of the m/A1-th second-stage switch to obtain a new target output value Res, and then entering step S732; if the first-stage switch included in the m/A1 th second-stage switch is not in the closed state, the m/A1 th second-stage switch is opened, and the m/A1 th second-stage switch is marked as the opened state, and then the step S732 is entered; if A1 is not divisible by m, then step S732 is entered;
step S732, judging whether A2 can be divided by m/A1, wherein A2 represents the number of second-stage switches included in each third-stage switch, if A2 can be divided by m/A1, judging the state of the second-stage switch included in the m/(a 1×a2) third-stage switch, if the second-stage switches included in the m/(a 1×a2) third-stage switch are all in the closed state, closing the m/(a 1×a2) third-stage switch, marking the m/(a 1×a2) third-stage switch as the closed state, subtracting the sum of the on-resistances of the second-stage switches included in the m/(a 1×a2) third-stage switch from the target output value Res, adding the on-resistance of the m/(a 1×a2) third-stage switch to obtain a new target output value Res, and then entering step S733; if the second-stage switch included in the m/(A1 A2) th third-stage switch is not in the closed state, the m/(A1 A2) th third-stage switch is opened, and the m/(A1 A2) th third-stage switch is marked as in the open state, and then step S733 is performed; if A2 is not divisible by m/A1, then step S733 is entered;
and so on;
until step S73i, determining whether Ai is divisible by m/(A1 a 2..a (i-1)), ai represents the number of N-1-th switches included in each N-th switch, determining the state of N-1-th switches included in m/(A1 a 2..a) th switches if Ai is divisible by m/(A1 a 2..a (i-1)), and if m/(A1 a 2..a) th switches are all in the closed state, then closing the m/(A1 a 2) th level switch, marking the m/(A1 a 2) th level switch as closed, subtracting the sum of the on-resistances of the N-1 th level switches included in the m/(A1 a 2) th level switch from the target output value Res, and adding the on-resistances of the m/(A1 a 2) th level switch to obtain a new target output value Res, and then proceeding to step S74; if the N-1 th switch included in the m/(A1 a 2.) th switch is not all in the closed state, turning off the m/(A1 a 2.) th third switch, and marking the m/(A1 a 2.) th switch as the open state, and then proceeding to step S74; if Ai is not divisible by m/(a1.a2..a (i-1)), step S74 is entered.
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