CN108831516B - Flash memory control method and flash memory control device - Google Patents
Flash memory control method and flash memory control device Download PDFInfo
- Publication number
- CN108831516B CN108831516B CN201810657590.3A CN201810657590A CN108831516B CN 108831516 B CN108831516 B CN 108831516B CN 201810657590 A CN201810657590 A CN 201810657590A CN 108831516 B CN108831516 B CN 108831516B
- Authority
- CN
- China
- Prior art keywords
- programming
- grouping
- programmed
- group
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 234
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000003860 storage Methods 0.000 claims abstract description 57
- 238000012360 testing method Methods 0.000 claims description 26
- 238000012545 processing Methods 0.000 claims description 6
- 238000004458 analytical method Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000005034 decoration Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a flash memory control method and a flash memory control device. The flash memory control method comprises the following steps: acquiring the grouping programming times, wherein the grouping programming times are the maximum programming times of a plurality of storage units to be programmed, and the inter-group aliasing degree of the storage units to be programmed is kept within a grouping tolerance in the grouping programming process; judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouping programming times, if so, grouping a plurality of storage units to be programmed according to different programming speeds; the packet programming is started. The invention can effectively improve the programming speed and ensure the performance of the flash memory while reducing the programming error rate.
Description
Technical Field
The present invention relates to the field of semiconductor control technologies, and in particular, to a flash memory control method and a flash memory control device.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
With the continuous popularization of digital products such as mobile phones and tablet computers and the demand of people for large data storage space, bit storage modes are gradually eliminated. Multi-bit flash memories, such as MLC (Multi-Level Cell) in which one memory Cell stores 2-bit information, TLC (Trinary-Level Cell) in which one memory Cell stores 3-bit information, etc., have been increasingly widely used due to their capability of storing Multi-bit information in one memory Cell.
However, in the manufacturing process of the flash memory, the programming speeds of different memory cells are inconsistent due to different device process parameters, and the aliasing of the threshold voltages among different memory cells is easily caused, so that the occurrence of programming errors is caused. Because the threshold voltage distribution of the multi-bit flash memory is narrow, aliasing errors are more likely to occur, and finally the failure of the flash memory is caused.
Therefore, how to reduce program aliasing among memory cells and ensure the performance of the flash memory is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention provides a flash memory control method and a flash memory control device, which are used for reducing the problem of program aliasing among memory units and ensuring the performance of a flash memory.
In order to solve the above problems, the present invention provides a flash memory control method, comprising the steps of:
acquiring the grouping programming times, wherein the grouping programming times are the maximum programming times of a plurality of storage units to be programmed, and the inter-group aliasing degree of the storage units to be programmed is kept within a grouping tolerance in the grouping programming process;
judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouping programming times, if so, grouping a plurality of storage units to be programmed according to different programming speeds;
and performing grouping programming according to grouping information of a plurality of memory cells to be programmed.
Preferably, the grouping margin is a preset threshold voltage; the specific steps for acquiring the times of the group programming comprise:
providing a plurality of test memory cells, wherein the test memory cells are programmed at least once;
dividing the plurality of test memory cells into a first memory cell group and a second memory cell group according to different programming speeds, wherein the programming speed of the first memory cell group is greater than that of the second memory cell group;
performing a one-time group program on the first and second memory cell groups;
and judging whether the difference between the threshold voltage corresponding to the first storage unit group and the threshold voltage corresponding to the second storage unit group after one-time grouping programming is larger than or equal to the grouping tolerance, and if so, taking the current grouping programming frequency as the grouping programming frequency.
Preferably, the specific step of obtaining the number of times of packet programming further includes:
and judging whether the difference between the threshold voltage corresponding to the first memory cell group and the threshold voltage corresponding to the second memory cell group after one-time grouping programming is larger than or equal to the grouping tolerance, and if not, performing the next-time grouping programming on the first memory cell group and the second memory cell group.
Preferably, the method further comprises the following steps:
performing one-time common programming on a plurality of memory cells to be programmed;
and judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouped programming times, and if not, carrying out the next common programming on the storage units to be programmed.
Preferably, the specific step of determining whether the remaining programming times of the to-be-programmed memory cells are less than or equal to the grouped programming times, and if so, grouping the to-be-programmed memory cells according to the difference of the programming speeds includes:
acquiring the total programming times required by the to-be-programmed storage unit to reach a target threshold voltage;
and judging whether the current programming times are larger than or equal to the difference between the total programming times and the grouping programming times, if so, grouping a plurality of memory cells to be programmed according to different programming speeds.
Preferably, the group programming includes adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed.
In order to solve the above problem, the present invention further provides a flash memory control device, including:
the acquisition module is used for acquiring the grouping programming times, wherein the grouping programming times are the maximum programming times of the inter-group aliasing degree of a plurality of storage units to be programmed in the grouping programming process, and the inter-group aliasing degree is kept within a grouping tolerance;
the control module is connected with the acquisition module and used for judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouping programming times, and if so, the storage units to be programmed are grouped according to different programming speeds;
and the grouping programming module is connected with the control module and is used for grouping programming the grouping information of the storage units to be programmed according to the control module.
Preferably, the grouping margin is a preset threshold voltage; the acquisition module includes:
an input unit for inputting a plurality of test memory cells, the test memory cells being programmed at least once;
the grouping unit is connected with the input unit and is used for dividing the plurality of test storage units into a first storage unit group and a second storage unit group according to different programming speeds, and the programming speed of the first storage unit group is greater than that of the second storage unit group;
the processing unit is connected with the grouping unit and is used for performing one-time grouping programming on the first storage unit group and the second storage unit group;
and the judging unit is connected with the processing unit and used for judging whether the difference between the threshold voltage corresponding to the first storage unit group and the threshold voltage corresponding to the second storage unit group after one-time grouping programming is greater than or equal to the grouping tolerance, and if so, taking the current grouping programming frequency as the grouping programming frequency.
Preferably, the determining unit is further configured to determine whether a difference between a threshold voltage corresponding to the first memory cell group and a threshold voltage corresponding to the second memory cell group after one-time group programming is greater than or equal to the grouping tolerance, and if not, perform the next-time group programming on the first memory cell group and the second memory cell group.
Preferably, the control module is further configured to, after performing one-time co-programming on the plurality of memory cells to be programmed, determine whether the remaining programming times of the memory cells to be programmed are less than or equal to the grouped programming times, and if not, perform the next co-programming on the plurality of memory cells to be programmed.
Preferably, the control module includes:
the obtaining unit is used for obtaining the total programming times required by the to-be-programmed storage unit to reach the target threshold voltage;
and the analysis unit is connected with the acquisition unit and used for judging whether the current programming frequency is greater than the difference between the total programming frequency and the grouping programming frequency, and if so, grouping the storage units to be programmed according to different programming speeds.
Preferably, the group programming includes adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed.
The flash memory control method and the flash memory control device provided by the invention can confirm the time of the grouping programming of the memory cells according to the grouping tolerance by setting the grouping tolerance, control the programming aliasing degree of the memory cells within the grouping tolerance, reduce the programming error rate, effectively improve the programming speed and ensure the performance of the flash memory.
Drawings
FIG. 1 is a flow chart of a method for controlling a flash memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a programming process of a memory cell to be programmed according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating the process of obtaining the number of times of programming in groups according to the embodiment of the present invention;
FIG. 4 is a flow chart illustrating a programming process in accordance with an embodiment of the present invention;
FIG. 5A is a graph illustrating a comparison of programming speed of an embodiment of the present invention with a conventional programming speed;
FIG. 5B is a graph illustrating a comparison of a program error rate of an embodiment of the present invention with a conventional program error rate;
FIG. 6 is a schematic structural diagram of a flash memory control device according to an embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of a flash memory control method and a flash memory control device according to the present invention with reference to the accompanying drawings.
In order to avoid the situation that threshold voltage aliasing occurs due to different programming speeds of different memory cells, generally, the memory cells are grouped according to the programming speed of the memory cells, different programming voltages are applied to the memory cells in different groups to control the programming speed of the memory cells, and the threshold voltage aliasing of the multi-bit flash memory is effectively reduced.
Currently, there are two ways to group memory cells: firstly, grouping is carried out according to the programming speed after one-step programming; second, grouping is performed when programming to near the target threshold voltage. The first grouping mode can effectively prevent the problem of over-programming of a storage unit with a higher programming speed, and can reduce the error rate of the flash memory to a certain extent; however, as the number of times of programming is increased, threshold voltage aliasing between different groups of memory cells occurs in the early grouping of memory cells, so that the memory cells with high programming speed and the memory cells with low programming speed cannot be distinguished, and thus the grouping fails. The second grouping mode can obtain a faster programming speed due to the fact that the overall programming times are reduced; however, grouping is performed near the end of programming, and memory cells with faster programming speeds have already been programmed to the wrong state, resulting in an increase in bit error rate.
In order to improve the programming speed and reduce the bit error rate at the same time, the present embodiment provides a flash memory control method, fig. 1 is a flowchart of the flash memory control method according to the present embodiment, and fig. 2 is a schematic diagram of a programming process of a to-be-programmed memory cell according to the present embodiment. The flash memory in the present embodiment is preferably a 3D NAND memory. As shown in fig. 1 and 2, the method for controlling a flash memory according to this embodiment includes the following steps:
step S11, obtaining a grouping programming number, which is a maximum programming number for which the inter-group aliasing degree of the memory cells to be programmed is kept within a grouping tolerance during the grouping programming.
The grouping tolerance refers to the allowable inter-group aliasing degree in the grouping programming process between two groups of memory cells with different programming speeds. Specifically, since the programming speed distribution of each group of memory cells is within a range during the group programming process, two different groups of memory cells may have overlapping speed distribution ranges during the group programming process, and the group tolerance defines the degree of overlap of the speed distribution ranges of the two groups of memory cells. If the grouping tolerance is exceeded, the degree of aliasing between two sets of memory cells with different programming speeds is too large, and it may be impossible to distinguish between two sets of memory cells with different programming speeds, resulting in a grouping failure. In this embodiment, the specific value of the grouping margin may be set by a person skilled in the art according to factors such as a specific type of the memory cell or a programming method of the memory cell, and this embodiment is not limited thereto. The specific type of the grouping margin is not limited in this embodiment, as long as the grouping margin can reflect the amount of aliasing between two groups of memory cells with different programming speeds.
Fig. 3 is a flow chart illustrating the acquisition of the number of times of the group program according to the embodiment of the present invention. In order to simplify the control step of the flash memory, preferably, the grouping margin is a preset threshold voltage, as shown in fig. 3, the specific step of obtaining the grouping programming times includes:
step S31, providing a plurality of test memory cells, wherein the test memory cells are programmed at least once;
step S32, dividing the plurality of test memory cells into a first memory cell group 21 and a second memory cell group 22 according to different programming speeds, wherein the programming speed of the first memory cell group 21 is greater than the programming speed of the second memory cell group 22;
step S33, performing a group-once programming on the first and second memory cell groups 21 and 22;
step S34, determining whether the difference between the threshold voltage corresponding to the first memory cell group 21 and the threshold voltage corresponding to the second memory cell group 22 after one-time group programming is greater than or equal to the group tolerance, and if so, taking the current group programming frequency as the group programming frequency.
A specific manner of dividing the plurality of test memory cells into the first memory cell group 21 and the second memory cell group 22 according to the difference in programming speed may be to use a programmed state verifying voltage after one-time programming as a determination criterion, and to assign the test memory cells with a threshold voltage greater than or equal to the programmed state verifying voltage to the first memory cell group 21 and assign the test memory cells with a threshold voltage less than the programmed state verifying voltage to the second memory cell group.
More preferably, the specific step of obtaining the number of times of packet programming further comprises: judging whether the difference between the threshold voltage corresponding to the first memory cell group 21 and the threshold voltage corresponding to the second memory cell group 22 after one-time grouping programming is greater than or equal to the grouping tolerance, and if not, performing the next-time grouping programming on the first memory cell group 21 and the second memory cell group.
In this embodiment, a cyclic test step is constructed for a plurality of test memory cells, and the maximum grouping programming frequency that can be performed when the aliasing degree between different memory cell groups is within the grouping tolerance is found through multiple grouping programming and threshold voltage difference determination steps with the set grouping tolerance as a reference standard, so as to avoid grouping failures. In order to ensure the final programming effect, the test memory cell and the memory cell to be programmed are the same in terms of device structure and forming process or have similarity larger than a preset value.
Step S12, determining whether the remaining programming times of the to-be-programmed memory cells 20 are less than or equal to the grouping programming times, if yes, grouping the to-be-programmed memory cells 20 according to different programming speeds.
And step S13, performing grouping programming according to the grouping information of the storage units to be programmed.
Preferably, the group programming includes adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed. According to the difference of the programming speed of each group of memory cells, one or more of word line voltage, bit line voltage and programming voltage duration applied to each group of memory cells to be programmed are adjusted, so that the programming speed of different groups of memory cells is controlled, and aliasing of the groups of memory cells is avoided.
In the embodiment, the grouping tolerance is set, the grouping programming times which can avoid grouping failure are searched, the optimal grouping time is obtained, the programming error rate is reduced, the programming speed is accelerated, and the performance of the flash memory is improved.
Preferably, the flash memory control method further includes the steps of:
(a) a number of the memory cells 20 to be programmed are programmed together. The common programming means that a plurality of memory cells 20 to be programmed are programmed under the same programming condition. The programming condition includes one or more of a word line voltage, a bit line voltage, a programming voltage duration. Wherein the program voltage duration includes a duration of applying a word line voltage and/or a duration of applying a bit line voltage.
(b) And judging whether the residual programming times of the memory cells 20 to be programmed are less than or equal to the grouped programming times, and if not, carrying out the next common programming on a plurality of memory cells to be programmed.
FIG. 4 is a flow chart illustrating a programming process in accordance with an embodiment of the present invention. In order to simplify the entire control flow, preferably, as shown in fig. 4, the specific step of determining whether the remaining programming times of the memory cells to be programmed are less than or equal to the grouped programming times includes:
step S41, acquiring the total programming times required for the to-be-programmed memory list 20 to reach the target threshold voltage. The total programming times may be an average programming time required for programming the memory cell to be programmed to the target threshold voltage through a plurality of tests, or may be preset.
Step S42, determining whether the current programming frequency is greater than or equal to the difference between the total programming frequency and the grouped programming frequency, if so, performing step S14, i.e. grouping the to-be-programmed memory cells according to the difference of the programming speeds. More preferably, if the current programming time is less than the difference between the total programming time and the grouped programming time, step S12 is performed, i.e. the next co-programming is performed on the plurality of memory cells 20 to be programmed.
For example: as shown in fig. 2, if the total programming time required for the memory cells 20 to be programmed to reach the target threshold voltage is a, which is obtained according to the grouping programming time M obtained by the grouping margin test, the condition for performing the grouping programming on the plurality of memory cells 20 to be programmed is that the programming time N is greater than or equal to a-M. After the number of times of common programming of the memory cells 20 to be programmed reaches N times, the memory cells 20 to be programmed are grouped. For example, with the program-state verifying voltage corresponding to the memory cells to be programmed after N times of programming as the reference standard, the memory cells with the threshold voltage higher than the program-state verifying voltage after N times of programming in the memory cells 20 to be programmed are assigned as the fast programming cell group, and the memory cells with the threshold voltage higher than the program-state verifying voltage after N times of programming are assigned as the fast programming cell group and the slow programming cell group. Then, the fast programming cell group and the slow programming cell group are separately programmed in groups M times, so that finally the fast programming cell group and the slow programming cell group both reach a target threshold voltage. At this time, a threshold voltage aliasing degree Δ V between the fast programming cell group and the slow programming cell group is less than or equal to the grouping margin.
FIG. 5A is a graph illustrating a comparison of a programming speed of an embodiment of the present invention with a conventional programming speed, and FIG. 5B is a graph illustrating a comparison of a program error rate of an embodiment of the present invention with a conventional program error rate. In fig. 5A and 5B, a dotted line 51 represents a threshold voltage distribution during programming by the flash memory control method according to the present embodiment, and a solid line 52 represents a threshold voltage distribution during programming by the conventional grouping method.
Taking the erased state cell E programmed to the P2 state as an example, in FIG. 5A, after the (N + 3) th programming, all the cells programmed by the flash memory control method provided in this embodiment pass the verification voltage V2 statep2(ii) a The memory cells programmed by the conventional grouping method are affected by the memory cells with a slower programming speed, and more programming cycles are required. Therefore, the flash memory control method provided by the embodiment can greatly improve the programming speed.
Also taking the example of programming the erased cell E to the P2 state, in FIG. 5B, the threshold distribution of the conventional grouping manner becomes wider after multiple programming pulses, and after the N + M programming, a part of the cells exceed the program-verify voltage V of the P3 statep3Causing coding errors; in the memory cells programmed by the flash memory control method according to the present embodiment, after the (N + M) th programming, all the memory cells pass the verification voltage V of the P2 statep2And, since the threshold voltage distribution is narrower when the memory cell programmed by the flash memory control method provided by the present embodiment reaches the target programming state, almost no memory cell reaches the P3 state,the programming error rate is effectively improved.
In order to solve the above problems, the present embodiment further provides a flash memory control device, and fig. 6 is a schematic structural diagram of the flash memory control device according to the present embodiment. As shown in fig. 6, the flash memory control device provided in the present embodiment includes an obtaining module 62, a control module 64, and a grouping program module 63.
The obtaining module 62 is configured to obtain a grouping programming frequency, where the grouping programming frequency is a maximum programming frequency for keeping an inter-group aliasing degree of a plurality of to-be-programmed memory cells within a grouping tolerance in a grouping programming process;
the control module 64 is connected to the obtaining module 62, and is configured to determine whether the remaining programming times of the to-be-programmed memory cells are less than or equal to the grouping programming times, and if yes, group the to-be-programmed memory cells according to different programming speeds;
the grouping programming module 63 is connected to the control module 64, and is configured to perform grouping programming on the grouping information of the plurality of memory cells to be programmed according to the control module 64.
In order to facilitate the user to adjust the grouping tolerance as desired, it is preferable that the flash memory control device further includes a setting module 61. The setting module 61 is connected to the obtaining module 62, and is configured to set the grouping tolerance.
Preferably, the grouping margin is a preset threshold voltage; the acquisition module 62 includes:
an input unit 621 for inputting a plurality of test memory cells, the test memory cells being programmed at least once;
a grouping unit 622, connected to the input unit 621, for dividing the plurality of test memory cells into a first memory cell group and a second memory cell group according to different programming speeds, where the programming speed of the first memory cell group is greater than that of the second memory cell group;
a processing unit 623 connected to the grouping unit 622, configured to perform grouping programming on the first memory cell group and the second memory cell group at a time;
a determining unit 624, connected to the processing unit 623, configured to determine whether a difference between a threshold voltage corresponding to the first memory cell group and a threshold voltage corresponding to the second memory cell group after one-time group programming is greater than or equal to the group tolerance, and if so, take the current group programming frequency as the group programming frequency.
Preferably, the determining unit 624 is further configured to determine whether a difference between the threshold voltage corresponding to the first memory cell group and the threshold voltage corresponding to the second memory cell group after one-time group programming is greater than or equal to the grouping tolerance, and if not, perform the next-time group programming on the first memory cell group and the second memory cell group.
Preferably, the control module 64 is further configured to determine whether the remaining programming times of the memory cells to be programmed are less than or equal to the grouped programming times, and if not, perform the next common programming on the memory cells to be programmed.
Preferably, the control module 64 includes:
an obtaining unit 641, configured to obtain the total programming times required for the to-be-programmed memory cell to reach the target threshold voltage;
and the analyzing unit 642 is connected to the obtaining unit and is configured to determine whether the current programming frequency is greater than a difference between the total programming frequency and the grouped programming frequency, and if so, group the to-be-programmed memory units according to different programming speeds.
Preferably, the group programming includes adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed.
In the flash memory control method and the flash memory control device according to the present embodiment, the grouping margin is set, and the timing of grouping the memory cells for programming is determined according to the grouping margin, so that the programming aliasing of the memory cells is controlled within the grouping margin, and the programming speed can be effectively increased while the programming error rate is reduced, thereby ensuring the performance of the flash memory.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. A flash memory control method is characterized by comprising the following steps:
acquiring the grouping programming times, wherein the grouping programming times are the maximum programming times of a plurality of storage units to be programmed, and the inter-group aliasing degree of the storage units to be programmed is kept within a grouping tolerance in the grouping programming process; the grouping tolerance refers to the allowable inter-group aliasing degree in the grouping programming process between two groups of storage units with different programming speeds;
judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouping programming times, if so, grouping a plurality of storage units to be programmed according to different programming speeds; and performing grouping programming according to grouping information of a plurality of memory cells to be programmed.
2. The method of claim 1, wherein the grouping margin is a predetermined threshold voltage; the specific steps for acquiring the times of the group programming comprise:
providing a plurality of test memory cells, wherein the test memory cells are programmed at least once;
dividing the plurality of test memory cells into a first memory cell group and a second memory cell group according to different programming speeds, wherein the programming speed of the first memory cell group is greater than that of the second memory cell group;
performing a one-time group program on the first and second memory cell groups;
and judging whether the difference between the threshold voltage corresponding to the first storage unit group and the threshold voltage corresponding to the second storage unit group after one-time grouping programming is larger than or equal to the grouping tolerance, and if so, taking the current grouping programming frequency as the grouping programming frequency.
3. The method of claim 2, wherein the step of obtaining the number of times of the group programming further comprises:
and judging whether the difference between the threshold voltage corresponding to the first memory cell group and the threshold voltage corresponding to the second memory cell group after one-time grouping programming is larger than or equal to the grouping tolerance, and if not, performing the next-time grouping programming on the first memory cell group and the second memory cell group.
4. The flash memory control method of claim 1, further comprising the steps of:
performing one-time common programming on a plurality of memory cells to be programmed;
and judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouped programming times, and if not, carrying out the next common programming on the storage units to be programmed.
5. The method of claim 1, wherein determining whether the remaining programming times of the to-be-programmed memory cells are less than or equal to the grouped programming times, if so, grouping the to-be-programmed memory cells according to different programming speeds comprises:
acquiring the total programming times required by the to-be-programmed storage unit to reach a target threshold voltage;
and judging whether the current programming times are larger than or equal to the difference between the total programming times and the grouping programming times, if so, grouping a plurality of memory cells to be programmed according to different programming speeds.
6. The method of claim 1, wherein the group programming comprises adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed.
7. A flash memory control apparatus, comprising:
the acquisition module is used for acquiring the grouping programming times, wherein the grouping programming times are the maximum programming times of the inter-group aliasing degree of a plurality of storage units to be programmed in the grouping programming process, and the inter-group aliasing degree is kept within a grouping tolerance; the grouping tolerance refers to the allowable inter-group aliasing degree in the grouping programming process between two groups of storage units with different programming speeds;
the control module is connected with the acquisition module and used for judging whether the residual programming times of the storage units to be programmed are less than or equal to the grouping programming times, and if so, the storage units to be programmed are grouped according to different programming speeds;
and the grouping programming module is connected with the control module and is used for grouping programming the grouping information of the storage units to be programmed according to the control module.
8. The flash memory control device of claim 7, wherein the grouping margin is a predetermined threshold voltage; the acquisition module includes:
an input unit for inputting a plurality of test memory cells, the test memory cells being programmed at least once;
the grouping unit is connected with the input unit and is used for dividing the plurality of test storage units into a first storage unit group and a second storage unit group according to different programming speeds, and the programming speed of the first storage unit group is greater than that of the second storage unit group;
the processing unit is connected with the grouping unit and is used for performing one-time grouping programming on the first storage unit group and the second storage unit group;
and the judging unit is connected with the processing unit and used for judging whether the difference between the threshold voltage corresponding to the first storage unit group and the threshold voltage corresponding to the second storage unit group after one-time grouping programming is greater than or equal to the grouping tolerance, and if so, taking the current grouping programming frequency as the grouping programming frequency.
9. The flash memory control device according to claim 8, wherein the determining unit is further configured to determine whether a difference between the threshold voltage corresponding to the first memory cell group and the threshold voltage corresponding to the second memory cell group after the one-time group programming is greater than or equal to the grouping tolerance, and if not, perform the next group programming on the first memory cell group and the second memory cell group.
10. The flash memory control device of claim 7, wherein the control module is further configured to determine whether the remaining programming times of the to-be-programmed memory cells are less than or equal to the grouped programming times after performing one-time co-programming on the to-be-programmed memory cells, and if not, perform the next co-programming on the to-be-programmed memory cells.
11. The flash memory control device of claim 7, wherein the control module comprises:
the obtaining unit is used for obtaining the total programming times required by the to-be-programmed storage unit to reach the target threshold voltage;
and the analysis unit is connected with the acquisition unit and used for judging whether the current programming frequency is greater than the difference between the total programming frequency and the grouping programming frequency, and if so, grouping the storage units to be programmed according to different programming speeds.
12. The flash memory control device of claim 7, wherein the group programming comprises adjusting one or more of a word line voltage, a bit line voltage, and a programming voltage duration applied to different groups of memory cells to be programmed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810657590.3A CN108831516B (en) | 2018-06-20 | 2018-06-20 | Flash memory control method and flash memory control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810657590.3A CN108831516B (en) | 2018-06-20 | 2018-06-20 | Flash memory control method and flash memory control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108831516A CN108831516A (en) | 2018-11-16 |
| CN108831516B true CN108831516B (en) | 2020-10-23 |
Family
ID=64137537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810657590.3A Active CN108831516B (en) | 2018-06-20 | 2018-06-20 | Flash memory control method and flash memory control device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108831516B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114415944A (en) * | 2021-12-27 | 2022-04-29 | 深圳忆联信息系统有限公司 | Solid state disk physical block management method and device, computer equipment and storage medium |
| CN117409843B (en) * | 2023-12-14 | 2024-03-22 | 合肥康芯威存储技术有限公司 | Quality analysis method and device of flash memory, electronic equipment and medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105989883A (en) * | 2015-02-26 | 2016-10-05 | 群联电子股份有限公司 | Memory programming method, memory storage device and memory control circuit unit |
| CN106297882A (en) * | 2015-06-25 | 2017-01-04 | 旺宏电子股份有限公司 | Method and apparatus for programming non-volatile memory device to reduce bit line disturb |
| US9959932B1 (en) * | 2017-02-21 | 2018-05-01 | Sandisk Technologies Llc | Grouping memory cells into sub-blocks for program speed uniformity |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101619249B1 (en) * | 2009-11-26 | 2016-05-11 | 삼성전자주식회사 | Program method |
| US9953703B2 (en) * | 2015-10-16 | 2018-04-24 | Samsung Electronics Co., Ltd. | Programming method of non volatile memory device |
-
2018
- 2018-06-20 CN CN201810657590.3A patent/CN108831516B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105989883A (en) * | 2015-02-26 | 2016-10-05 | 群联电子股份有限公司 | Memory programming method, memory storage device and memory control circuit unit |
| CN106297882A (en) * | 2015-06-25 | 2017-01-04 | 旺宏电子股份有限公司 | Method and apparatus for programming non-volatile memory device to reduce bit line disturb |
| US9959932B1 (en) * | 2017-02-21 | 2018-05-01 | Sandisk Technologies Llc | Grouping memory cells into sub-blocks for program speed uniformity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108831516A (en) | 2018-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE46014E1 (en) | Defective word line detection | |
| KR101222063B1 (en) | Non volatile memory device and operating method thereof | |
| JP6856400B2 (en) | Semiconductor storage device and memory system | |
| US10861557B2 (en) | Semiconductor storage apparatus | |
| KR101134691B1 (en) | Erase algorithm for multi-level bit flash memory | |
| US11011242B2 (en) | Bit line voltage control for damping memory programming | |
| US8929149B2 (en) | Semiconductor memory device and method of operating the same | |
| US10573397B1 (en) | Parameter tracking for non-volatile memory to avoid over-programming | |
| CN109817265B (en) | Semiconductor memory device and method of operating the same | |
| US7450432B2 (en) | Method of programming data in a flash memory device | |
| US20130182506A1 (en) | Programming algorithm for improved flash memory endurance and retention | |
| EP2562759A2 (en) | Memory device with reduced sense time readout | |
| USRE45544E1 (en) | Saw-shaped multi-pulse programming for program noise reduction in memory | |
| JP2005129194A (en) | Programming based on the behavior of non-volatile memory | |
| US8842476B2 (en) | Erratic program detection for non-volatile storage | |
| US10699776B1 (en) | Apparatus and methods for merging post-write read and select gate maintenance operations | |
| CN108831516B (en) | Flash memory control method and flash memory control device | |
| US10403379B1 (en) | Erased block reverification method for solid state storage device | |
| US8842469B2 (en) | Method for programming a multi-state non-volatile memory (NVM) | |
| US9378809B1 (en) | Relaxing verification conditions in memory programming and erasure operations | |
| CN110337694B (en) | Method of programming multi-level cell NAND flash memory devices and MLC NAND flash memory devices | |
| US6621742B1 (en) | System for programming a flash memory device | |
| US10762974B2 (en) | One check fail byte (CFBYTE) scheme | |
| US8787057B2 (en) | Fast analog memory cell readout using modified bit-line charging configurations | |
| US8472246B2 (en) | Method of programming a multi-bit per cell non-volatile memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |