[go: up one dir, main page]

CN108809627B - Round conversion multiplexing circuit and AES decryption circuit - Google Patents

Round conversion multiplexing circuit and AES decryption circuit Download PDF

Info

Publication number
CN108809627B
CN108809627B CN201810597055.3A CN201810597055A CN108809627B CN 108809627 B CN108809627 B CN 108809627B CN 201810597055 A CN201810597055 A CN 201810597055A CN 108809627 B CN108809627 B CN 108809627B
Authority
CN
China
Prior art keywords
matrix
constant
register
multiplication
round
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810597055.3A
Other languages
Chinese (zh)
Other versions
CN108809627A (en
Inventor
张肖强
郑辛星
梁广俊
王新航
王磊
孙忠先
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui Polytechnic University
Original Assignee
Anhui Polytechnic University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui Polytechnic University filed Critical Anhui Polytechnic University
Priority to CN201810597055.3A priority Critical patent/CN108809627B/en
Publication of CN108809627A publication Critical patent/CN108809627A/en
Application granted granted Critical
Publication of CN108809627B publication Critical patent/CN108809627B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/122—Hardware reduction or efficient architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)

Abstract

本发明涉及密码电路技术领域，提供了一种轮变换复用电路及AES加密电路，本发明提供的轮变换复用电路通过常数矩阵的合并与合成运算，将AES解密算法中的所有线性变换运算组合成两个合成矩阵，合成矩阵

Figure DDA0001692034380000012
与合成矩阵
Figure DDA0001692034380000011
从而缩短AES解密电路的关键路径，同时降低AES解密电路实现面积。

Figure 201810597055

The present invention relates to the technical field of cipher circuits, and provides a round transformation multiplexing circuit and an AES encryption circuit. The round transformation multiplexing circuit provided by the present invention converts all linear transformation operations in the AES decryption algorithm through the combination and synthesis operations of constant matrices. combined into two composite matrices, composite matrices

Figure DDA0001692034380000012
with composite matrix
Figure DDA0001692034380000011
Therefore, the critical path of the AES decryption circuit is shortened, and the implementation area of the AES decryption circuit is reduced at the same time.

Figure 201810597055

Description

Round conversion multiplexing circuit and AES decryption circuit
Technical Field
The invention relates to the technical field of cryptographic circuits, in particular to a round-robin circuit and an AES decryption circuit.
Background
AES (Advanced Encryption Standard) is a new generation of block symmetric cipher algorithm established by the national institute of standards and technology 2001, and is used to replace the original DES (Data Encryption Standard). Currently, the AES cryptographic algorithm has been adopted by several international standards organizations, and is the most widely used block cipher algorithm at present.
The data packet length of the AES cipher algorithm is 128 bits, the key length is 128 bits, 192 bits and 256 bits, and the key length is respectively called AES-128, AES-192 and AES-256. The AES algorithm is an iterative algorithm, each iteration can be called as round conversion, the key length is different, the number of round conversion is different, and the number N of round conversion of AES-128, AES-192 and AES-256r10, 12 and 14 respectively. AES encryption process is shown in figure 1, and sequentially carries out first-round transformation and N r1 round of ordinary round transformation and last round transformation, the first round of transformation carries on the operation of adding the cipher key and the byte substitution operation sequentially; the ordinary round conversion carries out four operations of row shift, column mixing, key addition and byte replacement in sequence; the first round of transformation carries out the operations of shifting and adding the key in sequence. The AES decryption process is a reverse process of the encryption process, and as shown in FIG. 2, the first round of transformation and N are also performed in sequence r1 round of common round conversion and last round conversion, wherein the first round conversion is the inverse operation of the last round conversion in the encryption process, and key addition and reverse shift operation are sequentially performed, the common round conversion is the inverse operation of the common round conversion in the encryption process and comprises inverse byte replacement, key addition, inverse column mixing and reverse shift operation, the last round conversion is the inverse operation of the first round conversion in the encryption process and sequentially performs inverse byte replacement and key addition operation, and the inverse column mixing, reverse shift and inverse byte replacement are respectively the inverse operation of column mixing, row shift and byte replacement in the encryption process.
The operations in the decryption process are sequentially and independently operated, so that not only is circuit resources wasted, but also the key path is long, and therefore, several adjacent operation units are combined into one operation unit through a synthesis matrix for implementation. The T box realizes that the operation results of operations such as S box, row shift, column mixing and the like are prestored in a storage operation unit in a precalculation mode, and the functions of S box, row shift and column mixing and merging operations are realized in a look-up table mode. The T box implementation reduces the critical path of the whole common round conversion circuit, so the T box implementation mode is mainly applied to the high-speed AES circuit design, although the T box implementation mode can accelerate the data processing speed, the circuit area is greatly increased, for example, Rach et al will be based on the last GF (2) in the composite domain S box/inverse S box4) The multiplier, the mapping matrix/inverse mapping operation, the affine/inverse affine operation, the column mixing/inverse column mixing operation, the key addition operation and the like are combined into an operation unit, the key path is shortened by the combination operation unit, but the circuit area is greatly increased, and the length of the key path is optimized at the cost of increasing the circuit area in the conventional round conversion circuit based on the combination operation.
Disclosure of Invention
The embodiment of the invention provides an AES decryption circuit, aiming at solving the problem that the length of a key path is optimized at the cost of increasing the circuit area in the conventional round conversion circuit based on merging operation.
The present invention is achieved as described above, and a round robin circuit includes:
a synthesis matrix multiplication unit 1, a constant addition unit, a complex domain inverse multiplication unit, a selector S1, a synthesis matrix multiplication unit 2, and a selector S2, the input end of the synthesis matrix multiplication arithmetic unit 1 is connected with the feedback data input port, the output end of the synthesis matrix multiplication arithmetic unit is connected with the input end of the constant addition arithmetic unit, the output end of the constant addition arithmetic unit is connected with the input end of the composite domain multiplication inverse arithmetic unit, the output end of the composite domain multiplication inverse arithmetic unit is connected with one input end of the selector S1, the other input end of the selector S1 is connected with the ciphertext data input port, the output end of the selector S1 and the key input port are both connected with the input end of the synthesis matrix multiplication arithmetic unit 2, two output ends of the synthesis matrix multiplication arithmetic unit 2 are respectively connected with two input ends of the selector S2, and the third output end of the synthesis matrix multiplication arithmetic unit 2 is;
a composite matrix multiplication unit 1 for multiplying the composite matrix
Figure GDA0002721857300000031
With column vectors input from feedback data inputs
Figure GDA0002721857300000032
Performing multiplication operation to obtain operation result
Figure GDA0002721857300000033
And outputting the output to a constant addition operation unit, wherein the expression of the synthesis matrix is specifically as follows:
Figure GDA0002721857300000034
a constant addition unit for adding the vector
Figure GDA0002721857300000035
And constant vector, i.e. omegaλ＝[ωλ,ωλ,ωλ,ωλ]TAdding the result of the operation
Figure GDA0002721857300000036
Outputting the data to a composite domain multiplication inverse operation unit;
a complex domain inverse multiplication unit for multiplying the vector
Figure GDA0002721857300000037
Each byte in the data processing system is subjected to complex domain inverse multiplication, and the operation result is obtained
Figure GDA0002721857300000038
Output to the synthesis matrix multiplication unit 2;
when performing the first-pass transform, the selector S1 selects data to be input from the ciphertext input port
Figure GDA0002721857300000039
Outputs the result to a synthesis matrix multiplication unit 2, and selects a result of inverse multiplication of the composite domain by a selector S1 when performing normal round conversion and final round conversion
Figure GDA00027218573000000310
Output to the synthesis matrix multiplication unit 2;
a synthesis matrix multiplication unit 2 for combining the data vectors outputted from the selector S1
Figure GDA00027218573000000311
And a key vector
Figure GDA00027218573000000312
Combined into a column vector
Figure GDA00027218573000000313
Key vector
Figure GDA00027218573000000314
With the key vector K in the encryption processvSame, will synthesize the matrix
Figure GDA00027218573000000315
And the column vector
Figure GDA00027218573000000316
Performing multiplication to synthesize matrix
Figure GDA00027218573000000317
The expression of (a) is specifically as follows:
Figure GDA0002721857300000041
vector composed of first line to fourth line of operation result
Figure GDA0002721857300000042
And the fifth to the second line
Figure GDA0002721857300000043
Respectively output to the selector S2, and the vectors composed of the ninth line to the twelfth line of the operation result
Figure GDA0002721857300000044
Outputting from a plaintext output port;
in the first-pass conversion, the selector S2 selects the vector
Figure GDA0002721857300000045
Fed back to the feedback data input port, and the selector S2 selects the vector to be converted when performing the ordinary round conversion
Figure GDA0002721857300000046
Fed back to the feedback data output port.
The invention is realized in this way, an AES decipher circuit based on round transform multiplex circuit, AES decipher circuit includes:
the feedback data output port of the round conversion multiplexing circuit is connected with the input end of the register 1, the output end of the register 1 is connected with the input end of the register 2, and the output end of the register 2 is connected with the feedback data input end of the round conversion multiplexing circuit;
the data bit width of register 1 and register 2 is 16 bytes.
The invention is realized in this way, an AES decipher circuit based on round transform multiplex circuit, AES decipher circuit includes:
the device comprises two multiplexing round conversion circuits, a register 1 and a register 2, wherein feedback data output ports of the two round conversion multiplexing circuits are connected with the input end of the register 1, the output end of the register 1 is connected with the input end of the register 2, and the output end of the register 2 is connected with the feedback data input ends of the two round conversion multiplexing circuits;
the data bit width of register 1 and register 2 is 16 bytes.
The invention is realized in this way, an AES decipher circuit based on round transform multiplex circuit, AES decipher circuit includes:
the four-wheel conversion multiplexing circuit comprises four multiplexing wheel conversion circuits and a register, wherein the feedback data output ports of the four wheel conversion multiplexing circuits are connected with the input end of the register, and the output end of the register is connected with the feedback data input ends of the four wheel conversion multiplexing circuits;
the data bit width of the register is 16 bytes.
The round conversion multiplexing circuit combines all linear conversion operations in an AES decryption algorithm into two synthetic matrixes through the combination and synthesis operation of constant matrixes, and the synthetic matrixes
Figure GDA0002721857300000051
And the synthesis matrix
Figure GDA0002721857300000052
Therefore, the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, is beneficial to improving the optimization efficiency of the circuit and reducing the realization area of the AES decryption circuit.
Drawings
Fig. 1 is a flowchart of a standard AES encryption provided by an embodiment of the present invention;
FIG. 2 is a flowchart of a standard AES decryption process provided by an embodiment of the invention;
fig. 3 is a schematic structural diagram of a round-robin circuit for AES decryption according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an AES decryption circuit according to a first embodiment of the invention;
fig. 5 is a schematic structural diagram of an AES decryption circuit according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of an AES decryption circuit according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The conventional arithmetic unit generally includes: the system comprises an inverse byte replacement operation unit, an inverse shift operation unit, an inverse column mixing operation unit and a key addition operation unit, wherein the operation formula of the operation unit is as follows:
the AES round transform is a transform operation performed in matrix form, and the decryption algorithm treats the incoming 128-bit packet data as 4 × 4 byte matrices, each matrix having 1 byte of elements. The intermediate result of the round-robin transformation is referred to as a state matrix that is a 4 x 4 byte matrix. Assume that the state matrix of the normal round shift input is:
Figure GDA0002721857300000061
the operation in the AES decryption process is described in detail as follows:
1. inverse byte substitution arithmetic unit
The inverse byte replacement operation unit performs an inverse byte replacement operation, which is an inverse operation of byte replacement, also called an inverse S-box operation. The inverse S-box operation is also to perform inverse replacement operation on each byte in the state matrix according to the byte replacement table. Assume that the state matrix after the inverse S-box operation is:
Figure GDA0002721857300000062
the inverse S-box operation can be expressed as:
Figure GDA0002721857300000071
Figure GDA0002721857300000072
wherein
Figure GDA0002721857300000073
Is an inverse S-box operation function. The inverse S-box operation is the only nonlinear operation in four operations of ordinary round conversion, and is also the operation with the highest operation complexity, so that the inverse S-box operation circuit occupies most of the circuit area and the power consumption of the whole AES decryption circuit.
In inverse S-box operation, the input byte is first subjected to an inverse affine operation, which is the inverse of the encrypted S-box affine operation, and then to a finite field GF (2)8) The inverse multiplication operation on the domain has the expression:
Figure GDA0002721857300000074
wherein x is input byte, omega is byte constant, tau ' is constant matrix of 8 x 8bit, and is inverse matrix of constant matrix tau in encryption S box, tau ' and omega are used for completing inverse affine operation ' ()A -1Is GF (2)8) The inverse of the multiplication over the field. GF (2) according to the present invention8) The field is GF (2) specified in AES cipher algorithm8) A field of irreducible polynomial
f(x)＝x8+x4+x3+x+1
Among many S-box implementations, the composite domain based S-box implementation has the smallest circuit area. Composite domain S-box transforms the principal arithmetic unit-GF (2) in the S-box by mathematical transformation8) The inverse domain multiplication unit maps to the complex domain implementation. The computational complexity of the complex domain multiplicative inverse is much less than GF (2)8) The computational complexity of the inverse of the domain multiplication can be reduced significantly, thus the hardware complexity of the S-box circuit implementation can be reduced significantly.
The inverse S-box operation expression based on the composite domain is as follows:
Figure GDA0002721857300000075
wherein ()C -1For multiplicative inverse operations on complex fields, the complex field being an arbitrary and GF (2)8) Composite domain of domain isomorphism, delta is 8 x 8bit mapping matrix, whose function is to convert input byte x from GF (2)8) The field is mapped to the complex field, δ' is the δ inverse matrix, which acts to map the complex field multiplicative inverse result from the complex field back to GF (2)8) A domain.
In the finite field, the addition operation is a bit exclusive or logic operation. According to
Figure GDA0002721857300000081
Figure GDA0002721857300000082
Therefore, when the constant addition operation + ω is implemented in hardware, the addition 0 operation can be directly omitted, and the addition 1 operation can replace the exclusive or logic operation by two methods: 1. the exclusive or logic of any two variables is replaced by the exclusive or logic; 2. the two variables are realized by using exclusive-OR logic and inverting logic. Because the circuit areas and the time delays of the exclusive-OR gate and the exclusive-OR gate are almost the same, and compared with the exclusive-OR gate, the circuit area and the time delay of the reverse logic gate can be ignored, and therefore, when the inverse S-box hardware is implemented, the area and the time delay of the constant addition operation + omega circuit can be ignored.
2. Key addition unit
The key addition operation unit performs key addition operation, and the key addition operation is the same as the key addition operation in the encryption flow. Assume that the state matrix after the key addition operation is:
Figure GDA0002721857300000083
the key addition operation expression is:
Figure GDA0002721857300000084
Figure GDA0002721857300000085
wherein the matrix
Figure GDA0002721857300000086
The sub-key matrix is generated by a key expansion algorithm, and the use sequence of the sub-key matrix is opposite to that of the sub-key matrix in the encryption process.
3. Inverse column hybrid arithmetic unit
The inverse column mixing operation unit performs inverse column mixing operation, the inverse column mixing operation is inverse operation of column mixing, and can be regarded as that each column in the state matrix is in a ring with a constant polynomial
Figure GDA00027218573000000910
The product of (a) and (b). The state matrix after the inverse column mixing operation is assumed to be:
Figure GDA0002721857300000091
the expression of the inverse column mix operation is:
Figure GDA0002721857300000092
Figure GDA0002721857300000093
wherein the matrix
Figure GDA0002721857300000094
Is a column mixed constant matrix, a constant matrix
Figure GDA0002721857300000095
In (1)
Figure GDA0002721857300000096
Are each GF (2)8) Domain multiplication by the constant x {09}16、×{0b}16、×{0d}16、×{0e}16In matrix form, in the present invention { }16Representing a hexadecimal form of the constant.
4. Reverse shift operation unit
The reverse shift operation unit performs reverse shift operation, and the reverse shift operation is the reverse operation of the line shift, namely the first line of the state matrix is not transformed, and the second, third and fourth lines are respectively shifted to the right by one byte, two bytes and three bytes. The state matrix after the reverse shift operation is assumed to be:
Figure GDA0002721857300000097
the state matrix after the retrograde shift can be expressed as:
Figure GDA0002721857300000098
Figure GDA0002721857300000099
the reverse shift operation does not need to consume any logic circuit resource in the hardware realization, and only needs to adjust the bus position.
5. General wheel transformation formula
Four arithmetic units in the common round transformation can be realized independently, and several adjacent arithmetic units can be combined into one arithmetic unit for realization. The round conversion circuit realized by the arithmetic unit independently wastes circuit resources and has a long critical path. The invention combines the linear operation in the decryption common round transformation by the combination and synthesis operation of the constant matrix according to the decryption common round transformation formula. According to each sub-operation formula in the middle-round transformation, a decryption common round transformation formula can be obtained as follows:
Figure GDA0002721857300000101
Figure GDA0002721857300000102
wherein
Figure GDA0002721857300000103
Is a constant matrix
Figure GDA0002721857300000104
The number of the row vectors in (1),
Figure GDA0002721857300000105
and
Figure GDA0002721857300000106
respectively input data matrix
Figure GDA0002721857300000107
And a key matrix
Figure GDA0002721857300000108
The column vector of (1), i.e.:
Figure GDA0002721857300000109
Figure GDA00027218573000001010
output variable r having the same input in the above formulax,yThe grouping is divided into four groups. These four groups have the same arithmetic operation and have the same circuit arithmetic unit when implemented in hardware. Each packet output variable can be expressed in the form of a linear equation:
Figure GDA0002721857300000111
the corresponding variables in each group of input variables and output variables in the above equation are:
group I:
Figure GDA0002721857300000112
group II:
Figure GDA0002721857300000113
group III:
Figure GDA0002721857300000114
group IV:
Figure GDA0002721857300000115
in order to reduce the circuit implementation area, the invention further converts GF (2) in the inverse S box8) The multiplication is inversely mapped to a composite domain, and the general round transformation grouping formula after mapping is as follows:
Figure GDA0002721857300000116
6. first-round transformation formula
According to the above sub-operation formulas, the first-round transformation formula can be obtained as follows:
Figure GDA0002721857300000117
Figure GDA0002721857300000118
according to the grouping of the common round transformation, the first round transformation formula can also be divided into four groups, and the first round transformation grouping formula is as follows:
Figure GDA0002721857300000121
the corresponding variables of the input variables and the output variables in the first-round transformation grouping formula in each group are the same as those in the common round transformation.
7. Last wheel transformation formula
According to the above sub-operation formulas, the final round transformation formula can be obtained as follows:
Figure GDA0002721857300000122
Figure GDA0002721857300000123
similarly, the last round transformation formula can also be divided into four groups, and the last round transformation group formula is:
Figure GDA0002721857300000124
the corresponding variables in each group of input variables and output variables in the above equation are:
group I:
Figure GDA0002721857300000125
group II:
Figure GDA0002721857300000126
group III:
Figure GDA0002721857300000127
group IV:
Figure GDA0002721857300000128
in the above grouping, the variable is output
Figure GDA0002721857300000129
The corresponding variables in each group are different from the ordinary round conversion, and the variables are input
Figure GDA00027218573000001210
And
Figure GDA00027218573000001211
the corresponding variables in each grouping are the same as the normal round of transformation. Mapping the inverse S-box operation in the last round transformation to the composite domain, and then the last round transformation grouping formula is as follows:
Figure GDA0002721857300000131
the round conversion multiplexing circuit combines all linear conversion operations in an AES decryption algorithm into two synthetic matrixes through combination and synthesis operation of constant matrixes, and the synthetic matrixes
Figure GDA0002721857300000132
And the synthesis matrix
Figure GDA0002721857300000133
Therefore, the key path of the AES decryption circuit is shortened, and the implementation area of the AES decryption circuit is reduced.
Fig. 3 is a schematic structural diagram of a multiplexing round conversion circuit according to an embodiment of the present invention, and for convenience of description, only the relevant parts of the embodiment of the present invention are shown.
The multiplexing round conversion circuit is used for realizing AES decryption operation of 4 bytes, and comprises the following components:
a synthesis matrix multiplication unit 1, a constant addition unit, a complex domain inverse multiplication unit, a selector S1, a synthesis matrix multiplication unit 2, and a selector S2;
the input end of the synthesis matrix multiplication arithmetic unit 1 is connected with the feedback data input port, the output end is connected with the input end of the constant addition arithmetic unit, the output end of the constant addition arithmetic unit is connected with the input end of the composite domain multiplication inverse arithmetic unit, the output end of the composite domain multiplication inverse arithmetic unit is connected with one input end of the selector S1, the other input end of the selector S1 is connected with the ciphertext data input port, the output end of the selector S1 and the key input port are both connected with the input end of the synthesis matrix multiplication arithmetic unit 2, two output ends of the synthesis matrix multiplication arithmetic unit 2 are respectively connected with two input ends of the selector S2, and the third output end is connected with the plaintext data output port.
A composite matrix multiplication unit 1 for multiplying the composite matrix
Figure GDA0002721857300000134
And the column vector
Figure GDA0002721857300000135
The multiplication operation is carried out and the operation is carried out,
Figure GDA0002721857300000136
is a column vector input from the feedback data input end, and the expression of the composite matrix is specifically as follows:
Figure GDA0002721857300000141
wherein the matrix is synthesized
Figure GDA0002721857300000142
By a matrix of four constants
Figure GDA0002721857300000143
Combined to form a constant matrix
Figure GDA0002721857300000144
Is the product of a constant matrix delta and a constant matrix tau', i.e.
Figure GDA0002721857300000145
The constant matrix delta is a mapping matrix whose function is to map GF (2)8) Elements on the domain are mapped onto the composite domain. The constant matrix τ' is a constant matrix specified by the inverse affine operation in the inverse S-box operation. The synthesis matrix multiplication unit 1 can be expressed by a specific formula as:
Figure GDA0002721857300000146
operation result
Figure GDA0002721857300000147
And further output to a constant addition unit.
A constant addition unit for adding the vector
Figure GDA0002721857300000148
And constant vector omegaλAddition operation, constant vector omegaλBy four constants ωλCombined, i.e. omegaλ＝[ωλ,ωλ,ωλ,ωλ]TWherein constant ωλIs the product of a constant matrix delta, a constant matrix tau' and a constant omega, i.e. omegaλThe constant ω is a byte constant specified by the inverse affine operation in the inverse S-box operation. The specific expression form of the constant addition operation unit is as follows:
Figure GDA0002721857300000149
operation result
Figure GDA00027218573000001410
And further outputting the result to a complex domain multiplication inverse operation unit.
A complex domain inverse multiplication unit for multiplying the vector
Figure GDA00027218573000001411
Is inverse operation of complex field multiplication, where the complex field is arbitrary and GF (2)8) A composite domain with homogeneous domains. The specific expression form of the composite domain multiplication inverse operation unit is as follows:
Figure GDA0002721857300000151
operation result
Figure GDA0002721857300000152
Further output to the selector S1.
The selector S1 is based on the selection signal S when performing first-round conversion1Select data to be input from the ciphertext input port as 0
Figure GDA0002721857300000153
Outputs the signal to a synthesis matrix multiplication unit 2, and performs normal round conversion and final round conversion based on a selection signal s1Selecting the inverse operation result of the multiplication in the composite domain as 1
Figure GDA0002721857300000154
Output to the synthesis matrix multiplication unit 2 as an output signal
Figure GDA0002721857300000155
The alternative selector 2 is expressed in the following specific form:
Figure GDA0002721857300000156
a synthesis matrix multiplication unit 2 for multiplying the data vectors
Figure GDA0002721857300000157
And a key vector
Figure GDA0002721857300000158
Figure GDA0002721857300000159
Combined into a column vector
Figure GDA00027218573000001510
Key vector
Figure GDA00027218573000001511
With the key vector K in the encryption processvSame, will synthesize the matrix
Figure GDA00027218573000001512
And the column vector
Figure GDA00027218573000001513
Performing multiplication to synthesize matrix
Figure GDA00027218573000001514
The expression of (a) is specifically as follows:
Figure GDA00027218573000001515
wherein the matrix is synthesized
Figure GDA00027218573000001516
From a matrix of constants
Figure GDA00027218573000001517
Delta' combined to form a constant matrix
Figure GDA0002721857300000161
Is a constant matrix
Figure GDA0002721857300000162
And the constant matrix delta', i.e.
Figure GDA0002721857300000163
Constant matrix
Figure GDA0002721857300000164
Is a constant matrix
Figure GDA0002721857300000165
And the constant matrix delta', i.e.
Figure GDA0002721857300000166
Constant matrix
Figure GDA0002721857300000167
Is a constant matrix
Figure GDA0002721857300000168
And the constant matrix delta', i.e.
Figure GDA0002721857300000169
Constant matrix
Figure GDA00027218573000001610
Is a constant matrix
Figure GDA00027218573000001611
And the constant matrix delta', i.e.
Figure GDA00027218573000001612
Constant matrix
Figure GDA00027218573000001613
Are each GF (2)8) Domain multiplication by the constant x {01}16、×{09}16、×{0b}16、×{0d}16、×{0e}16In the form of a matrix; the constant matrix delta' is a mapping matrix whose role is to map elements on the complex field to GF (2)8) On the domain. The synthesis matrix multiplication unit 2 can be expressed by a specific formula as:
Figure GDA00027218573000001614
vector composed of first line to fourth line of operation result
Figure GDA00027218573000001615
And the fifth to eight lines
Figure GDA00027218573000001616
Respectively output to the selector S2, and the vectors composed of the ninth line to the twelfth line of the operation result
Figure GDA00027218573000001617
And outputting from a plaintext output port.
The selector S2 is based on the selection signal S when performing first-round conversion2Choose to put the vector 1
Figure GDA00027218573000001618
Figure GDA00027218573000001619
Fed back to the feedback data input port, and performs the ordinary round conversion according to the selection signal s2Choose to put the vector 1
Figure GDA00027218573000001620
Fed back to the feedback data output port with an output signal of
Figure GDA00027218573000001621
Figure GDA00027218573000001622
The alternative selector 2 is expressed in the following specific form:
Figure GDA00027218573000001623
the round conversion multiplexing circuit provided by the invention decrypts AES through the combination and synthesis operation of constant matrixesAll linear transformation operations in the algorithm are combined into two composite matrices, a composite matrix
Figure GDA0002721857300000171
And the synthesis matrix
Figure GDA0002721857300000172
Therefore, the key path of the AES decryption circuit is shortened, the implementation area of the AES decryption circuit is reduced, and researches show that the larger the circuit scale is, the higher the circuit efficiency is, so that the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, thereby being beneficial to improving the optimization efficiency of the circuit and reducing the implementation area of the AES decryption circuit; and a first-round conversion/common-round conversion/last-round conversion multiplexing circuit is constructed by a multiplexing synthesis matrix multiplication unit 1, a composite domain multiplication inverse operation unit, a synthesis matrix multiplication unit 2 and a constant addition operation unit, so that a large amount of circuit resources are saved.
The serial structure and the cycle structure are two basic structures realized by the AES decryption circuit, the AES decryption circuit with the serial structure is formed by adopting a parallel processing mode based on the proposed round conversion multiplexing circuit, and the AES decryption circuit with the cycle structure is formed by adopting a time-sharing multiplexing processing mode or a mode of combining time-sharing multiplexing and parallel processing.
Fig. 4 is a schematic structural diagram of an AES decrypting circuit according to the first embodiment of the present invention, and for convenience of description, only relevant portions of the first embodiment of the present invention are shown.
The AES decryption circuit comprises:
the data bit width of the register 1 and the register 2 is 16 bytes, a feedback data output port of the round conversion multiplexing circuit is connected with an input end of the register 1, an output end of the register 1 is connected with an input end of the register 2, and an output end of the register 2 is connected with a feedback data input end of the round conversion multiplexing circuit;
the decryption method of the AES decryption circuit provided in the first embodiment includes the steps of:
s1, the first 4 operations constitute first round conversionThe vector is formed by inputting four groups of four-byte ciphertext data into the round conversion multiplexing circuit from a ciphertext data input port respectively, and the selector S2 converts the first line to the fourth line of the operation result of the round conversion multiplexing circuit
Figure GDA0002721857300000173
Outputting the data to a register 1, and transmitting the stored data to a register 2 after the 16 bytes of data are stored in the register 1;
s2, 5 th to 4 th N of multiplexing wheel conversion circuitrThe sub-operation constitutes (N)r-1) general round conversion, the register 2 outputs 4 bytes of data to the feedback data input end of the round conversion multiplexing circuit at a time, and the selector S2 outputs the vector formed by the fifth row to the eighth row of the operation result through the operation of the round conversion multiplexing circuit
Figure GDA0002721857300000181
Outputting the data to a register 1, after the round conversion multiplexing circuit operates for four times, the register 1 transmits the stored data to a register 2 for the next round of ordinary round conversion operation (N)r-1) round normal round transform operation;
s3, multiplexing the (4N) th round of the conversion circuitr+1)～4(NrThe operation of +1) time forms the last round conversion, the register 2 outputs 4 bytes of data to the feedback data input end of the round conversion multiplexing circuit each time, and the (4N) th data is selected through the operation of the round conversion multiplexing circuitr+1)～4(Nr+1) times the data output from the plaintext data port is taken as plaintext.
Fig. 5 is a schematic structural diagram of an AES decrypting circuit according to a second embodiment of the present invention, and for convenience of description, only relevant portions of the second embodiment of the present invention are shown.
The AES decryption circuit comprises:
the data bit width of the register 1 and the register 2 is 16 bytes, the feedback data output ports of the two round conversion multiplexing circuits are connected with the input end of the register 1, the output end of the register 1 is connected with the input end of the register 2, and the output end of the register 2 is connected with the feedback data input ends of the two round conversion multiplexing circuits.
The decryption method of the AES decryption circuit provided in the second embodiment includes the steps of:
s1, the first 2 operations constitute first round conversion, which means four bytes of ciphertext data are input into two round conversion multiplexing circuits from ciphertext data input ports, and the selector S2 converts the vector composed of the first line to the fourth line of the calculation result of the round conversion multiplexing circuits
Figure GDA0002721857300000182
Outputting the data to a register 1, and transmitting the stored data to a register 2 after the 16 bytes of data are stored in the register 1;
s2, 3 rd to 2 nd N of multiplexing round conversion circuitrThe sub-operation constitutes (N)r-1) common round conversion, the register 2 outputs two groups of 4 bytes data at a time, the two groups of 4 bytes data are respectively transmitted to the feedback data input ends of the two round conversion multiplexing circuits, and the selector S2 makes the vector composed of the fifth row vector to the eighth row vector of the operation result through the operation of the round conversion multiplexing circuits
Figure GDA0002721857300000193
Outputting the data to a register 1, after each round of operation of the conversion multiplexing circuit is performed twice, the register 1 transmits the stored data to a register 2 for the next round of ordinary conversion operation, and the operation is performed (N)r-1) round normal round transform operation;
s3, multiplexing (2N) th of round converting circuitr+1)～2(Nr+1) operation to form last round conversion, the register 2 outputs two groups of 4 bytes data each time, and respectively transmits the data to the feedback data input ends of the two round conversion multiplexing circuits, and the (2N) th data is selected through the operation of the round conversion multiplexing circuitsr+1)～2(Nr+1) times the data output from the plaintext data port is taken as plaintext.
Fig. 6 is a schematic structural diagram of an AES decryption circuit according to a third embodiment of the present invention, and for convenience of description, only relevant portions of the third embodiment of the present invention are shown.
The AES decryption circuit comprises:
the data bit width of the register is 16 bytes, the feedback data output ports of the four-wheel conversion multiplexing circuit are connected with the input end of the register, and the output end of the register is connected with the feedback data input end of the four-wheel conversion multiplexing circuit.
The decryption method of the AES decryption circuit provided in the third embodiment includes the steps of:
s1, the first operation forms first round conversion, the first round conversion means four groups of four bytes of cipher text data are input into four round conversion multiplexing circuits from cipher text data input ports, the selector S2 makes the first line to the fourth line of the result of the round conversion multiplexing circuits
Figure GDA0002721857300000191
Outputting the data to a register;
s2, 2 nd to N th of multiplexing round conversion circuitrThe sub-operation constitutes (N)r-1) general round conversion, the register outputs four groups of 4 bytes data at a time, the four groups of 4 bytes data are respectively transmitted to feedback data input ends of four round conversion multiplexing circuits, and through the operation of the round conversion multiplexing circuits, the selector S2 enables vectors consisting of vectors of the fifth row to the eighth row of the operation result
Figure GDA0002721857300000192
Output to the register for the next round of conversion operation (N)r-1) round normal round transform operation;
s3, multiplexing the (N) th of the round converting circuitr+1) operation to form last round conversion, the register outputs four groups of 4 bytes data each time, and transmits the data to the feedback data input end of four round conversion multiplexing circuits, and the (N) th data is selected through the operation of the round conversion multiplexing circuitsr+1) times the data output from the plaintext data port is taken as plaintext.
Compared with the AES decryption circuit with the serial structure, the AES decryption circuit with the circular structure has the advantages that the circuit area is greatly reduced, and therefore the AES decryption circuit is suitable for a data processing circuit with limited area; but the AES decryption circuit with the serial structure adopts the pipeline technology, so that the circuit processing speed can be greatly improved, and the AES decryption circuit is suitable for a high-speed data processing circuit, so that the structure of a common round conversion circuit can be designed according to actual requirements;
the AES decryption circuit is formed based on a round conversion multiplexing circuit, the round conversion multiplexing circuit combines all linear conversion operations in the AES decryption algorithm into two synthetic matrixes through combination and synthesis operation of constant matrixes, and the synthetic matrixes
Figure GDA0002721857300000201
And the synthesis matrix
Figure GDA0002721857300000202
Therefore, the key path of the AES decryption circuit is shortened, the implementation area of the AES decryption circuit is reduced, and researches show that the larger the circuit scale is, the higher the circuit efficiency is, so that the invention combines a plurality of small-scale linear operation units into large-scale linear operation through matrix combination and synthesis, thereby being beneficial to improving the optimization efficiency of the circuit and reducing the implementation area of the circuit;
and a first-round conversion/common-round conversion/last-round conversion multiplexing circuit is constructed by a multiplexing synthesis matrix multiplication unit 1, a composite domain multiplication inverse operation unit, a synthesis matrix multiplication unit 2 and a constant addition operation unit, so that a large amount of circuit resources are saved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (4)

1. A round robin circuit, wherein the round robin circuit comprises:
a synthesis matrix multiplication unit 1, a constant addition unit, a complex domain inverse multiplication unit, a selector S1, a synthesis matrix multiplication unit 2, and a selector S2, the input end of the synthesis matrix multiplication arithmetic unit 1 is connected with the feedback data input port, the output end of the synthesis matrix multiplication arithmetic unit is connected with the input end of the constant addition arithmetic unit, the output end of the constant addition arithmetic unit is connected with the input end of the composite domain multiplication inverse arithmetic unit, the output end of the composite domain multiplication inverse arithmetic unit is connected with one input end of the selector S1, the other input end of the selector S1 is connected with the ciphertext data input port, the output end of the selector S1 and the key input port are both connected with the input end of the synthesis matrix multiplication arithmetic unit 2, two output ends of the synthesis matrix multiplication arithmetic unit 2 are respectively connected with two input ends of the selector S2, and the third output end of the synthesis matrix multiplication arithmetic unit 2 is;
a composite matrix multiplication unit 1 for multiplying the composite matrix
Figure FDA0002884161730000011
With column vectors input from feedback data input ports
Figure FDA0002884161730000012
Performing multiplication operation to obtain operation result
Figure FDA0002884161730000013
And outputting the output to a constant addition operation unit, wherein the expression of the synthesis matrix is specifically as follows:
Figure FDA0002884161730000014
a constant addition unit for adding the vector
Figure FDA0002884161730000015
And constant vector, i.e. omegaλ＝[ωλ,ωλ,ωλ,ωλ]TAdding the result of the operation
Figure FDA0002884161730000016
Output to the inverse operation unit of the multiplication in the complex domain
Figure FDA0002884161730000017
Sequentially representing column vectors
Figure FDA0002884161730000018
Four elements of (a), constant ωλIs the product of a constant matrix delta, a constant matrix tau' and a constant omega, i.e. omegaλδ × τ' × ω, constant matrix
Figure FDA0002884161730000019
Is the product of a constant matrix delta and a constant matrix tau', i.e.
Figure FDA00028841617300000110
The constant ω is a byte constant specified by the inverse affine operation in the inverse S-box operation, the constant matrix τ' is a constant matrix specified by the inverse affine operation in the inverse S-box operation, and the constant matrix δ is a mapping matrix, the function of which is to map GF (2)8) Mapping elements on the domain to the composite domain;
a complex domain inverse multiplication unit for multiplying the vector
Figure FDA00028841617300000111
Each byte in the data processing system is subjected to complex domain inverse multiplication, and the operation result is obtained
Figure FDA00028841617300000112
Output to the selector S1;
when first-pass conversion is performed, the selector S1 selects data to be input from the ciphertext data input port
Figure FDA0002884161730000021
Outputs the result to a synthesis matrix multiplication unit 2, and selects a result of inverse multiplication of the composite domain by a selector S1 when performing normal round conversion and final round conversion
Figure FDA0002884161730000022
Output to the synthesis matrix multiplication unit 2;
a synthesis matrix multiplication unit 2 for combining the data vectors outputted from the selector S1
Figure FDA0002884161730000023
And a key vector
Figure FDA0002884161730000024
Combined into a column vector
Figure FDA0002884161730000025
Key vector
Figure FDA0002884161730000026
With the key vector K in the encryption processvSame, will synthesize the matrix
Figure FDA0002884161730000027
And the column vector
Figure FDA0002884161730000028
Performing multiplication to synthesize matrix
Figure FDA0002884161730000029
The expression of (a) is specifically as follows:
Figure FDA00028841617300000210
constant matrix
Figure FDA00028841617300000211
Is a constant matrix
Figure FDA00028841617300000212
And the constant matrix delta', i.e.
Figure FDA00028841617300000213
Constant matrix
Figure FDA00028841617300000214
Is a constant matrix
Figure FDA00028841617300000215
And the constant matrix delta', i.e.
Figure FDA00028841617300000216
Constant matrix
Figure FDA00028841617300000217
Is a constant matrix
Figure FDA00028841617300000218
And the constant matrix delta', i.e.
Figure FDA00028841617300000219
Constant matrix
Figure FDA00028841617300000220
Is a constant matrix
Figure FDA00028841617300000221
And the constant matrix delta', i.e.
Figure FDA00028841617300000222
Constant matrix
Figure FDA00028841617300000223
Are each GF (2)8) Domain multiplication by the constant x {01}16、×{09}16、×{0b}16、×{0d}16、×{0e}16In the form of a matrix; the constant matrix delta' is a mapping matrix;
vector composed of first line to fourth line of operation result
Figure FDA00028841617300000224
And the fifth to eighth lines
Figure FDA00028841617300000225
Respectively output to the selector S2, and the vectors composed of the ninth line to the twelfth line of the operation result
Figure FDA00028841617300000226
Outputting from a plaintext data output port;
in the first-pass conversion, the selector S2 selects the vector
Figure FDA0002884161730000031
Fed back to the feedback data input port, and the selector S2 selects the vector to be converted when performing the ordinary round conversion
Figure FDA0002884161730000032
Fed back to the feedback data output port.
2. An AES decryption circuit based on the round robin circuit of claim 1, wherein the AES decryption circuit comprises:
the feedback data output port of the round conversion multiplexing circuit is connected with the input end of the register 1, the output end of the register 1 is connected with the input end of the register 2, and the output end of the register 2 is connected with the feedback data input port of the round conversion multiplexing circuit;
the data bit width of register 1 and register 2 is 16 bytes.
3. An AES decryption circuit based on the round robin circuit of claim 1, wherein the AES decryption circuit comprises:
the device comprises two multiplexing round conversion circuits, a register 1 and a register 2, wherein feedback data output ports of the two round conversion multiplexing circuits are connected with the input end of the register 1, the output end of the register 1 is connected with the input end of the register 2, and the output end of the register 2 is connected with feedback data input ports of the two round conversion multiplexing circuits;
the data bit width of register 1 and register 2 is 16 bytes.
4. An AES decryption circuit based on the round robin circuit of claim 1, wherein the AES decryption circuit comprises:
the four-wheel conversion multiplexing circuit comprises four multiplexing wheel conversion circuits and a register, wherein the feedback data output ports of the four wheel conversion multiplexing circuits are connected with the input end of the register, and the output end of the register is connected with the feedback data input ports of the four wheel conversion multiplexing circuits;
the data bit width of the register is 16 bytes.
CN201810597055.3A 2018-06-11 2018-06-11 Round conversion multiplexing circuit and AES decryption circuit Active CN108809627B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810597055.3A CN108809627B (en) 2018-06-11 2018-06-11 Round conversion multiplexing circuit and AES decryption circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810597055.3A CN108809627B (en) 2018-06-11 2018-06-11 Round conversion multiplexing circuit and AES decryption circuit

Publications (2)

Publication Number Publication Date
CN108809627A CN108809627A (en) 2018-11-13
CN108809627B true CN108809627B (en) 2021-03-05

Family

ID=64089039

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810597055.3A Active CN108809627B (en) 2018-06-11 2018-06-11 Round conversion multiplexing circuit and AES decryption circuit

Country Status (1)

Country Link
CN (1) CN108809627B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109660333A (en) * 2019-01-25 2019-04-19 芜湖职业技术学院 AES decryption multiplexing round transformation arithmetic element structure
CN109639408A (en) * 2019-01-25 2019-04-16 芜湖职业技术学院 A kind of AES decryption multiplexing round transformation circuit structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102780557A (en) * 2012-07-10 2012-11-14 记忆科技(深圳)有限公司 Method and device for AES (advanced encryption standard) encryption/decryption with selection gate optimization
CN106921487A (en) * 2017-03-01 2017-07-04 芜湖职业技术学院 Reconfigurable S-box circuit structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103516512A (en) * 2013-10-21 2014-01-15 深圳市芯通信息科技有限公司 Encryption and decryption method and encryption and decryption device based on AES (advanced encryption standard) algorithm
CN206585573U (en) * 2017-03-01 2017-10-24 芜湖职业技术学院 reconfigurable S-box circuit structure
CN106992852B (en) * 2017-05-08 2023-09-15 芜湖职业技术学院 Reconfigurable S-box circuit structure applied to AES and Camellia cryptographic algorithms
CN107181586B (en) * 2017-05-22 2023-09-15 芜湖职业技术学院 Reconfigurable S-box circuit structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102780557A (en) * 2012-07-10 2012-11-14 记忆科技(深圳)有限公司 Method and device for AES (advanced encryption standard) encryption/decryption with selection gate optimization
CN106921487A (en) * 2017-03-01 2017-07-04 芜湖职业技术学院 Reconfigurable S-box circuit structure

Also Published As

Publication number Publication date
CN108809627A (en) 2018-11-13

Similar Documents

Publication Publication Date Title
CN109033892B (en) Rotation Multiplexing Circuit and AES Decryption Circuit Based on Synthesis Matrix
CN106921487A (en) Reconfigurable S-box circuit structure
CN107181586A (en) reconfigurable S-box circuit structure
CN207184503U (en) Reconfigurable S-box circuit structure
CN109150495B (en) Round conversion multiplexing circuit and AES decryption circuit thereof
CN108933652B (en) Ordinary round of transform arithmetic element, ordinary round of transform circuit and AES decryption circuit
CN109039583B (en) Multiplexing rotation circuit, AES encryption circuit and encryption method
CN108809627B (en) Round conversion multiplexing circuit and AES decryption circuit
CN109033893B (en) AES encryption unit, AES encryption circuit and encryption method based on synthetic matrix
CN109033847B (en) AES encryption operation unit, AES encryption circuit and encryption method thereof
CN206585573U (en) reconfigurable S-box circuit structure
CN108566271B (en) Multiplexing rotation circuit, AES encryption circuit and encryption method thereof
CN108964875B (en) Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES decryption circuit
CN109033023B (en) Ordinary round conversion operation unit, ordinary round conversion circuit and AES encryption circuit
CN108989018B (en) AES encryption unit, AES encryption circuit and encryption method
Bittencourt et al. CLEFIA implementation with full key expansion
Abebe Lightweight and Efficient Architecture for AES Algorithm based on FPGA
CN109150496B (en) AES encryption operation unit, AES encryption circuit and encryption method
CN108964876B (en) Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES encryption circuit
CN109033894B (en) Ordinary round conversion arithmetic unit, ordinary round conversion circuit and AES encryption circuit thereof
CN109639408A (en) A kind of AES decryption multiplexing round transformation circuit structure
CN109936440B (en) Multiplexing Round Transformation Operation Unit and Construction Method in AES Decryption Circuit
Lanjewar et al. Implementation of AES-256 Bit: A Review
Jain et al. An Inner Round Pipeline Architecture Hardware Core for AES
Razik et al. Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant