CN108807422B - Array substrate manufacturing method, array substrate and display panel - Google Patents

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display panel. The grid electrode layer is obtained by etching the grid electrode material layer twice, and the polycrystalline silicon material layer is subjected to ion doping twice, so that the polycrystalline silicon layers corresponding to low-doped regions with different lengths of different thin film transistors are obtained under the condition that no photomask is added, and the manufacturing cost of the array substrate and the manufacturing cost of the display panel are reduced.

Description

Fabrication method of array substrate, array substrate and display panel

technical field

The present invention relates to the field of display technology, and in particular, to a method for fabricating an array substrate, an array substrate, and a display panel.

Background technique

Polysilicon array substrates are widely used in small and medium-sized high-resolution liquid crystal display panels (LCDs) or organic light-emitting display panels (OLEDs) due to their high carrier mobility.

In the traditional polycrystalline silicon array substrate, in order to effectively improve the reliability of the TFT device in the polycrystalline silicon array substrate, to reduce the hot carrier effect caused by the horizontal or lateral electric field of the TFT device, and to reduce the negative bias condition caused by excessively large Optical display defects such as Crosstalk, flicker, contrast, etc. caused by the leakage current of TFT devices are usually prepared by a NP IMP MASK and GE self-alignment technology to form a low-doped and high-impedance LDD region (MASK LDD), which has an equivalent effect. A large resistor is placed in series across the channel. The polysilicon array substrate includes a variety of different thin film transistors (TFTs) for realizing different functions. For different thin film transistors, the corresponding lengths of the low-doped regions of the polysilicon layer are different. In the prior art, the polysilicon layer is generally patterned through a mask to obtain low-doped regions with different lengths corresponding to different thin film transistors. However, this process will add a mask, thereby increasing the manufacturing cost of the array substrate.

SUMMARY OF THE INVENTION

The present invention provides a method for fabricating an array substrate, the array substrate, and a display panel including the array substrate. While obtaining low-doped regions of different lengths, it is not necessary to add a mask, thereby reducing the manufacturing cost of the array substrate. .

The manufacturing method of the array substrate comprises the steps of:

A substrate is provided, a polysilicon material layer is formed on the substrate, and the polysilicon material layer is patterned to obtain a polysilicon pattern layer; the polysilicon pattern layer includes a first polysilicon pattern and a second polysilicon pattern;

A gate insulating layer and a gate material layer are sequentially formed on the polysilicon pattern layer, and the gate material layer is patterned through a second mask to obtain a gate pattern layer; the gate pattern layer includes a first gate pattern, a second gate pattern, and one or more spaced auxiliary patterns on at least one side of the second gate pattern, the first gate pattern and the second gate pattern both include a a portion and a second portion on both sides of the first portion; the first gate pattern is stacked on the first polysilicon pattern and partially covers the first polysilicon in a direction perpendicular to the substrate a silicon pattern; the second gate pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in a direction perpendicular to the substrate;

The polysilicon pattern layer is heavily doped from one side of the gate pattern layer, and the region of the first polysilicon pattern not covered by the first gate pattern is doped to form a highly doped region; the The region of the second polysilicon pattern layer not covered by the second gate pattern and the auxiliary pattern is doped to form a highly doped region;

etching the gate pattern layer to etch away the auxiliary pattern, etch away the second part of the first gate pattern to obtain a first gate, and etch the second gate The second part of the pattern is etched away to obtain a second gate electrode, and the first gate electrode and the second gate electrode are both located in the gate electrode layer;

The polysilicon pattern layer is lightly doped from one side of the gate layer, so that a region corresponding to the second portion of the first gate pattern is formed into a low-doped region of the first polysilicon pattern, A region corresponding to the second part of the second gate pattern and a region covered by the auxiliary pattern form a low-doped region of the second polysilicon pattern; the region corresponding to the first gate forms the The channel region of the first polysilicon pattern, and the region corresponding to the second gate forms the channel region of the second polysilicon pattern.

Wherein, after obtaining the first polysilicon pattern and the second polysilicon pattern, the steps further include:

A flat layer is formed on the gate layer and the gate insulating layer not covered by the gate layer, and a pixel electrode and a signal line are formed on the flat layer, and the pixel electrode is connected to the first through a via hole. The highly doped region on one side of the channel region of a polysilicon pattern is electrically connected, and the signal trace is electrically connected to the highly doped region of the first polysilicon pattern that is not electrically connected to the pixel electrode, and the Both sides of the channel region of the second polysilicon layer are electrically connected to the highly doped regions away from the channel region.

Wherein, before forming the polysilicon material layer on the substrate, it also includes the steps:

A buffer layer is formed on the substrate, and the buffer layer is located between the substrate and the polysilicon material layer.

Wherein, before forming the buffer layer on the substrate, it also includes the steps:

A light-shielding material layer is formed on the substrate, and the light-shielding material layer is patterned to obtain a light-shielding layer. The light-shielding layer includes a plurality of light-shielding regions arranged in a spaced array, and each of the light-shielding regions is on the positive side of the polysilicon material layer. The projection covers the channel region of the first polysilicon pattern.

Wherein, the heavy doping and the light doping are performed by GE self-alignment technology and ion doping technology to obtain the highly doped region and the low doped region.

The array substrate includes a first thin film crystal and a second thin film transistor; the first thin film transistor includes a first polysilicon layer, the second thin film transistor includes a second polysilicon layer; the first polysilicon The layer and the second polysilicon layer are located in the same layer; the first polysilicon layer and the second polysilicon layer both include a channel region, a low-doped region and a high-doped region, and the channel region Both sides are provided with the low-doped region and the high-doped region; both sides of the channel region of the first polysilicon layer include a low-doped region and a high-doped region, so The low-doped region is located between the channel region and the highly-doped region; at least one side of the channel region of the second polysilicon layer includes at least two low-doped regions and at least two a number of high-doped regions, the high-doped regions and the low-doped regions are alternately arranged, and the low-doped regions are close to the channel region relative to the high-doped regions; the first polysilicon The length of the low-doped region of the layer is the same as the length of one of the at least two low-doped regions of the second polysilicon layer that is adjacent to the channel region.

Wherein, a first gate insulating layer and a first gate are stacked on the first polysilicon layer in sequence; a second gate insulating layer and a second gate are stacked on the second polysilicon layer in sequence; The first gate insulating layer and the second gate insulating layer are located in the same layer and connected; the first gate and the second gate are located in the same layer and arranged at intervals; the first gate is located in the The projection on the first polysilicon layer perpendicular to the first polysilicon layer covers the first gate; the projection of the second gate on the second polysilicon layer is perpendicular to the first gate The projection of two polysilicon layers covers the second gate.

Wherein, the first polysilicon layer and/or the second polysilicon layer is a U-shaped polysilicon layer or a square-shaped polysilicon layer.

Wherein, the low-doped regions and the high-doped regions on both sides of the channel regions of the first thin film transistor and the second thin film transistor are symmetrically arranged.

The display panel includes the array substrate.

In the present invention, the gate layer is obtained by etching the gate material layer twice, and the polysilicon material layer is ion-doped twice, so as to obtain the thin film transistors corresponding to different types without adding a mask. of different lengths of the polysilicon layer of the low-doped regions. Specifically, in the present invention, the low-doped region of the second polysilicon layer includes a region corresponding to the auxiliary pattern, and the second gate pattern forms the second gate and is etched away and the low-doped region of the first polysilicon layer only includes the region corresponding to the portion etched away by the first gate pattern to form the first gate. In addition, since the etching time for the first gate pattern and the second gate is the same when the second etching is performed, the first gate pattern and the second gate pattern are etched away. The sizes of the parts are the same, therefore, the length of the low-doped region of the second polysilicon layer of the present invention is greater than the length of the low-doped region of the first polysilicon layer. Thus, low-doped regions corresponding to different lengths of different thin film transistors can be obtained without adding a photomask.

Description of drawings

In order to illustrate the structural features and effects of the present invention more clearly, the following detailed description will be given in conjunction with the accompanying drawings and specific embodiments.

1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention;

FIG. 2 is a flow chart of the fabrication of the array substrate according to the embodiment of the present invention;

3-7 are cross-sectional views of each step of the manufacturing process of the array substrate according to the embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Wherein, the accompanying drawings are only used for exemplary description, and are only schematic diagrams, which should not be construed as limitations on the present patent.

The present invention provides a display panel for displaying pictures. The display panel may be a liquid crystal display panel (LCD display panel) or a light emitting diode display panel (OLED display panel). The display panel includes an array substrate. Moreover, when the display panel is a liquid crystal display panel, the display panel further includes a color filter substrate opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate; When the panel is a light-emitting diode display panel, the display panel further includes a light-emitting layer and a cathode layer disposed on the array substrate.

The array substrate includes a display area and a non-display area surrounding the display area. The array substrate includes a variety of different thin film transistors. For example, the various types of thin film transistors include thin film transistors located in the display area for controlling the light emission of pixel units, electrostatic protection thin film transistors (ESD TFTs) located in the non-display area, and demux TFTs Wait. Wherein, due to the different sizes and functions of the different thin film transistors, the lengths of the low-doped regions (LDDs) of the different thin film transistors are different, so as to adaptively reduce the hot carrier effect of the thin film transistors , thereby improving the reliability of the thin film transistor. Optical defects such as crosstalk and flicker are avoided in the display panel. The present invention obtains different low-doped regions (LDDs) of different lengths of the thin film transistors without adding a photomask. For example, the length of the low-doped region of the ESD protection thin film transistor is generally 2-3 times the length of the low-doped region of the thin film transistor located in the display region. The following description will be given by taking the thin film transistors located in the display area for controlling the light emission of the pixel units and the ESD protection thin film transistors located in the non-display area as examples.

Please refer to FIG. 1 , the present application provides an array substrate 100 . The array substrate 100 includes a first thin film transistor 10 and a second thin film transistor 20 . In this embodiment, the first thin film transistor is a thin film transistor located in the display area; the second thin film transistor 20 is an electrostatic protection thin film transistor located in the non-display area. The first thin film transistor 10 includes a first polysilicon layer 11 , a first gate insulating layer 12 and a first gate 13 that are stacked in sequence. The second thin film transistor 20 includes a second polysilicon layer 21 , a second gate insulating layer 22 and a second gate 23 that are stacked in sequence. The first polysilicon layer 11 and the second polysilicon layer 21 are located on the same layer and spaced apart, and the layers where the first polysilicon layer 11 and the second polysilicon layer 21 are located are polysilicon layers ; The first gate insulating layer 12 and the second gate insulating layer 22 are located in the same layer and connected, and the layer where the first gate insulating layer 12 and the second gate insulating layer 22 are located is the gate Extremely insulating layer; the first gate 13 and the second gate 23 are located in the same layer and are separated and insulated. The first polysilicon layer 11 and the second polysilicon layer 21 may be U-shaped polysilicon layers, square polysilicon layers or polysilicon layers of other shapes. Wherein, the U-shaped polysilicon layer can be obtained by bending the square polysilicon layer. The present invention is described by taking the first polysilicon layer 11 and the second polysilicon layer 21 as both square polysilicon layers as an example.

The first polysilicon layer 11 includes a channel region 111 , a low-doped region 112 and a high-doped region 113 . Both sides of the channel region 111 of the first polysilicon layer 11 include one of the low-doped regions 112 and one of the high-doped regions 113 , and the low-doped regions 112 are located in the channel between the region 111 and the highly doped region 113 . The projection of the first gate 13 on the first polysilicon layer 11 perpendicular to the first polysilicon layer 11 covers the channel region 111 . The second crystalline silicon layer includes a channel region 211 , a low-doped region 212 and a high-doped region 213 . At least one side of the channel region 211 includes at least two of the low-doped regions 212 and at least two of the high-doped regions 213 , the high-doped regions 213 and the low-doped regions 212 are alternately arranged , and the low-doped region 212 is closer to the channel region 211 than the high-doped region 213 . The projection of the second gate 23 on the second polysilicon layer 21 perpendicular to the second polysilicon layer 21 covers the channel region 211 . In this embodiment, two low-doped regions 212 and two of the high-doped regions 213 are disposed on both sides of the channel region 211 , and the two low-doped regions 212 and the two The highly doped regions 213 are alternately arranged. In this embodiment, the low-doped regions and the high-doped regions on both sides of the channel region 111 and the channel region 211 are symmetrical. In this embodiment, the two low-doped regions 212 on both sides of the channel region 211 are a first low-doped region 2121 and a second low-doped region 2122 respectively; The two highly doped regions 213 are a first highly doped region 2131 and a second highly doped region 2132, respectively. The first low-doped region 2121 , the first high-doped region 2131 , the second low-doped region 2122 , and the second high-doped region 2132 extend from the channel region 211 to the direction away from the channel region 211 The extension means that the first low-doped region 2121 is closest to the channel region 211 , and the second highly-doped region 2132 is farthest from the channel region 211 . In the present invention, the low-doped region 112 of the first polysilicon layer 11 and the at least two low-doped regions 212 of the second polysilicon layer 21 are close to the channel region 211 The lengths of the low-doped regions 212 are the same. In this embodiment, the lengths of the low-doped regions 112 of the first polysilicon layer 11 and the first low-doped regions 2121 of the second polysilicon layer 21 are the same. Wherein, the direction of the length refers to the direction extending from the channel region to the doped region. In another embodiment of the present invention, one side of the channel region has two low-doped regions and two high-doped regions, and the other side has one low-doped region and one high-doped region.

In the present invention, since the lengths of the low-doped regions 112 of the first polysilicon layer 11 and the first low-doped regions 2121 of the second polysilicon layer 21 are the same, and the length of the first low-doped regions 2121 of the second polysilicon layer 21 The low-doped region 212 of the second polysilicon layer 21 further includes a second low-doped region 2122. Therefore, the total length of the low-doped region 212 of the second thin film transistor 2021 of the present application is longer than that of the first low-doped region 212. The total length of the low-doped region 112 of the thin film transistor 1011 is long, which meets the requirements of practical use.

Further, a planarization layer 60 is stacked on the first gate 13 of the first thin film transistor 10 and the second gate 23 of the second thin film transistor 20 . A plurality of signal wirings (SD wirings) 70 and pixel electrodes 80 are arranged on the flat layer at intervals and insulated. Wherein, the pixel electrode 80 is located in the display area, and is electrically connected to a highly doped region 113 on the side of the channel layer of the first thin film transistor 10 through a via hole. A highly doped region 113 of the first thin film transistor 10 that is not connected to the pixel electrode 80 is electrically connected to a signal trace 70 through a via hole. One of the highly doped regions of the second thin film transistor 20 away from the channel region 211 is electrically connected to one of the signal traces 70 . In this embodiment, the second highly doped region 2132 of the second thin film transistor 20 is electrically connected to one of the signal traces 70 . Data signals are transmitted for the first thin film transistor 10 and the second thin film transistor 20 through the signal trace 70 .

Further, the array substrate 100 in the present invention further includes a substrate 30 on which the first thin film transistor 10 and the second thin film transistor 20 are formed. The substrate 30 may be a rigid substrate or a flexible substrate. For example, when a rigid LCD display panel or an OLED display panel is required, the substrate 30 is a rigid glass substrate; when a flexible display panel (such as an AMOLED panel) is required, the substrate 30 can be a flexible plastic substrate . In this embodiment, the substrate 30 is a glass substrate.

Further, in some embodiments of the present invention, a light shielding layer 40 and a buffer layer 50 are stacked on the substrate 30 in sequence. The light-shielding layer 40 is located in the display area, and includes a plurality of light-shielding areas arranged in a spaced array. The orthographic projection of each of the light-shielding regions on the first polysilicon layer 11 covers the channel region of the first polysilicon layer 11 to prevent light from irradiating the first polysilicon layer 11 the channel region 111, to avoid damage to the channel region 111 due to light. The buffer layer 50 is located between the light shielding layer 40 and the first polysilicon layer 11 and the second polysilicon layer 21 of the first thin film transistor 10 and the second thin film transistor 20, so as to ensure The first polysilicon layer 11 and the second polysilicon layer 21 can be well combined with the substrate 30 .

Referring to FIG. 2 , the present invention further provides a method for fabricating an array substrate 100 for fabricating the array substrate 100 . The patterning of the present invention includes exposure, development, etching and other process steps through a mask. Specifically, the method for fabricating the array substrate 100 of the present application includes the steps of:

Step 110 , referring to FIG. 3 , a substrate 30 is provided, a polysilicon material layer is formed on the substrate 30 , and the polysilicon material layer is patterned to obtain a polysilicon pattern layer. The polysilicon pattern layer includes a first polysilicon pattern 11a and a second polysilicon pattern 21a.

In this embodiment, the first polysilicon pattern 11a includes a first portion 111a, a second portion 112a on both sides of the first portion 111a, and a second portion 112a on a side of the second portion 112a away from the first portion 111a Three parts 113a. The second polysilicon pattern 21a includes a first portion 211a, a second portion 212a located on both sides of the first portion 211a, and a third portion disposed in sequence from a side of the second portion 212a away from the first portion 211a 213a, fourth portion 214a and fifth portion 215a.

In some embodiments of the present invention, before forming the polysilicon material layer on the substrate 30 , step 111 is further included: forming a buffer layer 50 on the substrate 30 . The buffer layer 50 is located between the substrate 30 and the polysilicon material layer. In other embodiments of the present invention, before forming the buffer layer 50 on the substrate 30, the method further includes step 112: forming a light-shielding material layer on the substrate 30, patterning the light-shielding material layer to obtain the light-shielding layer 40, and the The light shielding layer 40 includes a plurality of light shielding regions arranged in a spaced array. The buffer layer 50 covers the light shielding layer 40 .

Step 120 , referring to FIG. 4 , a gate insulating layer and a gate material layer are sequentially formed on the polysilicon pattern layer. The gate material layer is patterned to obtain a gate pattern layer.

The gate insulating layer includes a first gate insulating layer 12 and a second gate insulating layer 22 . The first gate insulating layer 21 is stacked over the first polysilicon pattern 11a; the first gate insulating layer 22 is stacked over the first polysilicon pattern 21a. The gate pattern layer includes a first gate pattern 13a, a second gate pattern 23a and one or more auxiliary patterns 24a arranged at intervals, the one or more auxiliary patterns 24a are located in the direction of the second gate pattern. at least one side of case 23a. The first gate pattern 13a, the second gate pattern 23a and the auxiliary pattern 24a are arranged at intervals. The first gate pattern 13a and the second gate pattern 23a each include a first portion and a second portion located on both sides of the first portion. The first gate pattern 13 a is stacked on the first polysilicon pattern 21 a and partially covers the first polysilicon pattern 21 a in a direction perpendicular to the substrate 30 . In this embodiment, the first gate pattern 13a covers the first portion 111a and the second portion 112a of the first polysilicon pattern in a direction perpendicular to the substrate 30 . Specifically, the first portion of the first gate pattern 13a corresponds to the first portion 111a of the first polysilicon pattern, and the second portion corresponds to the second portion 112a of the first polysilicon pattern. The second gate pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in a direction perpendicular to the substrate. In this embodiment, the second gate pattern 23a covers the first portion 211a and the second portion 212a of the second polysilicon pattern in a direction perpendicular to the substrate 30 . The auxiliary pattern 24a covers the fourth portion 214a of the second polysilicon pattern. Specifically, the first portion of the second gate pattern corresponds to the first portion 211 of the second polysilicon pattern, and the second portion of the second gate pattern corresponds to the second portion of the second polysilicon pattern. The second portion corresponds to the second portion 212a.

Step 130, referring to FIG. 5, heavily doping the polysilicon material layer from the gate pattern layer, and doping the area of the first polysilicon pattern 11a not covered by the first gate pattern 13a A highly doped region is formed; the region of the second polysilicon pattern 21a not covered by the second gate pattern 23a and the auxiliary pattern 24a is doped to form a highly doped region.

In the present invention, the polysilicon material layer is heavily doped from the gate pattern layer by gate self-alignment technology (GE self-alignment technology) and ion heavy doping technology. In this embodiment, the polysilicon material layer is heavily doped with N-type ions. Specifically, the N-type ions in this embodiment are phosphorus ions. Specifically, when the polysilicon material layer is heavily doped from the gate pattern layer, the N-type ions cannot pass through the gate pattern layer and diffuse to the polysilicon material layer. Therefore, the gate The positions covered by the gate pattern layer are not doped, and the positions not covered by the gate pattern layer are doped to form heavily doped regions. In this embodiment, the third portion 113a of the first polysilicon pattern 11a is heavily ion-doped to form the heavily doped region. The heavily doped region of the first polysilicon pattern 11a is the highly doped region 113 of the first polysilicon layer 11 in this embodiment; the heavily doped region of the second polysilicon pattern 21a The third part 213a and the fifth part 215a are heavily doped with ions to form the heavily doped region, and the heavily doped region obtained by the heavy doping of the third part 213a is the second polycrystal of this embodiment The first highly doped region 2131 of the silicon layer 21, the highly doped region obtained by heavily ion-doping the fifth portion 215a is the second highly doped region of the second polysilicon layer 21 of this embodiment Miscellaneous area 2132.

Step 140 , referring to FIG. 6 , further etching the gate pattern layer to obtain a gate layer, the gate layer including the first gate 13 and the second gate 23 . When the gate pattern layer is etched to obtain the gate layer, the auxiliary pattern 24a is etched away, the first gate pattern 13a is etched to obtain the first gate 13, and the second gate The second gate electrode 23 is obtained by etching the pole pattern 23a.

Specifically, wet etching or dry etching is performed on the gate pattern layer to simultaneously remove the auxiliary pattern 24a and partially etch the first gate pattern 13a to obtain the first gate pattern 13a. For the gate 13 , the second gate pattern 23 a is partially etched to obtain the second gate 23 . During etching, since the first gate pattern 13a and the second gate pattern 23a are simultaneously etched, the first gate pattern 13a and the gate pattern are etched away parts are the same size. The size of the first gate 13 and the second gate 23 obtained by etching the gate pattern layer compared to the size of the first gate pattern 13a and the second gate pattern 23a is reduced, so that the area of the first polysilicon pattern originally covered by the first gate pattern 13a is completely covered by the first gate 13 and originally covered by the second gate pattern 23a The region of the second polysilicon pattern is not completely covered by the second gate electrode 23, and the region of the second polysilicon pattern originally covered by the auxiliary pattern 24a is also not covered. In this embodiment, the first electrode covers the first portion 111a of the first polysilicon pattern. The second electrode covers the first portion 211a of the second polysilicon pattern.

Step 150 , referring to FIG. 7 , lightly doping the first polysilicon pattern and the second polysilicon pattern to obtain the first polysilicon layer 11 and the second polysilicon layer 21 .

The first polysilicon pattern is not covered by the first gate 13 and regions other than the highly doped region are doped to form a low doped region 112 of the first polysilicon layer 11, the The region covered by the first gate electrode 13 forms the channel region 111 of the first polysilicon layer 11 . In this embodiment, the second portion 112 a of the first polysilicon pattern 21 a is lightly doped to obtain the low-doped region 112 of the first polysilicon layer 21 . The region not covered by the second gate 23 and the position where the auxiliary pattern 24a is located are doped to form a low-doped region of the second polysilicon layer 21, and the region covered by the second gate 23 is formed The channel region 211 of the second polysilicon layer 21 . In this embodiment, the second portion 212a and the fourth portion 214a of the second polysilicon pattern are lightly doped to obtain the low-doped region 2121 and the low-doped region 2122 of this embodiment.

Further, step 160 is also included, please refer to FIG. 1 again, forming a flat layer 60 on the gate layer and the gate insulating layer not covered by the gate layer, and forming a pixel electrode 80 on the flat layer 60 and signal traces 70, the pixel electrode 80 is electrically connected to the highly doped region 113 on the side of the channel region 111 of the first polysilicon layer 11 through vias, and the signal traces 70 are connected to The highly doped region 113 of the first polysilicon layer that is not electrically connected to the pixel electrode, and the highly doped regions on both sides of the channel region 211 of the second polysilicon layer 21 away from the channel region 211 2132 Electrical Connections.

Specifically, a flat layer 60 and a pixel electrode material layer are sequentially formed on the gate layer and the gate insulating layer not covered by the gate layer; and the pixel electrode layer is obtained by patterning the pixel electrode material layer. The pixel electrode layer includes a plurality of pixel electrodes 80 arranged at intervals, and the pixel electrodes 80 are connected to the highly doped region 113 of the first polysilicon layer 11 through via holes. Further, a signal trace layer is formed on the flat layer 60, and the signal trace layer is patterned to obtain a plurality of signal traces 70, the signal traces 70 are connected to the first polysilicon through via holes The highly doped region 113 of the silicon layer 11 that is not electrically connected to the pixel electrode 80 is electrically connected to a highly doped region 2132 away from the channel region 211 on both sides of the channel region 211 of the second polysilicon layer 21 .

In the manufacturing method of the array substrate 100 of the present invention, the gate layer is obtained by etching the gate material layer twice, and the polysilicon material layer is ion-doped twice, so as to avoid increasing the amount of the mask. In this case, the polysilicon layers corresponding to the low-doped regions of different lengths of different thin film transistors are obtained. Specifically, in the present invention, the low-doped region of the second polysilicon layer 21 includes a low-doped region 2122 corresponding to the auxiliary pattern 24a, and the second gate pattern forms the first The low-doped region 2123 corresponding to the portion etched away by the two gates 23; and the low-doped region of the first polysilicon layer 11 only includes the first gate pattern to form the first gate 13 and The etched portion corresponds to the low-doped region 112 . In addition, when the second etching is performed, the first gate pattern and the second gate are simultaneously etched by the same method and the etching time is the same, so that the first gate pattern and the second gate are etched at the same time. The sizes of the etched portions of the two gate patterns are the same, that is, the lengths of the low-doped regions 2123 and the low-doped regions 112 are the same. Therefore, the total length of the low-doped region (the sum of the lengths of the low-doped region 2123 and the low-doped region 2122 ) of the second polysilicon layer 23 of the present invention is greater than that of the first polysilicon layer the total length of the low-doped region 112. That is, low-doped regions corresponding to different lengths of different thin film transistors can be obtained without adding a photomask. Further, since the first gate pattern is simultaneously etched in the present application, the method of the present application can simultaneously obtain the first polysilicon layer 11 and the second polysilicon layer with different total lengths of the low-doped regions. twenty one. Moreover, by adjusting the length of the auxiliary pattern 24a, the total length of the low-doped region of the second polysilicon layer 21 can be adjusted without any additional operation. Simple operation, saving production time. In addition, in the present invention, by simultaneously etching the first gate pattern and the second gate by the same method, the first polysilicon layer 11 and the second polysilicon layer of the present invention are obtained by doping. For the low-doped layer of the crystalline silicon layer 21, compared with the prior art in which the highly doped region and the low-doped region are obtained through a mask, the prior art performs ion doping due to a certain distance between the mask and the polysilicon layer. When doped, it is difficult to truly realize the left-right symmetry of the high-doped regions and the low-doped regions on both sides of the channel layer. However, since the present application does not need to use a photomask, the left-right symmetry of the high-doped regions and the low-doped regions on both sides of the channel layer can be better achieved.

The above are the preferred embodiments of the present invention, it should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications are also regarded as It is the protection scope of the present invention.

Claims (10)

1. The manufacturing method of the array substrate is characterized by comprising the following steps:

providing a substrate, forming a polycrystalline silicon material layer on the substrate, and patterning the polycrystalline silicon material layer to obtain a polycrystalline silicon pattern layer; the polycrystalline silicon pattern layer comprises a first polycrystalline silicon pattern and a second polycrystalline silicon pattern;

sequentially forming a grid insulation layer and a grid material layer on the polycrystalline silicon pattern layer, and patterning the grid material layer through a second photomask to obtain a grid pattern layer; the grid pattern layer comprises a first grid pattern, a second grid pattern and one or more auxiliary patterns which are arranged at intervals and positioned on at least one side of the second grid pattern, the auxiliary patterns and the second grid pattern are arranged at intervals, and the first grid pattern and the second grid pattern respectively comprise a first part and second parts positioned on two sides of the first part; the first grid pattern is laminated on the first polysilicon pattern and partially covers the first polysilicon pattern in the direction vertical to the substrate; the second grid pattern and the auxiliary pattern are stacked on the second polysilicon pattern and partially cover the second polysilicon pattern in the direction vertical to the substrate;

heavily doping the polysilicon pattern layer from one side of the gate pattern layer, wherein the region of the first polysilicon pattern not covered by the first gate pattern is doped to form a highly doped region; the region of the second polysilicon pattern which is not covered by the second grid pattern and the auxiliary pattern is doped to form a high-doped region;

etching the gate pattern layer to etch away the auxiliary pattern, etching away a second portion of the first gate pattern to obtain a first gate, and etching away a second portion of the second gate pattern to obtain a second gate, wherein the first gate and the second gate are both located on the gate layer;

lightly doping the polysilicon pattern layer from one side of the gate layer so as to form a low-doped region of the first polysilicon pattern in a region corresponding to the second part of the first gate pattern, and form a low-doped region of the second polysilicon pattern in a region corresponding to the second part of the second gate pattern and a region covered by the auxiliary pattern; the region corresponding to the first grid electrode forms the channel region of the first polysilicon pattern, and the region corresponding to the second grid electrode forms the channel region of the second polysilicon pattern.

2. The method for manufacturing an array substrate according to claim 1, wherein the step of obtaining the first polysilicon pattern and the second polysilicon pattern further comprises the steps of:

and forming a flat layer on the gate layer and the gate insulating layer which is not covered by the gate layer, forming a pixel electrode and a signal wire on the flat layer, electrically connecting the pixel electrode with the high-doping area on one side of the channel area of the first polysilicon pattern through a via hole, and electrically connecting the signal wire with the high-doping area of the first polysilicon pattern which is not electrically connected with the pixel electrode, and electrically connecting the two sides of the channel area of the second polysilicon pattern far away from the high-doping area of the channel area.

3. The method for fabricating an array substrate according to claim 1, further comprising, before forming the polysilicon material layer on the substrate, the steps of:

and forming a buffer layer on the substrate, wherein the buffer layer is positioned between the substrate and the polycrystalline silicon material layer.

4. The method for fabricating an array substrate according to claim 3, further comprising, before forming the buffer layer on the substrate, the steps of:

and forming a shading material layer on the substrate, patterning the shading material layer to obtain a shading layer, wherein the shading layer comprises a plurality of shading areas arranged at intervals in an array mode, and the orthographic projection of each shading area on the polycrystalline silicon material layer covers the channel area of the first polycrystalline silicon pattern.

5. The method of claim 1, wherein the heavily and lightly doping are performed by GE self-aligned and ion doping to obtain the highly and lightly doped regions.

6. An array substrate is characterized by comprising a first thin film transistor and a second thin film transistor; the first thin film transistor comprises a first polycrystalline silicon layer, and the second thin film transistor comprises a second polycrystalline silicon layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer are positioned on the same layer; the first polycrystalline silicon layer and the second polycrystalline silicon layer respectively comprise a channel region, a low-doped region and a high-doped region, and the low-doped region and the high-doped region are arranged on two sides of the channel region; the two sides of the channel region of the first polycrystalline silicon layer respectively comprise a low-doped region and a high-doped region, and the low-doped region is positioned between the channel region and the high-doped region; at least one side of the channel region of the second polycrystalline silicon layer comprises at least two low-doped regions and at least two high-doped regions, the high-doped regions and the low-doped regions are alternately arranged, and the low-doped regions are close to the channel region relative to the high-doped regions; the length of the low-doped region of the first polysilicon layer is the same as the length of one of the at least two low-doped regions of the second polysilicon layer that is close to the channel region.

7. The array substrate of claim 6, wherein a first gate insulating layer and a first gate are sequentially stacked on the first polysilicon layer; a second grid electrode insulating layer and a second grid electrode are sequentially laminated on the second polycrystalline silicon layer; the first grid electrode insulating layer and the second grid electrode insulating layer are positioned on the same layer and connected; the first grid and the second grid are positioned on the same layer and are arranged at intervals; the projection of the first grid electrode on the first polycrystalline silicon layer covers the channel region of the first polycrystalline silicon layer; the projection of the second grid electrode on the second polycrystalline silicon layer covers the channel region of the second polycrystalline silicon layer.

8. The array substrate of claim 6 or 7, wherein the first polysilicon layer and/or the second polysilicon layer is a U-shaped polysilicon layer or a block-shaped polysilicon layer.

9. The array substrate of claim 6, wherein the low doped region and the high doped region are symmetrically disposed on both sides of the channel region of the first thin film transistor and the second thin film transistor.

10. A display panel comprising the array substrate according to any one of claims 6 to 9.

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