CN108768360B - Overcurrent protection circuit - Google Patents
Overcurrent protection circuit Download PDFInfo
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- CN108768360B CN108768360B CN201810961875.6A CN201810961875A CN108768360B CN 108768360 B CN108768360 B CN 108768360B CN 201810961875 A CN201810961875 A CN 201810961875A CN 108768360 B CN108768360 B CN 108768360B
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- overcurrent protection
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- 238000001514 detection method Methods 0.000 claims abstract description 34
- 230000005669 field effect Effects 0.000 claims description 47
- 230000001960 triggered effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000013024 troubleshooting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
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Abstract
The invention discloses an overcurrent protection circuit which comprises a protection circuit body and a conduction detection circuit, wherein the conduction detection circuit is used for detecting the conduction condition of a related MOS tube in the protection circuit body and controlling whether the protection circuit body triggers an overcurrent protection mechanism according to a detection result. The invention can solve the problem of dead zone in time existing in the traditional overcurrent protection.
Description
Technical Field
The invention relates to an overcurrent protection technology, in particular to an overcurrent protection circuit with high reaction speed and good protection effect.
Background
Some integrated circuit pins are prone to malfunction or other cause of excessive current flow through the pins, resulting in undesirable consequences such as damage to the chip or system. Therefore, some integrated circuit pins, particularly those that may be subject to high currents, require the addition of an over-current protection circuit.
The overcurrent protection circuit has the function of taking certain measures to protect a circuit or a system after the current is large to a certain value. Certain measures include, but are not limited to, shutting down a chip pin or system, restarting a chip or system, returning a pin to a normal operating state after a certain time or after troubleshooting, etc.
Fig. 1 is a schematic diagram of a conventional overcurrent protection circuit. The principle is as follows: the PMOS tube P1 is a main heavy current driving tube, and the PMOS tube P2, the resistor R1 and the comparator COMP1 form a current detection module. When the integrated circuit pin Y1 is normally opened, the control end A is at a low level, and the PMOS tube P1 and the PMOS tube P2 are conducted. If the integrated circuit pin Y1 is connected with a load, current flows from the power supply VDD end to the pin Y1 end through the PMOS tube P1 and the PMOS tube P2. The current flowing through the PMOS tube P1 and the PMOS tube P2 has an approximate proportional relation with the channel width-to-length ratio, and the current flowing through the PMOS tube P2 and the resistor R1 are the same, so that the voltage at two ends of the resistor R1 can be detected to know the current flowing through the PMOS tube P1 and the PMOS tube P2, and when the voltage at two ends of the resistor R1 is larger than a certain threshold value, the protection mechanism can be triggered through the output end Y2 of the comparator COMP 1.
However, the conventional overcurrent protection circuit has the following disadvantages: when the control terminal a is not completely low level but is in a certain specific voltage range, the PMOS transistor P1 and the PMOS transistor P2 are not completely turned on, and if the integrated circuit pin Y1 is connected with a load in a certain range, the current flowing through the PMOS transistor P2 will be increased, and if the voltage at the two ends of R1 reaches the threshold value of the comparator COMP1, the output Y2 of the comparator will be caused to trigger the protection mechanism by mistake.
In order to solve the problem of error protection, the conventional over-current protection circuit is generally controlled by adding a delay circuit to avoid the situation, and the specific principle is that when the control terminal a is changed from a high level to a low level, a delay circuit is added to make the control terminal a completely change from a high level to a low level for a period of time, and the output Y2 of the comparator COMP1 cannot trigger the protection mechanism. The delay time of the added delay circuit is generally much longer than the time for the control terminal a to completely change from high level to low level for reliability. The time from the moment when the control end A is completely changed from the high level to the low level to the moment when the output Y2 of the comparator COMP1 can trigger the protection mechanism is not enough, the dead zone on the time of the overcurrent protection function exists, particularly in the application occasion with short requirement on the overcurrent protection response time, and the hidden danger exists.
Disclosure of Invention
The invention aims to overcome the defect that the prior art has a dead zone in the time of an overcurrent protection function, and provides a novel overcurrent protection circuit.
In order to achieve the above purpose, the present invention proposes the following technical scheme: the overcurrent protection circuit comprises a protection circuit body, a logic control circuit and a conduction detection circuit, wherein the protection circuit body comprises a current driving piece and a current detection module connected with the current driving piece, the current driving piece and the current detection module are both connected with an integrated circuit pin, the current driving piece, the current detection module and the conduction detection circuit are all connected with the same control end, and the current detection module triggers overcurrent protection after detecting that the current flowing through the integrated circuit pin is larger than a set threshold value; the output ends of the current detection module and the conduction detection circuit are connected to the input end of the logic control circuit, and the logic control circuit outputs corresponding control level according to the input ends of the current detection module and the conduction detection circuit to control the chip to trigger or not trigger overcurrent protection.
Preferably, the current driving element is a first field effect transistor, and a gate electrode of the first field effect transistor is connected to the control end.
Preferably, the current detection module comprises a second field effect tube, a first load and a first comparator, wherein the first load and the first comparator are connected in series with the second field effect tube, the grid electrode of the second field effect tube is connected with the control end, two input ends of the first comparator are respectively connected with two ends of the first load and are used for detecting the current flowing through the first load, and the output end of the first comparator is connected with the input end of the logic control circuit.
Preferably, the on detection circuit includes a third field effect transistor, a second load connected in series with the third field effect transistor, and a second comparator, wherein a gate of the third field effect transistor is connected to the control end, one of two input ends of the second comparator is connected between the second load and the third field effect transistor, the other end of the second comparator is connected to a reference voltage, and an output end of the second comparator is connected to an input end of the logic control circuit.
Preferably, the first, second and third field effect transistors are at least selected from PMOS transistors or NMOS transistors.
Preferably, the first load and the second load are at least selected as resistors or MOS transistors.
Preferably, when the first, second and third field effect transistors are PMOS transistors, the sources of the first, second and third field effect transistors are all connected to a power supply voltage, the gates are connected to the control end, the drain of the first field effect transistor is connected to the integrated circuit pin, the drain of the second field effect transistor is connected to the integrated circuit pin through a first load, and the drain of the third field effect transistor is grounded through a second load. The control level output by the second comparator is low level, and the logic control circuit does not trigger overcurrent protection; and on the contrary, the control level output by the second comparator is high, and the logic control circuit allows the over-current protection to be triggered.
Preferably, when the first, second and third field effect transistors are NMOS transistors, the sources of the first, second and third field effect transistors are all grounded, the gate is connected to the control end, the drain of the first field effect transistor is connected to the integrated circuit pin, the drain of the second field effect transistor is connected to the integrated circuit pin through a first load, and the drain of the third field effect transistor is connected to a power supply voltage through a second load. The control level output by the second comparator is low level, and the logic control circuit does not trigger overcurrent protection; and on the contrary, the control level output by the second comparator is high, and the logic control circuit allows the over-current protection to be triggered.
The beneficial effects of the invention are as follows: the problem of dead zone in time existing in traditional overcurrent protection is solved by adding a circuit for detecting whether the related MOS tube is fully conducted or not, specifically, when the MOS tube is detected to be not fully conducted, the control circuit does not trigger an overcurrent protection mechanism, and when the MOS tube is detected to be fully conducted, the overcurrent protection function can be very rapidly played, so that the dead zone in time of the overcurrent protection function does not exist in the circuit.
Drawings
FIG. 1 is a schematic diagram of a conventional over-current protection circuit;
FIG. 2 is a schematic diagram of an embodiment of the present invention;
Fig. 3 is a schematic structural view of an alternative embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
The invention discloses an overcurrent protection circuit which comprises a protection circuit body, a logic control circuit and a conduction detection circuit, wherein the conduction detection circuit is used for detecting the conduction condition of a related MOS tube in the protection circuit body and controlling whether a chip triggers an overcurrent protection mechanism or not according to a detection result.
Referring to fig. 1 to 3, the protection circuit body disclosed in the embodiment of the present invention is a conventional overcurrent protection circuit shown in fig. 1, and specifically includes a current driving element and a current detection module, where the current driving element may use a first field effect transistor, the first field effect transistor uses a PMOS transistor or an NMOS transistor, and takes a PMOS transistor P1 as an example, a gate of the PMOS transistor P1 is connected to a control terminal a, a source is connected to a power supply voltage VDD, and a drain is connected to an integrated circuit pin Y1.
In this embodiment, the current detection module specifically includes a second field effect transistor, a first load and a first comparator, where the second field effect transistor corresponds to the first field effect transistor, and the second field effect transistor may also be a PMOS transistor or an NMOS transistor, taking PMOS transistor P2 as an example, where the gate of PMOS transistor P2 is also connected to control terminal a, the source is connected to power supply voltage VDD, and the drain is connected to the first load.
In this embodiment, the first load is a resistor R1, one end of the resistor R1 is connected to the drain of the PMOS transistor P2, and the other end is connected to the integrated circuit pin Y1.
The two input ends of the first comparator are respectively connected with the two ends of the first load and used for detecting the current flowing through the first load, and the output end Y2 is connected with the input end Y2 of the logic control circuit. In this embodiment, the comparator COMP1 has its non-inverting input terminal connected between the drain of the PMOS transistor P2 and the resistor R1, its inverting input terminal connected between the resistor R1 and the integrated circuit pin Y1, and its output terminal Y2 connected to the input terminal Y2 of the logic control circuit.
Referring to fig. 2, the turn-on detection circuit disclosed in the embodiment of the present invention includes a third field effect transistor, a second load and a second comparator, corresponding to the first and second field effect transistors, where the third field effect transistor may also be a PMOS transistor or an NMOS transistor, and a PMOS transistor P3 is taken as an example, where a gate of the PMOS transistor P3 is also connected to the control terminal a, a source is connected to the power supply voltage VDD, and a drain is connected to the second load.
In this embodiment, the second load is a resistor R2, one end of the resistor R2 is connected to the drain electrode of the PMOS tube P3, and the other end is grounded.
One end of the two input ends of the second comparator is connected between the resistor R2 and the PMOS tube P3, the other end of the second comparator is connected with a reference voltage, and the output end of the second comparator is connected with the input end Y3 of the logic control circuit. In this embodiment, the comparator COMP2 has its non-inverting input connected between the drain of the PMOS transistor P3 and the resistor R2, its inverting input connected to the reference voltage VERF, and its output Y3 connected to the input Y3 of the logic control circuit.
The output end Y4 of the logic control circuit outputs a corresponding control level to the chip to control the triggering or non-triggering of the overcurrent protection.
The working principle of the invention is as follows: when the control terminal a is not at a completely low level, the PMOS transistor P3 is not completely turned on, and the current flowing through the PMOS transistor P3 and the resistor R2 is smaller, so that the voltage on the resistor R2 is smaller, that is, the voltage detected on the in-phase terminal of the comparator COMP2 is smaller, and when the detected voltage is smaller than the reference voltage VERF at the opposite-phase terminal thereof, the output terminal Y3 of the comparator COMP2 is at a low level, so as to control the logic control circuit, so that the output Y2 of the comparator COMP1 is shielded, and the logic control circuit cannot trigger the protection mechanism. At this time, the PMOS transistor P1 is not completely turned on, and the current flowing through the PMOS transistor P1 is small, so that no overcurrent protection is needed.
When the control terminal a is at a completely low level, the PMOS transistor P3 is completely turned on, and the current flowing through the PMOS transistor P3 and the resistor R2 is larger, so that the voltage on the resistor R3 is larger, that is, the voltage detected on the in-phase terminal of the comparator COMP2 is larger, and when the voltage is larger than the reference voltage VERF, the output Y3 of the comparator COMP2 outputs a high level, so that the logic control circuit can be controlled, and the normal triggering function can be realized.
As an alternative embodiment, as shown in FIG. 3, the over-current protection circuit for the system flowing into the pin Y1 of the integrated circuit is replaced by the NMOS transistor N1, the NMOS transistor N2 and the NMOS transistor N3 correspondingly by the PMOS transistor P1, the PMOS transistor P2 and the PMOS transistor P3 in FIG. 2, and other signals are correspondingly changed. Specifically, the gates of the NMOS transistor N1, the NMOS transistor N2, and the NMOS transistor N3 are all connected to the control terminal a, the sources are all grounded, the drain of the NMOS transistor N1 is connected to the integrated circuit pin Y1, the drain of the NMOS transistor N2 is connected to the integrated circuit pin Y1 through the resistor R1, and the drain of the NMOS transistor N3 is connected to the power supply voltage through the resistor R2. The operation principle of this circuit is similar to that of fig. 2, and will not be described again here.
It should be noted that the above two embodiments are only specific examples of the present invention, and on the basis of this, an overcurrent protection circuit formed by appropriate changes is also within the protection of the present invention. Variations include, but are not limited to, the in-phase and anti-phase terminal of the comparators (comparator COMP1, comparator COMP 2) being swapped, equivalent comparators being employed, the resistors (resistor R1, resistor R2) in fig. 1,2 being made of MOS transistors, etc. However, the core idea of the invention is to add a circuit for detecting whether the related MOS tube in the protection circuit body is completely conducted, so as to solve the problem of the dead zone in the existing time of the traditional overcurrent protection, and the problem is within the protection scope of the patent.
While the foregoing has been disclosed in the specification and drawings, it will be apparent to those skilled in the art that various substitutions and modifications may be made without departing from the spirit of the invention, and it is intended that the scope of the invention be limited not by the specific embodiments disclosed, but by the appended claims.
Claims (7)
1. An overcurrent protection circuit is characterized by comprising a protection circuit body, a logic control circuit and a conduction detection circuit,
The protection circuit body comprises a current driving piece and a current detection module connected with the current driving piece, wherein the current driving piece and the current detection module are both connected with an integrated circuit pin, and the current driving piece, the current detection module and the conduction detection circuit are all connected with the same control end;
The current detection module comprises a second field effect transistor, a first load and a first comparator, wherein the first load and the first comparator are connected in series with the second field effect transistor, the grid electrode of the second field effect transistor is connected with the control end, the two input ends of the first comparator are respectively connected with the two ends of the first load and are used for detecting the current flowing through the first load, and the output end of the first comparator is connected with the input end of the logic control circuit; the current detection module triggers overcurrent protection after detecting that the current flowing through the pin of the integrated circuit is larger than a set threshold value in the pin; the output ends of the current detection module and the conduction detection circuit are connected to the input end of the logic control circuit, and the logic control circuit outputs corresponding control level to control the chip to trigger or not trigger overcurrent protection according to the input of the current detection module and the conduction detection circuit;
The on detection circuit comprises a third field effect tube, a second load and a second comparator, wherein the second load and the second comparator are connected in series with the third field effect tube, the grid electrode of the third field effect tube is connected with the control end, one of two input ends of the second comparator is connected between the second load and the third field effect tube, the other end of the second comparator is connected with a reference voltage, and the output end of the second comparator is connected with the input end of the logic control circuit.
2. The overcurrent protection circuit of claim 1, wherein the current driver is a first fet having a gate coupled to the control terminal.
3. The overcurrent protection circuit of claim 2, wherein the first, second and third field effect transistors are selected from PMOS or NMOS transistors.
4. The overcurrent protection circuit of claim 2, wherein the first load and the second load are selected from resistors or MOS transistors.
5. The overcurrent protection circuit of claim 2, wherein when the first, second and third field effect transistors are PMOS transistors, the sources of the first, second and third field effect transistors are all connected to a power supply voltage, the gate is connected to the control terminal, the drain of the first field effect transistor is connected to the integrated circuit pin, the drain of the second field effect transistor is connected to the integrated circuit pin through a first load, and the drain of the third field effect transistor is grounded through a second load.
6. The overcurrent protection circuit of claim 2, wherein when the first, second and third field effect transistors are NMOS transistors, the sources of the first, second and third field effect transistors are all grounded, the gate is connected to the control terminal, the drain of the first field effect transistor is connected to the integrated circuit pin, the drain of the second field effect transistor is connected to the integrated circuit pin through a first load, and the drain of the third field effect transistor is connected to a supply voltage through a second load.
7. The overcurrent protection circuit according to claim 1, wherein the control level of the second comparator output is a low level, and the logic control circuit does not trigger the overcurrent protection; and on the contrary, the control level output by the second comparator is high, and the logic control circuit allows the over-current protection to be triggered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810961875.6A CN108768360B (en) | 2018-08-22 | 2018-08-22 | Overcurrent protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810961875.6A CN108768360B (en) | 2018-08-22 | 2018-08-22 | Overcurrent protection circuit |
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| Publication Number | Publication Date |
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| CN108768360A CN108768360A (en) | 2018-11-06 |
| CN108768360B true CN108768360B (en) | 2024-07-30 |
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| CN201810961875.6A Active CN108768360B (en) | 2018-08-22 | 2018-08-22 | Overcurrent protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115951752B (en) * | 2023-03-13 | 2023-06-06 | 唯捷创芯(天津)电子技术股份有限公司 | Low dropout linear voltage regulator with overcurrent protection, chip and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033155A (en) * | 2010-12-03 | 2011-04-27 | 苏州华芯微电子股份有限公司 | Current detection circuit and method |
| CN208608973U (en) * | 2018-08-22 | 2019-03-15 | 苏州华芯微电子股份有限公司 | A kind of current foldback circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11146690A (en) * | 1997-11-07 | 1999-05-28 | Ricoh Co Ltd | Protection circuit against overcurrent in scanner control of image formation device |
| CN104883162B (en) * | 2014-02-27 | 2019-03-12 | 快捷半导体(苏州)有限公司 | Overcurrent sensing circuit, method, load switch and portable device |
| CN103887761B (en) * | 2014-03-20 | 2017-08-08 | 深圳创维－Rgb电子有限公司 | PWM drive circuit |
| CN106020317B (en) * | 2016-05-26 | 2017-09-29 | 深圳市国微电子有限公司 | A kind of current foldback circuit of low pressure difference linear voltage regulator |
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2018
- 2018-08-22 CN CN201810961875.6A patent/CN108768360B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033155A (en) * | 2010-12-03 | 2011-04-27 | 苏州华芯微电子股份有限公司 | Current detection circuit and method |
| CN208608973U (en) * | 2018-08-22 | 2019-03-15 | 苏州华芯微电子股份有限公司 | A kind of current foldback circuit |
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| CN108768360A (en) | 2018-11-06 |
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