CN108767053B - Manufacturing method of novel infrared detector BIB silicon epitaxial wafer - Google Patents

Abstract

The invention relates to a method for manufacturing a silicon epitaxial wafer for a novel infrared detector BIB. The N-type <100> polished wafer heavily doped with As is selected, the resistivity is less than or equal to 0.004Ω.cm, and the substrate is not back-sealed. In order to reduce the influence of self-doping on the back, a silicon-encapsulated process is adopted. In-situ high-temperature polishing with HCl to remove surface impurities and defects and improve the surface quality of the substrate. Through the high-flow high-temperature blow-off process, the substrate self-doping is reduced. Using two-step epitaxy, the low-resistance absorbing layer and the intrinsic layer are grown separately, and the high-flow H2 is cooled and blown off between the two steps; the intrinsic layer is gas-corroded with a large flow before the epitaxial wafer is installed, and the epitaxial growth is low-speed and low-temperature. The invention meets the requirements of BIB device design by controlling the self-doping, the absorption layer and the substrate transition area are steep, and the intrinsic barrier layer has a wide flat area.

Description

A new type of infrared detector BIB silicon epitaxial wafer manufacturing method

technical field

The invention belongs to the field of semiconductor basic material silicon epitaxial wafers, and in particular relates to a method for manufacturing a novel infrared detector BIB (impurity band infrared detector) silicon epitaxial wafer.

Background technique

Barrier impurity (BIB) detectors have the advantages of wide wavelength coverage, low dark current, high photoconductive gain, fast response, and high radiation resistance. It uses impurity photoconductivity to detect, and because the impurity ionization energy is small, it can respond to longer wave infrared. Traditional extrinsic photoconductive (ESPC) infrared detectors require high doping concentration to improve absorption performance, but their maximum doping concentration is limited by the excessive dark current caused by the resulting impurity band conductance, BIB infrared The detector skillfully introduces an intrinsic layer (blocking layer) between the electrode and the infrared absorbing layer to block the conduction of dark current in the impurity band, so that it can have a higher doping concentration. The structural design of the barrier layer of the BIB device greatly reduces the dark current of the device, so the impurity concentration of the infrared absorption layer of the BIB device can be 2 orders of magnitude higher than that of the ESPC device (up to 10 ¹⁷ orders of magnitude), and the quantum efficiency is significantly improved. On the other hand, the increase in doping concentration and volume of BIB devices is much smaller than that of ESPC devices, which enhances its ability to regulate the impact of cosmic particles, which is beneficial to space-based astronomical infrared detection. In addition, due to the heavy doping effect, the impurity energy level in the BIB device expands into an impurity band, which further reduces the ionization energy of the impurity, and can realize longer-wavelength infrared detection.

The doped semiconductors of BIB detectors are mainly silicon, germanium and gallium arsenide. Because silicon materials are easy to obtain large-diameter and high-purity uniform silicon single crystals, and the silicon device process is mature, it has better uniformity, stability, and wide wavelength coverage, making silicon-based BIB focal plane devices among the mainstream detectors above 5 μm in astronomy.

The most important structures in the BIB detector are the blocking layer and the infrared absorbing layer, which is sandwiched between the low-resistance silicon substrate and the near-intrinsic blocking layer. The doping concentration of the absorbing layer is usually 10 ¹⁷ ~ 10 ¹⁸ cm ^-3 . In order to greatly improve the quantum efficiency, the thickness of the infrared absorbing layer is generally 10 ~ 45 μm; the ideal blocking layer must be as pure as possible, but the actual layer can generally reach 10 On the order of ¹³ cm ^-3 , the thickness is between 3 and 6 μm. These thin layers are usually doped by ion implantation and neutron transmutation to form the absorbing layer, but in order to reduce lattice damage, the doping concentration is generally not too high; and by epitaxy, high-concentration doping can be introduced during the growth process. miscellaneous. Due to the complexity of silicon epitaxial growth, the resistivity difference between the low-resistance absorbing layer and the intrinsic layer is 5 orders of magnitude, and the interlayer self-doping and cavity environment self-doping have a great influence on the resistivity of the intrinsic layer; and the new BIB infrared detection In order to ensure the accuracy of detection, the detector (blocking impurities with infrared detectors) requires the transition region between the absorption layer and the intrinsic layer to be as wide as possible, and the intrinsic resistivity is as high as possible; the self-doping and intrinsic layer requirements of the high-concentration absorption layer There is a strong conflict between the high resistivity and the narrow transition region, and it is difficult to grow a high-purity barrier layer with a wide flat region on the heavily doped absorber layer.

Therefore, a new technical solution is needed to solve the above problems.

Contents of the invention

Purpose of the invention: To provide a process technology for manufacturing silicon epitaxial wafers for infrared detectors BIB

Technical solution: In order to achieve the above object, the present invention can adopt the following technical solutions:

A method for manufacturing a novel infrared detector BIB silicon epitaxial wafer, the specific scheme is:

The substrate for BIB infrared detectors is a heavily As-doped N-type <100> polished sheet with a diameter of 15cm and a local flatness of ≤3μm, and a resistivity of ≤0.004Ω.cm, without a back-sealed substrate.

Selection of gas corrosion conditions: HCl in-situ high-temperature polishing, gas corrosion temperature 1160 ° C;

Using a two-step epitaxy method, the low-resistance absorber layer and the intrinsic layer are grown separately, i.e.,

The first step of epitaxy is the growth of N-type low-resistance absorption layer: trichlorosilicon is used as raw material, the growth temperature is 1030 ° C ~ 1060 ° C, the growth rate is 0.7 ~ 1.1 μm/min, no dilution, and phosphine doping flow 30-60sccm/min, and the corresponding epitaxial doping concentration is 10 ¹⁷ ～10 ¹⁸ cm ^-3 , and a low-resistance absorbing layer is prepared on the substrate; after the absorbing layer is prepared, the temperature is slowly lowered to room temperature, and at the same time, H2 is passed into it for purging. Forming a buffer layer with a concentration lower than that of the low-resistance absorber layer on the surface of the low-resistance absorber layer to reduce the influence of the self-doping of the absorber layer on the second step intrinsic epitaxy;

The second step of epitaxy: Before growing the intrinsic barrier layer, the cavity is gas-corroded to take away the remaining impurities with the gas; during epitaxy, the growth temperature is 980-1020°C, and the growth rate is controlled at 0.1-0.2μm/min. The intrinsic layer is grown in two stages; the first stage grows 0.5 μm, the self-doping of the cavity and the substrate edge is suppressed through the high-resistance layer, H2 blowing is added for 3 to 6 minutes in the middle of the two stages, and the low-resistance absorption layer and the intrinsic layer A high-resistance buffer layer is further formed between them; the second stage continues to grow the intrinsic layer until the final concentration is 10 ¹² -10 ¹³ cm ^-3 .

Beneficial effect:

The present invention prevents the manufacturing method of the silicon epitaxial wafer for impurity belt infrared detector, is to synthesize multiple self-doping suppression processes: suitable polishing wafer technical parameters; HCl polishing process and large-flow H2 purging to reduce N-type impurities to N-type The self-doping effect of the epitaxial layer; the two-step epitaxy method, after the low-resistance absorption layer is grown, the large-flow gas-corrosion cavity, and then the process method of growing the intrinsic barrier layer at low temperature and low speed; realizes high-concentration absorption layer and low-concentration intrinsic The epitaxial parameters with the widest possible transition zone of the intrinsic layer and the highest intrinsic resistivity meet the device parameter requirements of the BIB infrared detector.

Description of drawings

Figure 1 is a schematic diagram of the device used in the present invention.

Fig. 2 is a typical distribution diagram of vertical resistivity of silicon epitaxial layer grown by the present invention.

Fig. 3 is a longitudinal structure diagram of the present invention.

Fig. 4 is a process flow diagram of the present invention.

Detailed ways

Please refer to Fig. 1, the equipment used in the present invention is Italian PE-2061S normal pressure silicon epitaxial growth equipment, the high-purity graphite base is used as a high-frequency induction heating body, and the main carrier gas H2 has a purity of more than 99.9999%.

Equipment preparation includes,

Reactor cleaning: The quartz bell jar and the quartz parts used in the reaction chamber must be carefully cleaned before epitaxy. The substrate removes the deposition residue on the inner wall of the quartz bell jar and the quartz parts to reduce the self-doping of the cavity.

High-temperature treatment in the reaction chamber: Before epitaxial growth, the graphite base must be subjected to HCl high-temperature treatment to remove residual reactants adsorbed by the base and cavity, and deposit a layer of intrinsic polysilicon.

Please combine with Fig. 3 and shown in Fig. 4 again, the steps of the manufacturing method of this novel infrared detector BIB silicon epitaxial wafer include:

a. In order to meet the requirements of BIB device design, N-type <100> polished wafers heavily doped with As are selected, the resistivity is ≤0.004, the local flatness of 15cm in diameter is ≤3μm, and the substrate is not back-sealed; in order to reduce the influence of self-doping on the back , a silicon-encapsulated process was adopted to reduce the influence of substrate self-doping on the subsequent growth of the BIB high-resistance intrinsic layer.

b. HCl in-situ polishing process: In order to obtain a clean surface before epitaxy and ensure the lattice quality of the epitaxial layer, the polishing time and process temperature are appropriately increased. At 1160°C, select a suitable HCl flow rate of 3L/min, and the polishing time is 8mim; After polishing, high-temperature and high-flow H2 is purged for more than 10 minutes to remove residual N-type impurities in the reactor and reduce the self-doping effect during epitaxial growth.

c. The first step of epitaxy in the two-step epitaxy method: comprehensively considering factors such as self-doping, lattice quality, resistivity control, and growth efficiency, ultra-high-purity trichlorosilicon (TCS) is used, and the growth temperature is 1030 ° C to 1060 ° C. The growth rate is controlled at 0.7-1.1 μm/min, without dilution, the doping is set at 30-60 sccm/min, the concentration is 10 ^{17-10 18 cm} -3, and a low-resistance absorption layer is prepared on the heavily doped substrate; After the layer is prepared, the temperature is slowly lowered to room temperature, and at the same time, a large flow of H2 is purged, and a buffer layer with a relatively low concentration is formed on the surface of the BIB low-resistance absorption layer through a large-flow low-temperature annealing process to reduce the impact of self-doping of the absorption layer on the second step. The effect of levy extension.

d. The second step of the two-step epitaxy method: In order to reduce the influence of the high-concentration self-doping attached to the cavity on the BIB intrinsic layer during the epitaxy of the absorber layer, the cavity is first gas-corroded before the intrinsic barrier layer is elongated, and the remaining The impurities are taken away with the large flow of gas; during epitaxy, the growth temperature is 980-1020 °C, the growth rate is controlled at 0.1-0.2 μm/min, and the intrinsic layer is grown in two stages; the first stage grows 0.5 μm and passes through the high-resistance layer Inhibit the self-doping of the cavity and the edge of the substrate, add 3-6min high-flow H2 to blow off in the middle of the two stages, and further form a high-resistance buffer layer between the low-resistance absorption layer and the intrinsic layer; the second stage continues to grow the intrinsic layer , the final concentration should be 10 ¹² ～10 ¹³ cm-3.

The present invention "a method of manufacturing silicon epitaxial wafers for preventing impurities from carrying infrared detectors" is to integrate various self-doping suppression processes: suitable technical parameters of polished wafers; adopt HCl polishing process and large-flow H2 purge to reduce N-type The self-doping effect of impurities on the N-type epitaxial layer; a two-step epitaxy method is adopted, after the low-resistance absorption layer is grown, the high-flow gas-corrosion cavity is grown, and then the intrinsic barrier layer is grown at low temperature and low speed; the high-concentration absorption layer is realized And the epitaxial parameters of the low-concentration intrinsic layer transition region as wide as possible and the intrinsic resistivity as high as possible meet the device parameter requirements of the BIB infrared detector. As shown in Figure 2, it is a typical distribution diagram of the longitudinal resistivity of the silicon epitaxial layer grown by the present invention, and it can be verified by Fig. 2 that the above-mentioned beneficial effects can be realized by the technical solution of the present invention: the typical distribution of the longitudinal resistivity of the epitaxial layer and the substrate The bottom transition zone is steep, and the intrinsic barrier layer has a wider flat zone.

In addition, there are many specific implementation methods and approaches of the present invention, and the above are only preferred embodiments of the present invention. It should be pointed out that those skilled in the art can make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. All components that are not specified in this embodiment can be realized by existing technologies.

Claims (4)

1. A manufacturing method of a novel infrared detector BIB silicon epitaxial wafer is characterized by comprising the following steps:

the preparation of the device includes:

cleaning a reactor: quartz bell jar and quartz parts used in the reaction chamber must be carefully cleaned before epitaxy, deposition residues on the inner wall of the quartz bell jar and the quartz parts are thoroughly removed, and self-doping of the cavity is reduced;

high-temperature treatment of the reaction chamber: before epitaxial growth, the graphite base is required to be subjected to HCl high-temperature treatment, residual reactants absorbed by the base and the cavity are removed, and a layer of intrinsic polycrystalline silicon is deposited;

the manufacturing method comprises the following steps:

the substrate slice for the BIB infrared detector is an N-type 100 polished slice heavily doped with As, the size diameter of which is 15cm, the local flatness of which is less than or equal to 3 mu m, the resistivity of which is less than or equal to 0.004 omega-cm, and the substrate is not sealed; silicon is coated for 8min, so that the influence of substrate autodoping on the subsequent growth of the BIB high-resistance intrinsic layer is reduced;

selection of gas corrosion conditions: performing in-situ high-temperature polishing by HCl at the gas corrosion temperature of 1160 ℃, the HCl flow rate of 3L/min and the polishing time of 8 mim; purging with high-temperature high-flow H2 for more than 10min after polishing is finished to remove residual N-type impurities in the reactor and reduce the self-doping effect during epitaxial growth;

using a two-step epitaxy method, the low resistance absorber layer and the intrinsic layer are grown separately, i.e.,

the first step of epitaxy is growth of an N-type low-resistance absorption layer: trichlorosilane is adopted as a raw material, the growth temperature is 1030-1060 ℃, the growth rate is 0.7-1.1 mu m/min, dilution is not needed, the doping flow of the introduced phosphane is 30-60 sccm/min, and the corresponding epitaxial doping concentration is 10¹⁷～10¹⁸cm^-3Preparing a low-resistance absorption layer on the substrate; after the absorption layer is prepared, slowly cooling to room temperature, simultaneously introducing H2 for blowing, and forming a buffer layer with the concentration lower than that of the low-resistance absorption layer on the surface of the low-resistance absorption layer so as to reduce the influence of the self-doping of the absorption layer on the intrinsic epitaxy in the second step;

and a second step of epitaxy: before growing the intrinsic barrier layer, the cavity is corroded by gas, and residual impurities are taken away along with the gas; external time delay, wherein the growth temperature is 980-1020 ℃, the growth rate is controlled to be 0.1-0.2 mu m/min, the intrinsic layer grows in two sections without doping, the first section grows 0.5 mu m, the self-doping of the cavity and the edge of the substrate is inhibited through the high-resistance layer, H2 for 3-6 min is added between the two sections for blowing off, and a high-resistance buffer layer is further formed between the low-resistance absorption layer and the intrinsic layer; the second stage continues to grow the intrinsic layer to a final concentration of 10¹²～10¹³cm^-3。

2. A silicon epitaxial manufacturing method according to claim 1, characterized in that: epitaxial conditions for epitaxial growth of the first layer: silicon coating is carried out for 8min, the gas corrosion temperature is 1160 ℃, the HCl flow is 3L/min, the polishing time is 8min, the epitaxial growth temperature is 1030-1060 ℃, the growth rate is controlled to be 0.7-1.1 mu m/min, dilution is not needed, and the doping flow is 30-60 sccm/min.

3. A silicon epitaxial manufacturing method according to claim 1, characterized in that: epitaxial conditions for epitaxial growth of the second layer: and (3) etching the cavity with gas before epitaxy to take away residual impurities along with the gas with large flow, wherein the temperature of epitaxy growth is 980-1020 ℃, the growth rate is controlled at 0.1-0.2 mu m/min, the intrinsic layer grows in two sections without doping, and the middle is blown off by adding 3-6 min of H2 with large flow.

4. A silicon epitaxial manufacturing process according to claim 1 or 2 or 3, characterized in that: by controlling the self-doping, the transition region between the absorption layer and the substrate is steep, and the intrinsic barrier layer has a wide flat region.