CN108766954B - Heterogeneous substrate integrated structure and preparation method - Google Patents
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- CN108766954B CN108766954B CN201810583888.4A CN201810583888A CN108766954B CN 108766954 B CN108766954 B CN 108766954B CN 201810583888 A CN201810583888 A CN 201810583888A CN 108766954 B CN108766954 B CN 108766954B
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- 239000000758 substrate Substances 0.000 title claims abstract description 266
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000010410 layer Substances 0.000 claims description 65
- 239000011521 glass Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 19
- 239000002313 adhesive film Substances 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 15
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 238000005507 spraying Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 43
- 239000000919 ceramic Substances 0.000 description 28
- 230000010354 integration Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 125000002524 organometallic group Chemical group 0.000 description 6
- 238000005452 bending Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 125000005842 heteroatom Chemical group 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000008707 rearrangement Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 238000012954 risk control Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optical Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a heterogeneous substrate integrated structure and a preparation method thereof, wherein the heterogeneous substrate integrated structure comprises an organic metal wiring layer and a plurality of heterogeneous substrates, the organic metal wiring layer is connected with bonding pads of the heterogeneous substrates needing to be interconnected, the electric connection between the heterogeneous substrates is realized through the organic metal wiring layer, the organic metal wiring layer completely covers the surface of each heterogeneous substrate needing to be directly interconnected and becomes a part of the metal wiring layer of each heterogeneous substrate, or the organic metal wiring layer is lapped on the surface of two adjacent heterogeneous substrates needing to be directly interconnected. The invention solves the space interconnection problem among different substrates, gives full play to the advantages of the substrates to achieve the optimal system performance and has good economic prospect.
Description
Technical Field
The invention belongs to the field of advanced electronic packaging, relates to a packaging substrate used in semiconductor electronic microsystem and component hybrid integrated packaging, and particularly relates to a heterogeneous substrate integrated structure and a preparation method thereof.
Background
Under the premise that the portable intelligent system continuously increases the requirements on the functions and the performance of electronic products, the size and the weight of the electronic products are required to be continuously reduced, and the functions of the whole electronic system are generally required to be realized in a tiny space, namely, a micro electronic system is realized, which is referred to as a micro system. Given the complexity of microsystems and the variety of devices involved, different forms of chips, devices and sub-assemblies may be incorporated into microsystems, either bare chips, plastic packages, ceramic packages or metal-encapsulated; the microsystems may contain chips, devices and sub-assemblies of different functions and materials, which may be MEMS, digital, analog, rf microwave, biological or other sensing; and meanwhile, a large number of passive elements such as resistors, capacitors and inductors and passive networks are required to be accommodated. Due to the limitations of the materials and the corresponding substrate preparation processes, the substrate made of a single material or a single process is difficult to meet the requirements of the complex microsystem integration on the substrate. Generally, a plurality of substrates are selected according to the characteristics of various substrates to jointly complete the integrated package of the complex microsystem, so as to achieve the optimal performance of the microsystem, and the interconnection between the substrates becomes a problem to be solved urgently. The vertical stacking of the substrates is formed by welding and interconnecting the bumps or the solder balls among the substrates, so that the method is very effective under the conditions of large interconnection quantity among the substrates, high interconnection speed and strict delay requirement, but has strict requirement on the matching between the sizes and the CTEs of the substrates and poor flexibility.
Disclosure of Invention
The invention aims to provide a heterogeneous substrate integrated structure and a preparation method thereof, which are used for overcoming the problems in the prior art, solving the space interconnection problem among different heterogeneous substrates, and giving full play to the advantages of the substrates so as to achieve the optimal system performance and have good economic prospect.
In order to achieve the purpose, the invention adopts the following technical scheme:
a heterogeneous substrate integrated structure comprises an organic metal wiring layer and a plurality of heterogeneous substrates, wherein the organic metal wiring layer is connected with a bonding pad which needs to be interconnected of each heterogeneous substrate, the electric connection between each heterogeneous substrate is realized through the organic metal wiring layer, the organic metal wiring layer completely covers the surface, needing to be directly interconnected, of each heterogeneous substrate and becomes a part of the metal wiring layer of each heterogeneous substrate, or the organic metal wiring layer is lapped on the surface, needing to be directly interconnected, of two adjacent heterogeneous substrates;
when the organic metal wiring layer completely covers the surface of each heterogeneous substrate needing direct interconnection, the organic metal wiring layer can be bent at the interconnection position of each heterogeneous substrate, and chips or devices on each heterogeneous substrate are assembled on the organic metal wiring layer;
when the organic metal wiring layer is lapped on the surface of two adjacent heterogeneous substrates to be directly interconnected, the chips or devices on each heterogeneous substrate are micro-assembled on the metal wiring layer on the surface of each heterogeneous substrate.
Further, the plurality of heterogeneous substrates are all organic substrates, or the plurality of heterogeneous substrates are all inorganic substrates, or the plurality of heterogeneous substrates are both organic substrates and inorganic substrates;
the substrate materials of the plurality of heterogeneous substrates are different, or the substrate materials of the plurality of heterogeneous substrates are partially consistent, or the substrate materials of the plurality of heterogeneous substrates are completely consistent.
Further, the thicknesses of the plurality of heterogeneous substrates are the same or different;
the plurality of heterogeneous substrates are in regular shapes or irregular shapes.
Further, the heterogeneous substrate comprises a silicon substrate, a ceramic substrate and a glass substrate, wherein the silicon substrate is a silicon substrate without TSV or a silicon substrate with TSV, and the glass substrate is a glass substrate without TGV or a glass substrate with TGV.
Furthermore, the surfaces of the silicon substrate and the glass substrate are provided with micro-bumps, and the surfaces or the inner parts of the silicon substrate and the glass substrate are provided with optical waveguides.
Further, the through silicon via TSV conduction material in the silicon substrate with the TSV and the through glass via TGV conduction material in the glass substrate with the TGV are metal materials, semiconductor materials or modified organic materials.
A preparation method of a heterogeneous substrate integrated structure comprises the following steps:
the method comprises the following steps: taking a temporary positioning carrier plate, and attaching a double-sided adhesive film on one surface of the temporary positioning carrier plate, wherein two surfaces of the temporary positioning carrier plate are flat surfaces;
step two: accurately positioning a plurality of heterogeneous substrates according to the pre-designed relative positions of the heterogeneous substrates by using the surface-facing double-sided adhesive films of the heterogeneous substrates which need to be directly interconnected to complete the specific arrangement structure of each heterogeneous substrate;
step three: spraying temporary bonding glue on the surface of each special arrangement structure of the heterogeneous substrates;
step four: aligning and bonding a carrier plate and the structure formed in the third step, wherein corresponding pits are prepared on one surface of the carrier plate facing to each heterogeneous substrate according to the thickness of each heterogeneous substrate, so that good bonding is formed between the carrier plate and the surface of each heterogeneous substrate far away from the temporary positioning carrier plate; and the other surface of the carrier plate is a flat surface;
step five: removing the temporary positioning carrier plate and the double-sided adhesive film to expose the surfaces of the heterogeneous substrates which need to be directly interconnected on the same plane;
step six: coating an organic medium adhesive layer on the plane exposed in the step five, further filling the exposed unevenness defect on the plane, then opening a window on the organic medium adhesive layer to expose the bonding pads of the heterogeneous substrates needing interconnection, sputtering or evaporating the metal layer after the organic medium adhesive layer is solidified, preparing a metal wiring layer by adopting an electroplating method, and forming an organic metal wiring layer;
step seven: adhering the surface of the organic metal wiring layer on the organic film, and flattening the organic film;
step eight: bonding the support plate;
step nine: and removing the organic film to form the heterogeneous substrate integrated structure.
Further, the double-sided adhesive film is made of a photosensitive material or a thermosensitive material.
Further, the temporary bonding glue is a heat-sensitive bonding material, a light-sensitive bonding material, a material dissolved in a chemical solution, or a material reacted with the chemical solution.
Furthermore, the material of the carrier plate is glass or silicon.
Compared with the prior art, the invention has the following beneficial technical effects:
the heterogeneous substrate integrated structure provided by the invention realizes the interconnection and the electrical interconnection between rigid heterogeneous substrates through the organic flexible material to form a rigid-flexible mixed substrate, and can realize bending, laminating and folding and rolling by virtue of the flexibility of the organic flexible connecting part so as to adapt to space requirements. The heterogeneous substrate integrated structure provided by the invention solves the spatial interconnection problem among heterogeneous substrates, fully exerts the advantages of the substrates to achieve the optimal system performance, and has good economic prospect.
The preparation method of the heterogeneous substrate integrated structure adopts a wafer-level or Panel-level process, realizes reconstruction among heterogeneous substrates by rearrangement and multilayer organic rewiring of various substrates on the carrier plate, and performs spatial rearrangement on the substrates according to the requirement of micro-system integration to form effective electrical interconnection among the substrates, thereby solving the problem of spatial interconnection among the heterogeneous substrates, fully exerting the advantages of the substrates to achieve the optimal system performance and having good economic prospect.
Drawings
FIG. 1 is a schematic cross-sectional view of a silicon substrate;
FIG. 2 is a schematic cross-sectional view of a ceramic substrate;
FIG. 3 is a schematic cross-sectional view of a glass substrate;
FIG. 4 is a schematic view of a carrier plate temporarily positioned with a double-sided adhesive film attached to one surface thereof;
FIG. 5 is a schematic structural diagram illustrating a process of bonding different heterogeneous substrates to a temporary positioning carrier via a double-sided adhesive film;
FIG. 6 is a schematic structural view after spraying of the temporary bonding paste;
FIG. 7 is a schematic structural diagram of a bonded carrier and the structure of FIG. 6;
FIG. 8 is a schematic structural view after the temporary positioning carrier and the double-sided adhesive film are removed;
FIG. 9 is a schematic diagram of a organometallic wiring layer formed over the structure of FIG. 8;
FIG. 10 is a schematic view of a surface of an organometallic wiring layer being pasted on an organic film;
FIG. 11 is a schematic structural view of a carrier after being unbonded;
FIG. 12 is a structural diagram of a hetero-substrate integrated structure A;
FIG. 13 is a schematic structural diagram of a hetero-substrate integrated structure A after bending;
FIG. 14 is a structural diagram of a hetero-substrate integrated structure B;
FIG. 15 is a schematic structural diagram of a hetero-substrate integrated structure C;
fig. 16 is a structural diagram of the hetero-substrate integrated structure C after bending.
Wherein, 1: a silicon substrate without TSV; 1': a silicon substrate with TSV; 12: a silicon substrate metal wiring layer; 13: a silicon wafer material; 14: through Silicon Vias (TSV); 2: a ceramic substrate; 21: a via hole between the metal wiring layers; 22: a ceramic substrate metal wiring layer; 23: a ceramic dielectric; 3: glass substrate without TGV; 3': a glass substrate with TGV; 32: a glass substrate metal wiring layer; 33: a glass substrate; 34: a glass via TGV; 4: adhering the film on the two sides; 5: temporarily positioning a carrier plate; 6: a temporary bonding glue; 7: a carrier plate; 8: an organometallic wiring layer; 9: an organic film; 10: a chip or device; 100: a hetero-substrate integrated structure A; 100 a: a hetero-substrate integrated structure B; 100': and D, a heterogeneous substrate integrated structure C.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
the invention provides a heterogeneous substrate integrated structure, which can spatially rearrange substrates such as a ceramic substrate, a silicon substrate, a glass substrate and the like according to the requirement of microsystem integration and form effective electric interconnection among the substrates. It is a feature of the present invention that the substrates to be interconnected are not limited to the same material, the same thickness, or similar structures. The individual substrates being interconnected may be silicon, glass, alumina ceramic, aluminum nitride ceramic, silicon carbide, aluminum silicon, but are not so limited. The individual substrates being interconnected may be rigid substrates or may be both rigid and flexible substrates. The various substrates being interconnected may be of different thicknesses. The interconnected substrates can be independently designed, independently optimized, independently processed by tape-out, independently tested, and rearranged in relative positions according to system design requirements after the test is qualified, so that the system has good risk control and quality control capabilities.
The heterogeneous substrate integrated preparation method provided by the invention adopts a wafer-level or Panel-level process, and realizes reconstruction among heterogeneous substrates through rearrangement and multilayer organic rewiring of various substrates on the carrier plate. The heterogeneous substrate integrated structure provided by the invention realizes the interconnection and the electrical interconnection between rigid heterogeneous substrates through the organic flexible material to form a rigid-flexible mixed substrate, and can realize bending, stacking and rolling by virtue of the flexibility of the organic flexible connecting part so as to adapt to space requirements. The heterogeneous substrate integrated structure and the preparation method provided by the invention solve the problem of space interconnection among different heterogeneous substrates, give full play to the advantages of the substrates, achieve the optimal system performance and have good economic prospects.
Referring to fig. 1, the silicon substrate at least includes a silicon wafer material 13 and a silicon substrate metal wiring layer 12 located on one surface of the silicon wafer material 13, and the silicon substrate may further include a conductive Through hole (TSV), a micro bump and an optical waveguide penetrating Through the silicon wafer material, the silicon substrate may have a metal wiring layer on only one surface or both surfaces, the metal wiring layer is composed of at least one metal conductive layer and one dielectric insulating layer, or a plurality of metal conductive layers and a plurality of dielectric insulating layers are alternately stacked. The dielectric insulating layer material of the metal wiring layer may be an inorganic dielectric material (such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc.), an organic dielectric material (such as, but not limited to, PI, BCB, PBO, etc.), or a composite structure dielectric composed of an inorganic dielectric and an organic dielectric.
Referring to fig. 2, the ceramic substrate 2 may be LTCC, HTCC, thick film ceramic, and includes a ceramic dielectric 23 and at least one ceramic substrate metal wiring layer 22 on the surface of the ceramic substrate, and may further include multiple metal wirings, via holes 21 between the metal wiring layers, micro bumps, embedded passive resistors, capacitors, inductors, and the like.
Referring to fig. 3, the glass substrate at least includes a glass substrate 33 and a glass substrate metal wiring layer 32 on one surface of the glass substrate 33, the glass substrate may further include a conductive via (i.e., TGV), a micro bump and an optical waveguide penetrating Through the glass substrate, the glass substrate may have a metal wiring layer on only one surface or both surfaces, the metal wiring layer is composed of at least one metal conductive layer and one dielectric insulating layer, or may be formed by alternately stacking a plurality of metal conductive layers and a plurality of dielectric insulating layers. The dielectric insulating layer material of the metal wiring layer may be an inorganic dielectric material (such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc.), an organic dielectric material (such as, but not limited to, PI, BCB, PBO, etc.), or a composite structure dielectric composed of an inorganic dielectric and an organic dielectric.
Fig. 4 to 12 show a process flow of a method for integrally manufacturing a heterogeneous substrate such as a silicon substrate, a ceramic substrate, a glass substrate, and the like according to an embodiment.
Wherein a double-sided adhesive film 4 is attached to one surface of the temporary positioning carrier 5 in fig. 4. The double-sided adhesive film 4 is made of a photosensitive or thermosensitive material, and both surfaces of the temporary positioning carrier 5 are flat surfaces.
In fig. 5, the two-sided adhesive film 4 facing the different heterogeneous substrates to be directly connected is used to accurately position the heterogeneous substrates according to the pre-designed relative positions of the heterogeneous substrates, thereby completing the specific arrangement structure of the heterogeneous substrates. Is positioned to be less than exactly one-half of each foreign substrate minimum interconnect pad, and is preferably positioned to be less than exactly one-fourth of each foreign substrate minimum interconnect pad. The invention has no limit on the material of each substrate participating in integration, the process of each substrate and the thickness of each substrate. The respective substrates participating in the integration may be inorganic substrates, organic substrates, or both inorganic and organic substrates. Each substrate participating in the integration may be a rigid substrate, or may be both a rigid substrate and a flexible substrate. The respective substrates involved in the integration may be silicon, glass, alumina ceramic, aluminum nitride ceramic, LTCC, HTCC, silicon carbide, aluminum silicon, but are not limited thereto. The respective substrate materials participating in the integration may be different, may be partially the same, or may be the same substrate material.
FIG. 6: and spraying temporary bonding glue 6 on the surface of each substrate arrangement structure in the step 5. The spraying method is selected because it can form good temporary bonding glue coverage not only on the surface (plane) of each substrate, but also on the side surface of each substrate. The application of the temporary bonding paste on the exposed surface of each substrate can be accomplished by tilting the figure 5 or tilting the nozzle in different directions during the spraying process. And the coverage rate of the temporary bonding glue on the side wall can be further improved by combining multiple spraying.
FIG. 7: the carrier plate 7 is bonded in alignment with the completed structure of fig. 6 described above. Corresponding pits are prepared on one surface, facing each substrate, of the carrier plate 7 according to the thickness of each substrate, so that the thickness difference among the substrates is compensated, and good bonding can be formed between the carrier plate 7 and the surface, far away from the temporary positioning carrier plate 5, of each substrate; the other side of the carrier plate 7 is flat. The size of each recess on the carrier plate 7 is slightly larger than the size of each corresponding substrate. The side walls of the pits on the carrier plate 7 can be vertical or inclined, so that the corresponding substrates can smoothly enter the pits; the bottom of each recess in the carrier plate 7 is flat. Preferred materials for the carrier plate 7 are glass and silicon. When the selected temporary bonding adhesive is a photosensitive material and the light with the characteristic wavelength is required to be subjected to debonding, the material of the carrier plate 7 is a material transparent to the light wave with the characteristic wavelength.
Then, the temporary positioning carrier 5 and the double-sided adhesive film 4 are removed as shown in fig. 8. Up to this point, the faces of the respective substrates that need direct interconnection are exposed on the same plane.
And coating an organic medium adhesive layer on the exposed plane, further filling the defects such as slits on the exposed plane, and opening windows in the organic medium adhesive layer to expose the bonding pads of each substrate required to be interconnected. After the organic medium glue layer is solidified, a metal layer, such as Ti/Cu, TiW/Cu, but not limited to, is sputtered or evaporated. And preparing a metal wiring layer by adopting an electroplating method. If multiple layers of wiring are required, the processes of organic dielectric layer coating, photolithographic development, curing, sputtering or evaporating a metal layer, electroplating, forming metal wiring, etc. may be repeated to finally form the organometallic wiring layer 8, as shown in fig. 9. The organic dielectric glue layer includes PI, BCB, PBO, SU8, etc., but is not limited thereto. The surface of the organic metal wiring layer 8 can be prepared with a micro-bump array for flip-chip bonding, and can also be prepared with a bump array for the external leads of the finally formed hetero-substrate integrated structure a 100.
And (3) pasting the bonding sheet of the organic metal wiring layer 8, namely pasting the surface of the organic metal wiring layer 8 on the organic film 9, and flattening the organic film 9 on the tension ring. As shown in fig. 10.
After the carrier plate 7 is debonded, as shown in fig. 11, the debonding manner of the carrier plate 7 is related to the material property of the temporary bonding glue 6, when the adopted temporary bonding glue 6 is a thermosensitive bonding material, the carrier plate 7 needs to be heated to the softening temperature of the temporary bonding glue 6 when debonding, and then mechanical force is applied to remove the carrier plate 7; when the adopted temporary bonding glue 6 is a photosensitive bonding material, a certain dose of light wave with a specific wavelength (such as ultraviolet light) is needed for irradiation when the carrier plate 7 is bonded, and then mechanical force is applied to remove the carrier plate 7, wherein the carrier plate 7 is made of a material transparent to the specific wavelength, such as glass, resin and the like; when the adopted temporary bonding glue 6 is dissolved in a certain chemical solution or reacts with a certain chemical solution, the bonding strength of the carrier plate 7 is weakened to be capable of being removed without damage, and the carrier plate 7 needs to be soaked in the chemical solution when being debonded.
After removing the organic film 9, heterogeneous integration of the silicon substrate 1 without TSV, the ceramic substrate 2, and the glass substrate 3 without TGV is completed as shown in fig. 12. The electrical connection between the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV is achieved by an organometallic wiring layer 8. Since the organic metal wiring layer 8 is flexibly bendable, the hetero substrate integrated structure a100 formed after hetero integration of the silicon substrate 1 without TSV, the ceramic substrate 2, and the glass substrate 3 without TGV is bendable at the hetero substrate interconnection as shown in fig. 13. The micro-assembly form of the chip on the hetero-substrate integrated structure a100 may be wire bonding, flip-chip bonding, surface mount soldering, or surface mount bonding. In the micro-assembly process, each heterogeneous substrate in the heterogeneous substrate integrated structure A100 is in a horizontal state, and after the micro-assembly of the chip is completed, the heterogeneous substrate integrated structure A100 can be bent as required. The chips and devices micro-assembled on the hetero-substrate integrated structure a100 may be bare chips or packaged chips, devices and subassemblies.
Fig. 14 shows another hetero-substrate integrated structure B100a of a silicon substrate, a ceramic substrate, and a glass substrate. Unlike the embodiment in which the organic metal wiring layer 8 covers the entire surface of the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV and becomes a part of the metal wiring layer of each hetero-substrate of the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV, chips and devices on each hetero-substrate of the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV are micro-assembled on the organic metal wiring layer 8, the embodiment in which the organic metal wiring layer 8 covers only a part of the edge of each hetero-substrate of the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV, the organic metal wiring layer 8 serves only as an interconnection part between the respective hetero-substrates, chips and devices on each hetero-substrate of the silicon substrate 1 without TSV, the ceramic substrate 2 and the glass substrate 3 without TGV are micro-assembled on the metal wiring layer on the surface of each hetero-substrate, independent of the organometallic wiring layer 8.
Fig. 15 is a hetero substrate integrated structure C100 ' of the silicon substrate 1 ' with TSV, the ceramic substrate 2, and the glass substrate 3 ' with TGV. The through-silicon via TSV14 conductive material in the silicon substrate 1' with TSV and the through-glass via TGV34 conductive material in the glass substrate may be metal materials such as copper and tungsten, semiconductor materials such as doped polysilicon and doped monocrystalline silicon, or modified organic materials such as carbon nanotubes and conductive resin. In this case, metal wires are formed on both surfaces of the silicon substrate 1 'with TSV, the ceramic substrate 2 and the glass substrate 3' with TGV, and chips and devices can be assembled on both surfaces of the silicon substrate 1 'with TSV, the ceramic substrate 2 and the glass substrate 3' with TGV.
Fig. 16 shows that after the chip or device 10 is assembled on the hetero-substrate integrated structure C100', it can be folded and stacked according to the application requirements to form a three-dimensional integration of an electronic system to fit the application space.
The heterogeneous substrate integrated structure and the preparation method disclosed by the invention are not only suitable for rigid-flexible hybrid integration among heterogeneous substrates, but also suitable for rigid-flexible hybrid integration among homogeneous substrates.
The heterogeneous substrates such as the silicon substrate, the ceramic substrate, and the glass substrate may have any shape, and may have a regular shape, such as a rectangle, a square, a polygon, a circle, or an irregular shape. The heterogeneous substrate may be a sheet material such as a metal sheet, a glass sheet, a resin sheet, etc., but is not limited thereto.
Claims (4)
1. A preparation method of a heterogeneous substrate integrated structure is characterized by comprising the following steps:
the method comprises the following steps: taking a temporary positioning carrier plate (5), and attaching a double-sided adhesive film (4) on one surface of the temporary positioning carrier plate (5), wherein two surfaces of the temporary positioning carrier plate (5) are flat surfaces;
step two: accurately positioning a plurality of heterogeneous substrates according to the pre-designed relative positions of the heterogeneous substrates by using the surface-facing double-sided adhesive films (4) of the heterogeneous substrates which need to be directly interconnected to complete the specific arrangement structure of each heterogeneous substrate;
step three: spraying temporary bonding glue (6) on the surface of each heterogeneous substrate specific arrangement structure;
step four: aligning and bonding the carrier plate (7) and the structure formed in the third step, wherein corresponding pits are prepared on one surface, facing each heterogeneous substrate, of the carrier plate (7) according to the thickness of each heterogeneous substrate, so that good bonding is formed between the carrier plate (7) and the surface, far away from the temporary positioning carrier plate (5), of each heterogeneous substrate; and the other surface of the carrier plate (7) is a flat surface;
step five: removing the temporary positioning carrier plate (5) and the double-sided adhesive film (4) to expose the surfaces of the heterogeneous substrates which need to be directly interconnected on the same plane;
step six: coating an organic medium adhesive layer on the plane exposed in the step five, further filling the exposed unevenness defect on the plane, then opening a window on the organic medium adhesive layer to expose the bonding pads of the heterogeneous substrates needing interconnection, sputtering or evaporating the metal layer after the organic medium adhesive layer is solidified, preparing a metal wiring layer by adopting an electroplating method, and forming an organic metal wiring layer (8);
step seven: adhering the surface of the organic metal wiring layer (8) to the organic film (9), and flattening the organic film (9);
step eight: bonding the carrier plate (7) off;
step nine: and removing the organic film (9) to form a heterogeneous substrate integrated structure.
2. A method for fabricating a hetero-substrate integrated structure according to claim 1, wherein the double-sided adhesive film (4) is a photosensitive material or a thermosensitive material.
3. A method for fabricating a hetero-substrate integrated structure according to claim 1, wherein the temporary bonding glue (6) is a heat sensitive bonding material, a light sensitive bonding material, a material dissolved in a chemical solution or a material reacting with a chemical solution.
4. The method according to claim 1, wherein the carrier (7) is made of glass or silicon.
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