CN108766953B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN108766953B CN108766953B CN201810552229.4A CN201810552229A CN108766953B CN 108766953 B CN108766953 B CN 108766953B CN 201810552229 A CN201810552229 A CN 201810552229A CN 108766953 B CN108766953 B CN 108766953B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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Abstract
A semiconductor device and method of forming the same, the semiconductor device comprising: the device comprises a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure; a plurality of pads electrically connected with the metal interconnect structure; the surface of the pixel wafer is bonded with the front surface of the device wafer; a plurality of conductive plugs extending through the pixel wafer, wherein a portion of the plurality of conductive plugs is connected to the pad, and another portion of the plurality of conductive plugs is separated from the pad by a dielectric. The scheme of the invention can reduce the switching noise and reuse the conductive plug and the gasket as two layers of metal in the MIM capacitor structure, thereby being beneficial to improving the space utilization rate and reducing the production cost.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device and a method for forming the same.
Background
In the conventional chip application, when the digital circuit output signal is subjected to level conversion, a large impulse current, also called switching noise, is easily generated.
In one existing solution, in order to reduce switching noise, a decoupling capacitor is provided to store current when the inrush current is too large, thereby reducing the effect of switching noise on the device.
However, the additional addition of decoupling capacitors in the existing circuit not only occupies chip space, but also increases production cost.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor device and a forming method thereof, which can reduce switching noise and reuse a conductive plug and a gasket as two layers of metal in an MIM capacitor structure, thereby being beneficial to improving the space utilization rate and reducing the production cost.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor device, including: the device comprises a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure; a plurality of pads electrically connected with the metal interconnect structure; the surface of the pixel wafer is bonded with the front surface of the device wafer; a plurality of conductive plugs extending through the pixel wafer, wherein a portion of the plurality of conductive plugs is connected to the pad, and another portion of the plurality of conductive plugs is separated from the pad by a dielectric.
Optionally, the material of the dielectric is selected from: silicon oxide and silicon nitride.
Optionally, the semiconductor device further includes: the dielectric layer is positioned between the pixel wafer and the front surface of the device wafer and is used for bonding the pixel wafer and the device wafer; wherein the dielectric layer is made of a material different from that of the dielectric.
Optionally, a portion of the plurality of conductive plugs comprises: a power conductive patch adapted for connection to a power line, another portion of the plurality of conductive patches being located within a predetermined range around the power conductive patch.
Optionally, the number of the other part of the plurality of conductive plugs accounts for 5% to 50% of the total number of the plurality of conductive plugs.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure; forming a plurality of pads electrically connected with the metal interconnect structure; forming a dielectric on a portion of a surface of a liner; providing a pixel wafer, and bonding the pixel wafer with the front surface of the device wafer; and forming a plurality of conductive plugs, wherein the plurality of conductive plugs penetrate through the pixel wafer, one part of the plurality of conductive plugs is connected with the liner, and the other part of the plurality of conductive plugs is separated from the liner by the dielectric.
Optionally, the material of the dielectric is selected from: silicon oxide and silicon nitride.
Optionally, the front surfaces of the pixel wafer and the device wafer are bonded through a dielectric layer; wherein the dielectric layer is made of a material different from that of the dielectric.
Optionally, a portion of the plurality of conductive plugs comprises: a power conductive patch adapted for connection to a power line, another portion of the plurality of conductive patches being located within a predetermined range around the power conductive patch.
Optionally, the number of the other part of the plurality of conductive plugs accounts for 5% to 50% of the total number of the plurality of conductive plugs.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, a plurality of pads are arranged to be electrically connected with the Metal interconnection structure, one part of a plurality of conductive plugs is connected with the pads, another part of the plurality of conductive plugs is separated from the pads by a dielectric, one part of the pads can be connected with the conductive plugs without influencing the circuit function, and another part of the pads, the dielectric and the conductive plugs form a Metal-dielectric-Metal (MIM) capacitor structure to serve as a decoupling capacitor and reduce the switching noise. Compared with the prior art, due to the fact that the switching noise is larger due to the lack of the decoupling capacitor, or due to the fact that the additional increase of the decoupling capacitor occupies the chip space, by adopting the scheme of the embodiment of the invention, the switching noise can be reduced, and meanwhile, the conductive plug and the gasket are reused as two layers of metal in the MIM capacitor structure, so that the space utilization rate is improved, and the production cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device according to the prior art;
FIG. 2 is a flow chart of a method of forming a semiconductor device in an embodiment of the present invention;
fig. 3 to 9 are schematic cross-sectional views of devices corresponding to respective steps in a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 10 is a schematic cross-sectional view of another semiconductor device in an embodiment of the present invention.
Detailed Description
In the conventional chip application, when the digital circuit output signal is subjected to level conversion, a large impulse current, also called switching noise, is easily generated.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device in the prior art.
The semiconductor device may include a device wafer 100, a pixel wafer 120, and a dielectric layer 130.
The dielectric layer 130 may be located between the pixel wafer 120 and the front surface of the device wafer 100, and is used for bonding the pixel wafer 120 and the device wafer 100.
Specifically, the device wafer 100 may include a semiconductor substrate 101, and the metal interconnection structure 102 is located on a surface of a front side of the semiconductor substrate 101.
The semiconductor device may further include a plurality of pads 104, the plurality of pads 104 being electrically connected with the metal interconnect structure 102.
In a specific implementation, the plurality of pads 104 may be formed by deposition on the surface of the metal interconnect structure 102.
The semiconductor device may further include a plurality of conductive plugs 122 extending through the pixel wafer 120, and the plurality of conductive plugs 122 are connected to the pad 104 to conduct current.
The inventor of the present invention has found that, in the specific application of the prior art, when the digital circuit output signal is subjected to level conversion, a large impulse current, also called switching noise, is easily generated. With the continuous improvement of the requirements on the performance of the CIS device, the noise control requirements are higher and higher, and in order to reduce the switching noise, a decoupling capacitor is additionally added in the existing circuit to store the current when the impact current is too large, so that the influence of the switching noise on the device is reduced, the occupation of the chip space is easily increased, and the production cost is increased.
In the embodiment of the invention, a plurality of gaskets are arranged to be electrically connected with the metal interconnection structure, one part of a plurality of conductive plugs is connected with the gaskets, the other part of the plurality of conductive plugs is separated from the gaskets by a dielectric, one part of the gaskets can be connected with the conductive plugs without influencing the circuit function, and the other part of the gaskets, the dielectric and the conductive plugs form an MIM capacitor structure to be used as a decoupling capacitor to reduce the switching noise. Compared with the prior art, due to the fact that the switching noise is larger due to the lack of the decoupling capacitor, or due to the fact that the additional increase of the decoupling capacitor occupies the chip space, by adopting the scheme of the embodiment of the invention, the switching noise can be reduced, and meanwhile, the conductive plug and the gasket are reused as two layers of metal in the MIM capacitor structure, so that the space utilization rate is improved, and the production cost is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a flow chart of a method for forming a semiconductor device in an embodiment of the invention. The method of forming the semiconductor device may include steps S21 to S25:
step S21: providing a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure;
step S22: forming a plurality of pads electrically connected with the metal interconnect structure;
step S23: forming a dielectric layer, the dielectric layer being located on a surface of a portion of the liner;
step S24: providing a pixel wafer, and bonding the pixel wafer with the front surface of the device wafer;
step S25: and forming a plurality of conductive plugs, wherein the plurality of conductive plugs penetrate through the pixel wafer, one part of the plurality of conductive plugs is connected with the liner, and the other part of the plurality of conductive plugs is separated from the liner by the dielectric.
The above steps will be described with reference to fig. 3 to 9.
Fig. 3 to 9 are schematic cross-sectional views of devices corresponding to steps in a method for forming a semiconductor device according to an embodiment of the invention.
Referring to fig. 3, a device wafer 200 is provided, the front side of the device wafer 200 having a metal interconnect structure 202, a plurality of pads 204 are formed, and the plurality of pads 204 are electrically connected to the metal interconnect structure 202.
In an implementation, the device wafer 200 may include a semiconductor substrate 201, and the metal interconnect structure 202 may be located on a surface of a front side of the semiconductor substrate 201.
Specifically, the semiconductor substrate 201 may be a silicon substrate, or the material of the semiconductor substrate 201 may also be a material suitably applied to an image sensor, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate 201 may also be a silicon substrate on the surface of an insulator or a germanium substrate on the surface of an insulator, or a substrate on which an epitaxial layer (Epi layer) is grown. Preferably, the semiconductor substrate 201 may be a lightly doped semiconductor substrate, and the doping type is opposite to the drain region. Specifically, Deep Well doping (Deep Well Implant) may be achieved by ion implantation into the semiconductor substrate 201.
Further, the metal interconnection structure 202 may include not only metal lines of each layer, but also an interlayer dielectric between the metal lines of each layer.
The process of forming the plurality of spacers 204 may include: forming a pad layer covering the metal interconnection structure; forming a patterned liner mask layer on the surface of the liner layer; and etching the liner layer by taking the liner mask layer as a mask to obtain the liner 204.
In a specific implementation, the material of the liner may be metallic aluminum (Al) to form an aluminum liner (Al Pad).
Referring to fig. 4, a dielectric layer 205 is formed, the dielectric layer 205 covering the plurality of pads 204 and the metal interconnect structure 202.
In particular, the material of the dielectric layer 205 may be selected from: silicon oxide and silicon nitride, wherein the silicon oxide may be, for example, SiO2The silicon nitride may be, for example, Si3N4。
In a specific implementation manner of the embodiment of the present invention, silicon nitride may be used as the dielectric layer 205, and compared with silicon oxide, the compactness of silicon nitride is higher, which is beneficial to improving the capacitance performance of MIM, thereby improving the device quality.
Specifically, the dielectric Layer 205 may be formed by In-situ Steam Generation (ISSG), Atomic Layer Deposition (ALD), Fluid Chemical Vapor Deposition (FCVD), plasma Chemical Vapor Deposition (pecvd), sub-atmospheric cvd, low pressure cvd, or fluid cvd.
In the embodiment of the present invention, preferably, the dielectric layer 205 may be formed by using an atomic layer deposition process. Since the ald process is typically used to perform atomic scale controlled film growth, the uniformity of the dielectric layer 205 is better controlled, and since the ald process is deposited as a single atomic film layer by layer to form a thin film, the ald process has a stronger gap-filling capability than other deposition processes.
The dielectric layer 205 may also be formed using an In-situ Steam Generation (ISSG) process. The ISSG process is considered to be a low-pressure rapid oxidation thermal annealing technique, and performs a compensating oxidation growth while performing thermal annealing on the deposited thin film, which facilitates the formation of a more dense and uniform dielectric layer 205.
It will be appreciated that the dielectric layer 205 should not be too thin, otherwise it is difficult to achieve capacitive storage function for surge currents; the dielectric layer 205 should not be too thick, which would affect the bonding effect between the pixel wafer and the front surface of the device wafer in the subsequent process and increase the cost unnecessarily.
Referring to fig. 5, a patterned dielectric mask layer 241 is formed on the surface of the dielectric layer 205.
In particular, the dielectric mask layer 241 may be used to form a dielectric in a subsequent process.
Referring to fig. 6, the dielectric layer 205 is etched using the dielectric mask layer 241 as a mask to obtain the dielectric 215, where the dielectric 215 is located on a portion of the surface of the pad 204.
It should be noted that the proportion of the number of the part of the pads 204 to the total number of the plurality of pads 204 should not be too high, otherwise the normal function of the circuit is easily affected due to the insulating function of the dielectric 215; the proportion of the number of the portion of the pads 204 to the total number of the plurality of pads 204 should not be too low, otherwise it is difficult to sufficiently protect the switching noise.
As a non-limiting example, the number of the portion of pads 204 is 5% to 50% of the total number of the plurality of pads 204.
Referring to fig. 7, a pixel wafer 220 is provided and the pixel wafer 220 is bonded to the front side of the device wafer 200.
Specifically, the pixel wafer 220 and the front side of the device wafer 200 may be bonded via a dielectric layer 230.
More specifically, an initial dielectric layer may be deposited on the surface of the device wafer 200, and the initial dielectric layer may be planarized by a planarization process (CMP) to obtain the dielectric layer 230.
Preferably, the initial dielectric layer covers the plurality of pads 204 and the dielectric 215 during deposition to form the initial dielectric layer, so as to protect the plurality of pads 204 and the dielectric 215 in the subsequent bonding process and other processes.
Further, the pixel wafer 220 and the front side of the device wafer 200 are bonded (Bonding).
The material of the dielectric layer 230 may be selected from: silicon oxide and silicon nitride, wherein the silicon oxide may be, for example, SiO2The silicon nitride may be, for example, Si3N4。
Further, the material of the dielectric layer 230 is different from the material of the dielectric 215.
In the embodiment of the present invention, by setting the material of the dielectric layer 230 to be different from the material of the dielectric 215, it is possible to avoid the influence on the dielectric 215 in the process of etching the dielectric layer 230 when forming the conductive plug later, and use the top surface of the dielectric 215 as a Stop layer (Stop layer).
Preferably, silicon oxide may be used as the dielectric layer 230, and compared to silicon nitride, since the stress of silicon oxide is lower than that of silicon nitride, the bonding quality between the pixel wafer 220 and the device wafer 200 is improved.
Referring to fig. 8, a plurality of conductive plugs 222 are formed, the plurality of conductive plugs 222 penetrate through the pixel wafer 200, a portion of the plurality of conductive plugs 222 is connected to the pad 204, and another portion of the plurality of conductive plugs 222 is separated from the pad 204 by the dielectric 215.
Specifically, the step of forming the plurality of conductive plugs 222 may include: forming a patterned plug mask layer on the surface of the pixel wafer 200; and etching the pixel wafer 200 by taking the plug mask layer as a mask to obtain a plurality of conductive plug grooves.
Further, a conductive material is filled in the plurality of conductive plug trenches to form the plurality of conductive plugs 222.
Specifically, the material of the conductive plug 222 may be metal tungsten (W).
When the semiconductor device is a Three-dimensional Stack (3D Stack) structure, the conductive plug 222 may be referred to as a Through Via (TSV).
Referring to fig. 9, the pixel wafer 220 and the dielectric layer 230 are etched to form a pad window exposing a portion of the pad 204.
Specifically, the pad window may be used to lead out a power line 241 or a test line 242 to power or test the semiconductor device.
Further, a portion of the plurality of conductive plugs 222 includes: a power conductive plug adapted to be connected to the power line 241, another portion of the plurality of conductive plugs 222 being located within a predetermined range around the power conductive plug.
In the embodiment of the present invention, some of the conductive plugs 222 may include the conductive plug 222 without the dielectric 215, that is, without the MIM structure, and the power supply conductive plug connected to the power line 241 may be used to normally supply power to the semiconductor device.
Further, another part of the plurality of conductive plugs 222 may include the conductive plug 222 provided with the dielectric 215, that is, provided with the MIM structure, and by disposing another part of the plurality of conductive plugs 222 within a predetermined range around the power supply conductive plug, the another part may serve as a decoupling capacitor near the power supply line 241, thereby reducing switching noise.
It is noted that, as shown in fig. 9, another part of the plurality of conductive plugs 222 may include a conductive plug coupled to the power line 241, so as to store the current when the inrush current is too large, thereby reducing the influence of the switching noise on the device.
It is understood that the semiconductor device may also include a conductive plug 222 for testing, or a conductive plug 222 for other purposes.
In the embodiment of the present invention, by disposing a plurality of pads 204 electrically connected to the metal interconnect 202, a portion of the plurality of conductive plugs 222 is connected to the pads 204, and another portion of the plurality of conductive plugs 222 is separated from the pads 204 by the dielectric 215, a portion of the pads 204 can be connected to the conductive plugs 222 without affecting the circuit function, while another portion of the pads 204, the dielectric 215 and the conductive plugs 222 form an MIM capacitor structure as a decoupling capacitor to reduce the switching noise. Compared with the prior art, due to the lack of decoupling capacitors, the switching noise is larger, or due to the fact that additional decoupling capacitors are added, the chip space is occupied, by adopting the scheme of the embodiment of the invention, the switching noise can be reduced, and meanwhile, the conductive plug 222 and the gasket 204 are reused as two layers of metal in the MIM capacitor structure, so that the space utilization rate is improved, and the production cost is reduced.
Further, the number of the other part of the plurality of conductive plugs accounts for 5% -50% of the total number of the plurality of conductive plugs.
Specifically, the ratio of the number of the other portions of the plurality of conductive plugs 222 to the total number of the plurality of conductive plugs 222 should not be too high, otherwise the normal function of the circuit is easily affected due to the insulating function of the dielectric 215; the ratio of the number of the other portions of the plurality of conductive plugs 222 to the total number of the plurality of conductive plugs 222 should not be too low, otherwise it is difficult to sufficiently protect against switching noise.
As a non-limiting example, the number of another portion of the plurality of conductive plugs is between 5% and 50% of the total number of the plurality of conductive plugs.
Referring to fig. 10, fig. 10 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention. Compared with fig. 9, the coverage area of the dielectric 315 on the surface of the pad 204 is a smaller cross-sectional area between the pad 204 and the cross-sectional area of the conductive plugs 222, that is, the dielectric 315 is arranged to separate another part of the plurality of conductive plugs 222 from the pad 204 by an area as small as possible, wherein the direction of the cross-section is parallel to the flow direction of carriers of the device.
In the embodiment of the present invention, by disposing the dielectric 315 to separate another portion of the conductive plugs 222 from the liner 204 with an area as small as possible, it is helpful to avoid additional influence of the added dielectric 315 on the existing device, and to reduce the cost.
In an embodiment of the present invention, there is also provided an image sensor, and referring to fig. 8, the semiconductor device may include:
a device wafer 200, a front side of the device wafer 200 having a metal interconnect structure 202;
a plurality of pads 204 electrically connected to the metal interconnect structure 202;
a pixel wafer 220, a surface of the pixel wafer 220 being bonded to a front side of the device wafer 200;
a plurality of conductive plugs 222 extending through the pixel wafer 220, wherein a portion of the plurality of conductive plugs 222 is connected to the pad 204, and another portion of the plurality of conductive plugs 222 is separated from the pad 204 by a dielectric 215.
Further, the material of the dielectric 215 may be selected from: silicon oxide and silicon nitride.
The semiconductor device further includes: a dielectric layer 230 located between the pixel wafer 220 and the front side of the device wafer 200 for bonding the pixel wafer 220 and the device wafer 200; wherein the material of the dielectric layer 230 is different from the material of the dielectric 215.
Some of the plurality of conductive plugs 222 may include: a power conductive plug adapted to connect to a power line, another portion of the plurality of conductive plugs 222 may be located within a predetermined range around the power conductive plug.
The number of another portion of the plurality of conductive plugs 222 may be 5% to 50% of the total number of the plurality of conductive plugs 222.
For the principle, specific implementation and beneficial effects of the semiconductor device apparatus, reference is made to the foregoing description and related descriptions of the method for forming the semiconductor device shown in fig. 2 to fig. 10, and no further description is given here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A semiconductor device, comprising:
the device comprises a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure;
a plurality of pads electrically connected with the metal interconnect structure;
the surface of the pixel wafer is bonded with the front surface of the device wafer;
a plurality of conductive plugs penetrating through the pixel wafer, wherein one part of the plurality of conductive plugs is connected with the gasket, and the other part of the plurality of conductive plugs is separated from the gasket by a dielectric medium;
wherein a portion of the plurality of conductive plugs comprises: a power conductive patch adapted for connection to a power line, another portion of the plurality of conductive patches being located within a predetermined range around the power conductive patch.
2. The semiconductor device of claim 1, wherein the dielectric is of a material selected from the group consisting of: silicon oxide and silicon nitride.
3. The semiconductor device according to claim 1, further comprising:
the dielectric layer is positioned between the pixel wafer and the front surface of the device wafer and is used for bonding the pixel wafer and the device wafer;
wherein the dielectric layer is made of a material different from that of the dielectric.
4. The semiconductor device according to claim 1, wherein the number of the another portion in the plurality of conductive plugs accounts for 5% to 50% of the total number of the plurality of conductive plugs.
5. A method of forming a semiconductor device, comprising:
providing a device wafer, wherein the front surface of the device wafer is provided with a metal interconnection structure;
forming a plurality of pads electrically connected with the metal interconnect structure;
forming a dielectric on a portion of a surface of a liner;
providing a pixel wafer, and bonding the pixel wafer with the front surface of the device wafer;
forming a plurality of conductive plugs, wherein the plurality of conductive plugs penetrate through the pixel wafer, one part of the plurality of conductive plugs is connected with the liner, and the other part of the plurality of conductive plugs is separated from the liner by the dielectric;
wherein a portion of the plurality of conductive plugs comprises: a power conductive patch adapted for connection to a power line, another portion of the plurality of conductive patches being located within a predetermined range around the power conductive patch.
6. The method of claim 5, wherein the dielectric is formed from a material selected from the group consisting of: silicon oxide and silicon nitride.
7. The method of forming a semiconductor device according to claim 5,
the front surfaces of the pixel wafer and the device wafer are bonded through a dielectric layer;
wherein the dielectric layer is made of a material different from that of the dielectric.
8. The method of claim 5, wherein the number of the another portion of the plurality of conductive plugs accounts for 5% to 50% of the total number of the plurality of conductive plugs.
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| CN109638155A (en) * | 2018-12-10 | 2019-04-16 | 中国电子科技集团公司第二十四研究所 | Mim capacitor structure and preparation method thereof |
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| CN100539016C (en) * | 2007-04-24 | 2009-09-09 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacture method thereof |
| US8866260B2 (en) * | 2009-02-27 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | MIM decoupling capacitors under a contact pad |
| US8236645B1 (en) * | 2011-02-07 | 2012-08-07 | GlobalFoundries, Inc. | Integrated circuits having place-efficient capacitors and methods for fabricating the same |
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