CN108762719A - A kind of parallel broad sense inner product reconfigurable controller - Google Patents

Abstract

The parallel generalized inner product reconstruction controller of the present invention includes: an intermediate result calculation module, which receives source data and calculates an intermediate result vector according to the source data , generating a vector The address is stored in the bank; every time an intermediate result vector is completed The calculation generates a completion signal, and sends the completion signal to the final result calculation module as a start signal; the final result calculation module reads data into the complex multiplication accumulator for final result calculation to obtain the result matrix Lth element , generating a vector The address is stored in the bank; the data storage address processing module selects the data according to the ping-pong operation selection signal, and generates the correct bank address signal. Beneficial effects: the calculation time is less and the storage resource utilization rate is large, and the high real-time requirement for obtaining test statistics can be met when non-uniform detection is performed in many signal detection application scenarios.

Description

A Parallel Generalized Inner Product Reconfiguration Controller

technical field

The invention belongs to the technical field of non-uniform detection, in particular to a parallel generalized inner product reconstruction controller.

Background technique

Space-time adaptive processing (STAP) is a detection technology for moving objects. In the conventional STAP algorithm, the clutter covariance matrix must be estimated. When using quadratic data to estimate the clutter covariance matrix, the quadratic data must meet the condition of independent and identical distribution in order to reduce performance loss.

In practical applications, the detected signal echo will not only be polluted by natural clutter, but also be polluted by man-made non-uniform interference, so the independent and identical distribution condition is often not satisfied.

For the interference target in the sample, Melvin first proposed the idea of non-uniform detector (NHD), which can suppress its influence on the estimation of the clutter covariance matrix by eliminating the sample containing the interference target. The basic idea of NHD is: according to the difference between the statistical characteristics of the sample polluted by the interference target and other samples, set the corresponding test statistics to distinguish the two samples.

In the selection of NHD test statistics, Gerlach et al. proposed two criteria of generalized inner product (GIP) and adaptive power residual. Let X _L represent the Lth sample in the initial sample, then its corresponding autocorrelation matrix is expressed as: where T is the noise covariance matrix, so that Represents a sample covariance matrix composed of L samples, then the GIP value corresponding to each sample can be expressed as: According to the GIP value corresponding to each sample, the interference target can be effectively eliminated.

The ability of the generalized inner product non-uniform detection method to suppress clutter is related to the number of samples. The larger the number of samples, the more realistic the clutter covariance matrix data, and the stronger the ability to suppress clutter. The generalized inner product non-uniform detection method implemented in software has the problems of low precision and long operation time when calculating a large number of samples, so as to meet the high real-time requirements of the actual non-uniform detection technology.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the above-mentioned background technology, and propose a parallel generalized inner product reconstruction controller to better meet the needs of high real-time and large-point calculations in practical applications, specifically through the following technical solutions. :

The parallel generalized inner product reconstruction controller includes:

The intermediate result calculation module receives the source data and calculates the intermediate result vector Y _L according to the source data, generates the address of the vector Y _L , and stores it in the bank; every time the calculation of an intermediate result vector Y _L is completed, a completion signal is generated, and the completed The signal is sent to the final result calculation module as a start signal;

The final result calculation module continuously generates the address of the column X _L element of the matrix X and the address of the corresponding intermediate result vector Y _L element through the address generator, and reads the data into the complex multiplication accumulator to obtain the Lth element Z _L of the result matrix Z _1xN , Generate the address of the vector Z _L and store it in the bank;

The data storage address processing module selects data according to the ping-pong operation selection signal, and simultaneously processes signals for the same bank from the intermediate result calculation module and the final result calculation module to generate correct bank address signals.

The further design of the hardware realization method of described parallel generalized inner product operation is that the process of calculating Y _L is X _L and square matrix T, and the process of multiplying and accumulating each column, the number of rows and columns of said square matrix T and the number of columns of matrix X equal, the process of multiplying and accumulating is realized by multi-channel parallel computing.

A further design of the hardware implementation method of the parallel generalized inner product operation is that the intermediate result calculation module is implemented in a four-way parallel implementation.

The further design of the hardware implementation method of the parallel generalized inner product operation is that the source data storage method of the intermediate result calculation module is: the matrix T is stored in bank0-bank3 by column, and continues to be stored in bank4-bank7 by column after it is full ;Matrix X is stored in bank8-bank11 by column.

The further design of the hardware implementation method of the parallel generalized inner product operation lies in that the intermediate result storage mode of the intermediate result calculation module is as follows: odd items are stored in bank12, and even items are stored in bank13.

The further design of the hardware implementation method of the parallel generalized inner product operation is that the intermediate result calculation module performs the intermediate result calculation process as follows: in an operation process, first the address generator generates a column of elements X _L and four columns of T matrix of X The element address, and at the same time transport the corresponding matrix element data, input the complex number multiplied by the accumulator to obtain the intermediate result Y _L ; then the address generator generates the storage address of the intermediate result, and stores the intermediate result in the bank.

The further design of the hardware implementation method of the parallel generalized inner product operation is that the final result calculation module performs the final result calculation process as follows: when the final result calculation module obtains the intermediate result calculation completion signal, the address generator continuously generates the columns of the matrix X The address of the X _L element and the address of the corresponding intermediate result vector Y _L element; at the same time input to the complex multiplication accumulator to obtain the final result Z _L , the address generator generates the final result storage address, and stores the final result in the bank.

The further design of the hardware implementation method of the parallel generalized inner product operation is that the complex multipliers are pipelined single-precision floating-point units with a delay of 4 clock cycles, and the memory access delay of the complex multipliers is set to 6 cycles .

A further design of the hardware implementation method of the parallel generalized inner product operation is that there are five complex multiplication accumulators, four of which are used for four-way parallel calculation of intermediate results, and the other is used for synchronous calculation of final results.

The further design of the hardware implementation method of the parallel generalized inner product operation is that each complex multiplication accumulator is composed of a complex multiplier and three complex adders, and the area of DC integration is 19993.56 μm ² in 40nm CMOS technology.

Advantages of the invention

The parallel generalized inner product reconstruction controller provided by the present invention adopts the strategy of calculating a final result element immediately after calculating an intermediate result, and the time for calculating ZL _-1 can be hidden in the time for calculating _YL , and the calculation time is less and storage High resource utilization. The parallel generalized inner product reconstruction controller can meet the high real-time requirements for obtaining test statistics when performing non-uniform detection in many signal detection application scenarios.

Description of drawings

Figure 1 is a schematic diagram of the architecture of a parallel generalized inner product reconstruction controller.

Fig. 2 is a schematic diagram of parallel generalized inner product data storage.

Fig. 3 is a schematic diagram of the calculation flow of the parallel generalized inner product algorithm.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation cases.

As shown in Figure 1, the parallel generalized inner product reconstruction controller of this embodiment takes four-way parallelism as an example, and is mainly composed of three sub-modules: an intermediate result calculation module, a final result calculation module, and a data storage address processing module. The intermediate result calculation module is used to calculate intermediate results; the final result calculation module calculates the final result; the data storage address processing module processes bank addresses and other related signals.

The intermediate result calculation module is a fully pipelined calculation of the intermediate result vector Y _L , including generating the element address of the X _L column, performing the inner product multiplication and accumulation operation on the elements of the X _L column and each column of the square matrix T _MxM to obtain the intermediate result vector Y _L , and generating Address of vector Y _L , stored in bank. Every time a calculation of Y _L is completed, a completion signal is given to the final result calculation module as a start signal for its calculation.

The final result calculation module continuously generates the address of the column X _L element of the matrix X and the address of the corresponding intermediate result vector Y _L element through the address generator, and reads the data into the complex multiplication accumulator to obtain the Lth element Z _L of the result matrix Z _1xN , Generate the address of the vector Z _L and store it in the bank.

The data storage address processing module selects data according to the ping-pong operation selection signal, and simultaneously processes the signals for the same bank from the intermediate result calculation module and the final result calculation module to generate correct bank address and other signals.

As shown in Figure 1, the storage unit includes 15 banks, where the matrix T is stored in bank0-7, the matrix X is stored in bank8-11, the intermediate result Y _L is stored in bank12 and bank13, and the final parallel generalized inner product matrix is stored in bank14 . The arithmetic unit includes 5 complex multiplication accumulators, complex multiplication accumulators 0-3 are used for four-way parallel calculation of intermediate results, and complex multiplication accumulator 4 is used for simultaneous calculation of final results.

Figure 2 is a schematic diagram of parallel generalized inner product data storage. The source data storage method is as follows: the matrix T is stored in bank0-bank3 by column, and continues to be stored in bank4-bank7 by column after it is full; the matrix X is stored in bank8-bank11 by column. Such storage is convenient for 4-way parallel operation when calculating the intermediate result Y _L , and can also simplify the design of the corresponding DMA module; intermediate results Y _L , Y ₁ , Y ₃ ... and other odd items are stored in bank12 (the latter covers the former), Even items such as Y ₂ , Y ₄ ... are stored in bank13 (the latter covers the former). The final generalized inner product matrix is stored in bank14.

As shown in Figure 3, the process of calculating the intermediate results of the parallel generalized inner product algorithm is as follows: in the course of one operation, first, the address generator 1 generates the addresses of one column element X _L of X and four columns T matrix elements, and at the same time transfers the corresponding matrix element data , input the complex number multiplied by the accumulator to get the intermediate result Y _L , then the address generator 2 generates the storage address of the intermediate result, and stores the intermediate result in the bank.

Similarly, the process of calculating the final result of the parallel generalized inner product algorithm is as follows: during one operation, when the module receives a signal of completion of intermediate result calculation, the address generator 1 continuously generates the addresses of the column X _L elements of the matrix X, and The address of the corresponding intermediate result vector Y _L element. At the same time, it is input to the complex multiplication accumulator to obtain the final result Z _L , and then the address generator 2 generates the storage address of the final result, and stores the final result in the bank.

The parallel generalized inner product algorithm hardware of the present invention realizes a complete calculation including the following steps:

Step 1) put L=1, start to calculate from the first column of matrix X;

Step 2) Calculate the intermediate result Y _L .

Calculating the intermediate result Y _L includes the following steps:

Step 2-1) According to the address generated by the address generator sub-module, the elements of X _L and (T ₁ T ₂ T ₃ T ₄ ) are sequentially taken and sent to the multiplication and accumulation sub-module for complex multiplication and accumulation operation to obtain (Y _L1 Y _L2 Y _L3 Y _L4 );

Step 2-2) Write (Y _L1 Y _L2 Y _L3 Y _L4 ) into the intermediate result bank sequentially according to the address generated by the address generator sub-module, and at the same time take the next set of 4-column T matrix elements and X _L , repeat 1 ) and 2), until the calculation of Y _L is completed;

Step 3) Calculate the final result Z _L . Synchronous with 1) and 2), if Y _L-1 has been generated, according to the address generated by the address generator, the elements of X _L-1 and Y _L-1 are sequentially taken for complex multiplication and accumulation, and Z _L-1 is obtained according to The address generated by the address generator writes the final result into the final result bank;

Step 4) If L<N, L=L+1, jump to step 2;

Step 5) Take the elements of X _N and Y _N in turn to perform complex multiplication and accumulation to obtain Z _N , store it in the bank, and complete the inner product operation.

The complex multipliers and complex adders used in the parallel generalized inner product reconstruction controller of this embodiment are pipelined single-precision floating-point units with a delay of 4 clock cycles, and the memory access delay is 6 cycles, using EDA simulation /Comprehensive tool, the working frequency is up to 1GHz.

The parallel generalized inner product reconstruction controller of this embodiment consumes five complex multiply-accumulators in total, four of which are used for four-way parallel calculation of intermediate results, and the other is used for synchronous calculation of final results. Each complex multiply-accumulator is composed of a complex multiplier and three complex adders, and the area of DC integration is 19993.56μm ² in 40nm CMOS process.

The parallel generalized inner product reconstruction controller of this embodiment adopts the strategy of calculating a final result element immediately after calculating an intermediate result, and the time for calculating ZL _-1 can be hidden in the time for calculating _YL , which is compared to the time for calculating the complete The method of calculating the final result in parallel after the intermediate result has less calculation time and high storage resource utilization.

The parallel generalized inner product reconstruction controller of this embodiment is characterized by fast calculation speed, flexible and variable number of points, and high utilization rate of storage resources. It can meet the high real-time requirements for obtaining test statistics when performing non-uniform detection in digital signal processing with a large amount of data, such as real-time signal detection application scenarios.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of changes or modifications within the technical scope disclosed in the present invention. Any transformation should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A parallel generalized inner product reconstruction controller, characterized in that: comprising: The intermediate result calculation module receives the source data and calculates the intermediate result vector Y _L according to the source data, generates the address of the vector Y _L , and stores it in the bank; every time the calculation of an intermediate result vector Y _L is completed, a completion signal is generated, and the completed The signal is sent to the final result calculation module as a start signal; The final result calculation module continuously generates the address of the column X _L element of matrix X and the address of the corresponding intermediate result vector Y _L element through the address generator, and reads the data into the complex multiplication accumulator for final result calculation to obtain the result matrix Z _1xNth L The element Z _L generates the address of the vector Z _L and stores it in the bank; The data storage address processing module selects data according to the ping-pong operation selection signal, and simultaneously processes signals for the same bank from the intermediate result calculation module and the final result calculation module to generate correct bank address signals. 2. the hardware implementation method of parallel generalized inner product operation according to claim 1, is characterized in that: the process of calculating Y _L is X _L and square matrix T, and the process of multiplying and accumulating each column, the ranks of described square matrix T The number is equal to the number of columns of the matrix X, and the process of multiplying and accumulating is realized by multi-channel parallel computing. 3. The parallel generalized inner product reconstruction controller according to claim 2, characterized in that: the intermediate result calculation module is implemented in a four-way parallel implementation. 4. The parallel generalized inner product reconstruction controller according to claim 3, characterized in that: the source data storage mode of the intermediate result calculation module is: the matrix T is stored in bank0-bank3 by column, and continues to be column-by-column after it is full Stored in bank4-bank7; matrix X is stored in bank8-bank11 by column. 5. The parallel generalized inner product reconstruction controller according to claim 3, characterized in that: the intermediate result storage method of the intermediate result calculation module is as follows: odd items are stored in bank12, and even items are stored in bank13. 6. The parallel generalized inner product reconstruction controller according to claim 1, characterized in that: the intermediate result calculation module performs the intermediate result calculation process as follows: in an operation process, at first the address generator generates a column element X of X _L and four columns of T matrix element addresses, simultaneously transport the corresponding matrix element data, and input the complex multiplication accumulator to obtain the intermediate result Y _L ; then the address generator generates the intermediate result storage address, and stores the intermediate result in the bank. 7. parallel generalized inner product reconstruction controller according to claim 1, is characterized in that: the flow process that final result calculation module carries out final result calculation is: when final result calculation module obtains intermediate result calculation completion signal, address generator Continuously generate the address of the column X _L element of the matrix X and the address of the corresponding intermediate result vector Y _L element; at the same time input to the complex multiplication accumulator to obtain the final result Z _L , the address generator generates the final result storage address, and stores the final result in in bank. 8. parallel generalized inner product reconfiguration controller according to claim 1, is characterized in that: described complex multiplier is the pipeline single-precision floating-point operation unit that delays 4 clock cycles, and the memory access delay of complex multiplier Set to 6 cycles. 9. The parallel generalized inner product reconstruction controller according to claim 1, characterized in that: there are five complex multiplication accumulators, four of which are used for four-way parallel calculation of intermediate results, and the other is used for synchronous calculation Final result. 10. parallel generalized inner product reconstruction controller according to claim 1, is characterized in that: each complex multiplying accumulator is made up of a complex multiplier and three complex adders, and the area of DC synthesis under 40nm CMOS technology It is 19993.56 μm ² .