CN108761637B - Three-dimensional multilayer waveguide mode multiplexing and demultiplexing device and preparation method thereof - Google Patents
Three-dimensional multilayer waveguide mode multiplexing and demultiplexing device and preparation method thereof Download PDFInfo
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12007—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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Abstract
The invention relates to a three-dimensional multilayer waveguide mode multiplexing and demultiplexing device and a preparation method thereof, belongs to the technical field of optical communication devices, and particularly aims at a mode division multiplexing system. The invention breaks through the limitation of the traditional two-dimensional planar waveguide structure through the three-dimensional multilayer waveguide integrated structure, increases the integrated dimension of the device, and improves the integrated level and the flexibility of the device, thereby further improving the communication capacity of the system. The boundary alignment of any side of the upper and lower two layers of waveguides of the three-dimensional waveguide realizes the direct stereo coupling of the fundamental mode and the high-order mode, overcomes the defect that the traditional three-dimensional mode multiplexer cannot realize the direct coupling of modes, and simplifies the structure and complexity of the device. The invention can be prepared based on a mature CMOS process, and realizes high-efficiency, low-cost and batch manufacturing; the invention can realize mode three-dimensional flexible coupling, lay a good foundation for the on-chip mode multiplexing technology, and further realize flexible mode routing applied to the mode division multiplexing network.
Description
Technical Field
The invention relates to a three-dimensional multilayer waveguide mode multiplexing and demultiplexing device and a preparation method thereof, belongs to the technical field of optical communication devices, and particularly aims at a mode division multiplexing system.
Background
The communication industry has evolved rapidly, and the large data age has provided higher demands on the transmission of communication networks, and the capacity demand of people for bandwidth has increased. The most widely used of conventional optical communication systems is Wavelength Division Multiplexing (WDM) technology. But today, the bandwidth requirements far exceed the bandwidth capacity offered by WDM technology, and thus the Mode-division multiplexing, MDM technology has gained attention.
The MDM technology utilizes different modes in optical fibers or waveguides to realize data transmission of different channels, increases one direction for the optical communication multiplexing technology, has smaller volume and higher information density, and thus realizes higher integration level.
The current mode multiplexing method mainly comprises the following steps: the method comprises the steps of utilizing a scheme of adjusting phases after beam splitting of a multimode interferometer to realize mode spot matching, an asymmetric directional coupler scheme based on a coupling mode theory, an asymmetric Y-branch structure based on a principle of mode adiabatic evolution or a structure of a directional coupler.
The current mode division multiplexing technology methods are basically mode multiplexing and demultiplexing devices based on two-dimensional plane technology, and the mode division multiplexing technology of the two-dimensional plane technology limits the integration level of devices and is insufficient for meeting the demands of people on information transmission. In order to further expand the communication capacity and improve the integration level, waveguide transmission technology based on three-dimensional multilayer waveguide stereo technology is proposed. The three-dimensional multilayer waveguide integrated structure breaks through the limitation of the traditional two-dimensional planar waveguide structure, increases the integrated dimension of the device, and improves the integrated level and flexibility of the device, thereby further improving the communication capacity of the system. The three-dimensional mode multiplexing technology which is currently realized is applied to the three-dimensional mode multiplexing technology through a mode rotator, and the realization method increases the volume of a device and the complexity of a process and needs to be further optimized for use.
The invention provides a three-dimensional multilayer waveguide mode multiplexer and a demultiplexer. The traditional two-dimensional planar waveguide mode multiplexing and demultiplexing device is improved, the structure is different from the traditional two-dimensional planar waveguide structure, the three-dimensional multilayer waveguide mode multiplexing and demultiplexing device is built in a three-dimensional space, the innovation in the aspect of structure is realized by aligning the boundaries of any one side of the upper layer of waveguide and the lower layer of waveguide, the mode direct coupling can be realized, the defect that the traditional three-dimensional device cannot be directly coupled is overcome, and therefore the requirements of widening communication capacity and meeting the increasing large communication capacity of people are met.
Disclosure of Invention
The invention aims to provide a three-dimensional multilayer waveguide mode multiplexing and demultiplexing device structure and a preparation method thereof, break through the limitation of the traditional two-dimensional planar waveguide structure, increase the integrated dimension of devices through the three-dimensional multilayer waveguide integrated structure, and improve the integrated level and flexibility of the devices, thereby further improving the communication capacity of a system and meeting the requirement of people on continuous increase of bandwidth. The mode direct three-dimensional coupling is realized through the boundary alignment structure of any side of the upper waveguide and the lower waveguide, and the defect that the traditional device cannot be directly coupled and needs to be added with additional devices is overcome.
The invention adopts the following technical scheme:
the invention relates to a three-dimensional multilayer waveguide mode multiplexing and demultiplexing device, which comprises: the substrate layer is provided with a lower cladding layer, a lower waveguide layer is arranged on the lower cladding layer, an intermediate isolation layer is paved on the lower waveguide layer, an upper waveguide layer is arranged on the intermediate isolation layer, an upper cover layer is covered on the upper waveguide layer, the boundary of any side of the lower waveguide layer is aligned with the boundary of any side of the upper waveguide layer, and the dislocation of the waveguide width centers of the lower waveguide layer and the upper waveguide layer is more than 0 and less than 5 mu m.
The three-dimensional multilayer waveguide structure has bidirectional symmetry; in terms of size, the lower layer waveguide 4 and the upper layer waveguide 3 are the same in height and different in width.
The invention relates to a preparation method of a three-dimensional multilayer waveguide mode multiplexing and demultiplexing device, which comprises the following steps:
step 1: and (3) taking a silicon substrate, treating the surface of the silicon substrate, and depositing a silicon dioxide cladding layer with the thickness of 2-3 mu m on the surface of the silicon substrate by a chemical vapor deposition (PECVD), wherein the cladding layer is a lower cladding layer. The reactive gas for depositing silicon dioxide is Silane (SiH) 4 ) And nitric oxide (N) 2 O). In the deposition process, the temperature of the upper stage plate is 300 ℃, the temperature of the lower stage plate is 300 ℃, the power of a radio frequency source is 700W, the pressure of a cavity is 300mTorr, and N 2 O flow rate is 2000sccm, siH 4 The flow rate was 17sccm,
step 2: performing photoresist homogenizing lithography on the lower cladding, and spreading the photoresist on the surface of the chip at a low rotation speed of 1500-1750r/min for 3-5s; the photoresist is then volatilized at a high speed to achieve the desired thickness of 210-230nm, typically at a speed of 4000-4250r/min for 29-40s, and then the excess photoresist is washed away. The negative photoresist ma-N2403 is mainly used, the exposure time is short, the index meets the processing precision requirement,
step 3: performing photoetching, preparing a waveguide structure by using photoetching and etching processes, wherein the model number of photoetching equipment is Raith150 Two The EBL of (2) is used as an exposure device, and electron beam exposure is carried out without making a mask plate according to a maskThe pattern and sequence in the graph are completed sequentially. The exposure adopts a mode of combining a fixed platform and a movable platform so as to obtain the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, the aperture size of the electron gun is generally 10 μm,
step 4: etching adopts Inductively Coupled Plasma (ICP) technology, and SF is selected as reaction gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The flow rate of (2) is 4.9sccm, the power of the coil RF is 500W, the frequency is 13.56Mhz, the power of the substrate RF is 20W, the frequency is 13.56Mhz, the operating pressure is 1mTorr, the chamber temperature is generally controlled to 65 ℃, the etching speed is 1.83nm/s,
step 5: removing residual mask from etched sample wafer, depositing silicon dioxide intermediate isolation layer with thickness of 190-210nm, removing protruding portion of intermediate isolation layer by chemical mechanical method,
step 6: performing secondary photoresist homogenizing photoetching on the middle isolation layer, and spreading the photoresist on the surface of the chip at a low rotating speed at a speed of 1500-1750r/min and for 3-5s; the photoresist is then volatilized at a high speed to achieve the desired thickness of 210-230nm, typically at a speed of 4000-4250r/min for 29-40s, and then the excess photoresist is washed away. The negative photoresist ma-N2403 is mainly used, the exposure time is short, the index meets the processing precision requirement,
step 7: performing a secondary photoetching step, preparing a waveguide structure by utilizing photoetching and etching processes, wherein the photoetching equipment adopts a model Raith150 Two The EBL of (2) is used as exposure equipment, and electron beam exposure is completed sequentially according to patterns and sequences in a mask pattern without manufacturing a mask plate. The exposure adopts a mode of combining a fixed platform and a movable platform so as to obtain the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, the aperture size of the electron gun is generally 10 μm,
step 8: the secondary etching adopts inductive couplingPlasma technology (ICP), reactive gas selection SF 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 4.9sccm, 500W for coil RF, 13.56Mhz for frequency, 20W for substrate RF, 13.56Mhz for frequency, 1mTorr for operating pressure, 65℃for cavity temperature, 1.83nm/s for etching rate,
step 9: and removing residual mask, depositing a silicon dioxide upper covering layer with the thickness of 2-3 mu m on the sample wafer after the secondary etching, and removing the protruding part of the middle isolation layer by using a chemical mechanical method after the deposition is finished.
The invention can further optimize the technical scheme of the preparation method of the three-dimensional waveguide mode multiplexing and demultiplexing device by adopting the following technical measures:
before the step 2, a layer of HMDS (hexamethyldisilazane) is spun to reduce the surface roughness, so as to play a role of an anti-reflection layer.
Compared with the prior art, the invention has the following advantages:
1. the invention breaks through the traditional two-dimensional planar waveguide structure, realizes the structure of the three-dimensional multi-layer waveguide mode multiplexing and de-multiplexing device, increases the integrated dimension of the device, and improves the integrated level and flexibility of the device, thereby further improving the communication capacity of the system.
2. According to the invention, the boundary alignment of any side of the upper and lower waveguides of the three-dimensional multilayer waveguide is adopted, so that the direct stereoscopic coupling of the fundamental mode and the high-order mode is realized, the defect that the traditional three-dimensional mode multiplexer cannot realize the direct coupling of modes is overcome, and the structure and the complexity of the device are simplified. The literature Nobutomo Hanzawa, kuimasa Saitoh, "Mode multi/demultiplexing with parallel waveguide for Mode division multiplexed transmission" Optics Express, vol.22, no.24, pp.29321-29330 (2014). Shows a multimode multiplexer and demultiplexer which requires the addition of a Mode converter to achieve multimode multiplexing. At present, there is no report of structures or schemes that can achieve direct stereo coupling.
The mode multiplexing and de-multiplexing device designed by the invention can realize direct coupling of transmission modes through left boundary alignment between the upper waveguide and the lower waveguide, namely, the modes are input by the upper input waveguide and directly coupled into the lower trunk waveguide, so that the direct coupling of the modes is realized, a mode converter is avoided, a plurality of input waveguides can be placed in the same plane, and the integration level of the device is increased.
3. According to the invention, the three-dimensional multilayer waveguide side boundaries are aligned and have bidirectional symmetry, when the left side boundary or the right side boundary is aligned, the coupling development can be carried out on the left side and the right side, the development space of the device is wide, and the operability is strong.
4. The invention can be prepared based on a mature CMOS process, has low operation cost by utilizing the prior art, can realize batch manufacturing, has higher production efficiency due to the mature prior art, and has competitive advantage.
5. The device has compact size structure, nano-scale waveguide structure, small structure space, small device length, space saving and high integration level and excellent performance.
6. The invention can be compatible with the prior multiplexing technology (WDM, TDM, SDM, etc.), and can be compatible with various multiplexing technologies, thereby widening the application range and bandwidth capacity, and having high compatibility and wide application range.
The three-dimensional multi-layer waveguide mode multiplexing and de-multiplexing device has the advantages of easy implementation, mature process, compact size structure and high CMOS process compatibility, has high waveguide mode coupling rate, can ensure that the mode energy transmitted in the waveguide mode is transmitted into other layers of waveguides as much as possible, ensures the transmission efficiency, realizes the mode three-dimensional flexible coupling, lays a good foundation for the on-chip mode multiplexing technology, further realizes the flexible mode routing applied to a mode division multiplexing network, and lays a foundation for realizing high-performance optical signal processing chips or devices in optical communication and photon systems.
Drawings
The invention will be further described with reference to the drawings and examples.
FIG. 1 is a schematic diagram of a three-dimensional multi-layer mode multiplexer and demultiplexer;
FIG. 2 is a schematic diagram of a mode multiplexer and demultiplexer;
FIG. 3 is a schematic cross-sectional view of a mode multiplexing and de-multiplexing waveguide;
FIG. 4 is a pattern multiplexing and de-multiplexing supermodulo odd-mode energy distribution diagram;
FIG. 5 is a graph of the mode multiplexing and de-multiplexing supermode even mode energy distribution;
fig. 6 is a schematic diagram of a mode transmission structure;
FIG. 7 is a schematic view of a substrate layer;
FIG. 8 is a schematic diagram of lower cladding fabrication;
FIG. 9 is a schematic diagram of the fabrication of an underlying waveguide layer;
FIG. 10 is a schematic view of an underlying waveguide
FIG. 11 is a schematic diagram of an intermediate spacer fabrication;
FIG. 12 is a schematic diagram of an intermediate spacer layer fabrication completion;
FIG. 13 is a schematic diagram of upper waveguide layer fabrication;
FIG. 14 is a schematic view of an upper layer waveguide;
FIG. 15 is a schematic diagram of the top cover layer fabrication;
in the figure: 1 is a substrate layer, 2 is a lower cladding layer; 3 is an upper layer waveguide; 4 is an underlying waveguide; 5 is an upper cladding layer, 6 is an intermediate isolation layer, 7 is a lower waveguide fabrication cladding layer, and 8 is an upper waveguide fabrication cladding layer.
Detailed Description
A three-dimensional multi-layer waveguide mode multiplexer and demultiplexer, comprising: a substrate layer 1, a lower cladding layer 2 is arranged on the substrate layer, a lower layer waveguide 4 is arranged on the lower cladding layer 2, an intermediate isolation layer 6 is paved on the lower layer waveguide 4, an upper layer waveguide 3 is arranged on the intermediate isolation layer, an upper cover layer 5 is covered on the upper layer waveguide 3, the boundary of any side of the lower layer waveguide 4 is aligned with the boundary of any side of the upper layer waveguide 3, the waveguide width centers of the lower layer waveguide 4 and the upper layer waveguide 3 are staggered by more than 0 and less than 5 mu m,
in the present embodiment, the left side boundaries of the lower layer waveguide 4 and the upper layer waveguide 3 are aligned, or the right side boundaries of the lower layer waveguide 4 and the upper layer waveguide 3 are aligned and have bilateral symmetry. The lower waveguide 4 and the upper waveguide 3 have the same height and different widths. The lower layer waveguide 4 comprises a first trunk waveguide section 401, a second trunk waveguide section 402 and a third trunk waveguide section 403, which are used for realizing multiplexing and demultiplexing of different high-order modes; the upper layer waveguide 3 includes a first input waveguide 301, a second input waveguide 302, and a third input waveguide 303; the first input waveguide 301 is aligned with the first main waveguide segment 401 at either side boundary, the second input waveguide 302 is aligned with the second main waveguide segment 402 at either side boundary, and the third input waveguide 303 is aligned with the third main waveguide segment 403 at either side boundary; the lower waveguides 4 are arranged in rows and the widths of the lower waveguides gradually change according to the arrangement sequence, the width of the first trunk waveguide section 401 is smaller than the width of the second trunk waveguide section 402, and the width of the second trunk waveguide section 402 is smaller than the width of the third trunk waveguide section 403 and are connected with each other through tapered waveguides.
The preparation method of the three-dimensional waveguide mode multiplexing and demultiplexing device comprises the following steps:
step 1: and (3) taking a silicon substrate, treating the surface of the silicon substrate, and depositing a silicon dioxide cladding layer with the thickness of 2-3 mu m on the surface of the silicon substrate by a chemical vapor deposition (PECVD), wherein the cladding layer is a lower cladding layer. The reactive gas for depositing silicon dioxide is Silane (SiH) 4 ) And nitric oxide (N) 2 O). In the deposition process, the temperature of the upper stage plate is 300 ℃, the temperature of the lower stage plate is 300 ℃, the power of a radio frequency source is 700W, the pressure of a cavity is 300mTorr, and N 2 O flow rate is 2000sccm, siH 4 The flow rate was 17sccm,
step 2: performing photoresist homogenizing lithography on the lower cladding, and spreading the photoresist on the surface of the chip at a low rotation speed of 1500-1750r/min for 3-5s; the photoresist is then volatilized at a high speed to achieve the desired thickness of 210-230nm, typically at a speed of 4000-4250r/min for 29-40s, and then the excess photoresist is washed away. The negative photoresist ma-N2403 is mainly used, the exposure time is short, the index meets the processing precision requirement,
step 3: performing photoetching, preparing a waveguide structure by using photoetching and etching processes, wherein the model number of photoetching equipment is Raith150 Two The EBL of (B) is used as exposure equipment, and electron beam exposure does not need mask plate manufactureThe patterning is done sequentially in the pattern and order of the mask pattern. The exposure adopts a mode of combining a fixed platform and a movable platform so as to obtain the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, the aperture size of the electron gun is generally 10 μm,
step 4: etching adopts Inductively Coupled Plasma (ICP) technology, and SF is selected as reaction gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The flow rate of (2) is 4.9sccm, the power of the coil RF is 500W, the frequency is 13.56Mhz, the power of the substrate RF is 20W, the frequency is 13.56Mhz, the operating pressure is 1mTorr, the chamber temperature is generally controlled to 65 ℃, the etching speed is 1.83nm/s,
step 5: removing residual mask from etched sample wafer, depositing silicon dioxide intermediate isolation layer with thickness of 190-210nm, removing protruding portion of intermediate isolation layer by chemical mechanical method,
step 6: performing secondary photoresist homogenizing photoetching on the middle isolation layer, and spreading the photoresist on the surface of the chip at a low rotating speed at a speed of 1500-1750r/min and for 3-5s; the photoresist is then volatilized at a high speed to achieve the desired thickness of 210-230nm, typically at a speed of 4000-4250r/min for 29-40s, and then the excess photoresist is washed away. The negative photoresist ma-N2403 is mainly used, the exposure time is short, the index meets the processing precision requirement,
step 7: performing a secondary photoetching step, preparing a waveguide structure by utilizing photoetching and etching processes, wherein the photoetching equipment adopts a model Raith150 Two The EBL of (2) is used as exposure equipment, and electron beam exposure is completed sequentially according to patterns and sequences in a mask pattern without manufacturing a mask plate. The exposure adopts a mode of combining a fixed platform and a movable platform so as to obtain the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, the aperture size of the electron gun is generally 10 μm,
step 8: secondary etching processSF is selected for the reaction gas by Inductively Coupled Plasma (ICP) 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 4.9sccm, 500W for coil RF, 13.56Mhz for frequency, 20W for substrate RF, 13.56Mhz for frequency, 1mTorr for operating pressure, 65℃for cavity temperature, 1.83nm/s for etching rate,
step 9: and removing residual mask, depositing a silicon dioxide upper covering layer with the thickness of 2-3 mu m on the sample wafer after the secondary etching, and removing the protruding part of the middle isolation layer by using a chemical mechanical method after the deposition is finished.
To further illustrate the aspects and features of the present invention, the present invention is further described below with reference to the accompanying drawings, but the present invention is not limited to the embodiments.
Embodiment one:
referring to fig. 2, a three-dimensional multi-layer waveguide mode multiplexer and demultiplexer includes a substrate layer 1, a lower cladding layer 2, an upper layer waveguide 3, a lower layer waveguide 4, an upper layer cladding layer 5 and an intermediate isolation layer 6.
The three-dimensional multi-layer waveguide mode multiplexing and demultiplexing device shown in fig. 2, the lower layer waveguide 4 has a width gradual change structure, and comprises a first trunk waveguide section 401, a second trunk waveguide section 402 and a third trunk waveguide section 403, so that multiplexing and demultiplexing of different high-order modes can be realized; the upper layer waveguide 3 includes a first input waveguide 301, a second input waveguide 302, and a third input waveguide 303.
By constructing a three-dimensional multi-layer waveguide structure, compared with a traditional two-dimensional planar waveguide mode multiplexing and demultiplexing structure, the structure of the invention is original: firstly, through the left side boundary alignment of the upper layer waveguide and the lower layer waveguide, the direct coupling of the mode transmission is realized, namely, the mode is input by the upper layer narrow waveguide and directly coupled into the lower layer wide waveguide, and a plurality of narrow waveguides, namely, a plurality of input ports, can be placed in the same plane, so that the transmission efficiency is improved; secondly, the two-dimensional planar waveguide technology is mature at present, the cost is low, and the waveguide is compatible with the CMOS technology in the manufacturing technology, so that the technology of the invention has excellent foundation and is easy to realize.
Embodiment two:
referring to fig. 3, a three-dimensional multi-layer waveguide multiplexing and demultiplexing device comprises a substrate layer 1, a lower cladding layer 2, an upper layer waveguide 3, a lower layer waveguide 4, an upper layer cover layer 5 and an intermediate isolation layer 6.
The three-dimensional multi-layer waveguide single-mode multiplexer and demultiplexer shown in fig. 3 belongs to a specific case analysis example, and in the structure, a lower layer trunk waveguide and an upper layer input waveguide only have one section of structure, which belongs to the local case in the first embodiment, and is specifically analyzed. The widths h of the upper and lower waveguides are 220nm, and the widths w of the lower waveguide are 1 Upper waveguide width w =838 nm 2 =400 nm, upper and lower waveguide pitch gap=200 nm. The upper layer waveguide 3 adopts a P-type silicon waveguide, and the lower layer waveguide 4 adopts a silicon waveguide.
FIG. 4 is a cross-sectional view of a three-dimensional multi-layer waveguide single mode multiplexer and demultiplexer and an odd mode diagram; fig. 5 is a cross-sectional view and an even mode view of a three-dimensional multi-layer waveguide single mode multiplexer and demultiplexer, illustrating a state diagram at the time of a transmission mode. Fig. 6 is a mode transmission diagram, and fig. 6 is a mode transmission diagram of an upper-layer input waveguide and a lower-layer trunk waveguide.
The coupling ratio of the mode transmission in fig. 3 reaches 92.7%, the mode crosstalk is 15dB, and the insertion loss is 0.18dB.
Embodiment III:
referring to fig. 7-15, a method of fabricating a three-dimensional multi-layer waveguide mode multiplexer and demultiplexer is described in detail below. The method comprises the following steps:
step 1: and (5) processing the substrate. Firstly, mixing solution of strong oxidant sulfuric acid and hydrogen peroxide in a ratio of 4:1, heating to carbonize pollutants and removing the carbonized pollutants; next, immersing the substrate in NH 3 F and HF are diluted in the ratio of 1:6 for 30-40s, and the primary oxide layer on the surface of the silicon substrate is removed. The surface of the substrate is thoroughly cleaned on the premise of ensuring the surface quality not to be damaged, and then acetone, methanol and isopropyl alcohol are used for cleaning the silicon surface.
Step 2: and a lower cladding layer. A silicon dioxide cladding layer with the thickness of 2.2-3 mu m is deposited on the surface of the silicon substrate by a chemical vapor deposition (PECVD) method, and the cladding layer is a lower cladding layer. The reactive gas for depositing silicon dioxide is Silane (SiH) 4 ) And nitric oxide (N) 2 O). In the deposition process, the temperature of the upper stage plate is 300 ℃, the temperature of the lower stage plate is 300 ℃, the power of a radio frequency source is 700W, the pressure of a cavity is 300mTorr, and N 2 O flow rate is 2000sccm, siH 4 The flow rate was 17sccm.
Step 3: and (5) photoresist homogenizing and photoetching. The lower cladding layer is coated with a corresponding photoresist. The indexes such as the thickness, particle contamination, uniformity and the like of the photoresist are greatly related to the device, the speed and the time consumption used in the photoresist homogenizing process. The spin process comprises two stages with different rotation speeds: first, the substrate is fixed on a vacuum objective table; then spreading the photoresist on the surface of the substrate at a low rotating speed, wherein the typical rotating speed is 1500-1750r/min for 3-5s; then, the photoresist is made to reach a thickness of 210-230nm by adopting a high rotating speed, and the typical rotating speed is 4000-4250r/min and 29-40s. The negative photoresist ma-N2403 is mainly used, the exposure time is short, and the index meets the processing precision requirement.
Step 4: after the photoresist is coated on the surface of the substrate, the excessive moisture is required to be removed by pre-baking, so that the photoresist is formed into a film, and the effects of curing and releasing stress are achieved, thereby improving the adhesiveness between the photoresist and the substrate. In this step, the uniformity of the photoresist is also significantly improved, and the pre-baking condition is that the photoresist is baked on a hot plate at 90-100 ℃ for 90 seconds, and then naturally cooled after baking is completed.
Step 5: and the exposure operation is carried out, and an electron beam exposure machine is adopted, so that the wavelength of the electron beam is short, and the line width of the pattern is reduced to a great extent. The electron beam exposure is completed sequentially according to the patterns and the sequence in the mask pattern without manufacturing a mask plate. Since the exposure range of the electron gun is limited, the electron beam exposure partitions the mask pattern for exposure. The exposure here adopts a combination of a fixed stage and a movable stage to achieve the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, and the aperture size of an electron gun is generally 10 μm.
Step 6: and after the previous work is finished, performing post-baking. The post-bake is to react the photosensitive components in the photoresist more thoroughly and form a stable distribution, and its baking temperature is typically 10 ℃ higher than the pre-bake temperature, i.e.: baking on hot plate at 100-110deg.C for 5min, and naturally cooling.
Step 7: and (5) developing. Development is a critical step in creating a pattern in the photoresist on the surface of the master. The soluble areas in the photoresist are dissolved by the chemical developer leaving the visible window pattern on the surface of the wafer. The most common development method is soaking, followed by rinsing with deionized water and then spin-drying. The time and temperature of soaking are two very important control factors. Typically MaD developer is used, in which it is allowed to stand for 90s.
Step 8: and (5) checking. The quality of the fabricated lower waveguide was observed with a high magnification microscope. After the photoresist is patterned on the surface of the wafer, the photoresist is inspected in time to determine the quality of the photoresist pattern. The purpose of inspection has two aspects, namely, a silicon wafer with the quality problem of the photoresist is found in time, the process performance of the photoresist is inspected to meet the standard requirement, and if the colloid is determined to be defective, the colloid can be removed by photoresist removal, and the sample wafer is reworked. If the lithographic pattern is defective, it is fatal to the performance of the waveguide and therefore requires inspection prior to etching.
Step 9: etching. The width of the waveguide is generally a certain difference from the ideal width after development, and besides adjusting the exposure dose and development time, the waveguide can be solved by etching. The etching time is mainly determined by the etching speed and the etching depth, and the etching quality determines the verticality and the roughness of the side wall of the waveguide and determines the performance of the device. The etching here employs Inductively Coupled Plasma (ICP) with SF being selected as the reactant gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The power of the coil RF was 500W, the frequency was 13.56Mhz, the power of the substrate RF was 20W, the frequency was 13.56Mhz, the operating pressure was 1mTorr, the chamber temperature was typically controlled at 65℃and the etch rate was 1.83nm/s.
Step 10: an intermediate isolation layer. After etching, removing residual photoresist and reaction products by adopting an oxygen plasma photoresist removing method, and putting the photoresist and reaction products into an N-methyl pyrrolidone (NMP) solution with the temperature of 70 ℃ to shake and remove the residues. And after the residue is removed, covering a silicon dioxide isolation layer with the thickness of 200-220nm on the lower-layer waveguide by using a chemical vapor deposition (PECVD) method after the lower-layer waveguide is manufactured.
Step 11: and after the deposition of the middle isolation layer is finished, removing the protruding part of the middle isolation layer by using a chemical mechanical method.
Step 12: and (5) secondary spin coating. The process is used for manufacturing the upper layer waveguide. And coating photoresist on the middle isolation layer. The spin coating process comprises two stages with different rotation speeds, wherein a substrate is fixed on a vacuum objective table; then spreading the photoresist on the surface of the substrate at a low rotating speed, wherein the typical rotating speed is 1500-1750r/min for 3-5s; then, the photoresist is made to reach a thickness of 210-230nm by adopting a high rotating speed, and the typical rotating speed is 4000-4250r/min and 29-40s. The negative photoresist ma-N2403 is mainly used, the exposure time is short, and the index meets the processing precision requirement.
Step 13: secondary pre-baking: after the photoresist is coated on the middle isolation layer, pre-baking is needed to remove redundant water, so that the photoresist is formed into a film, and the effects of curing and releasing stress are achieved, thereby improving the adhesiveness of the photoresist and a substrate. In this step, the uniformity of the photoresist is also significantly improved, and a typical pre-bake condition is baking for 90s at 90-100 ℃ on a hot plate, and naturally cooling after baking is completed.
Step 14: and (5) secondary exposure. And the exposure operation is carried out, and an electron beam exposure machine is adopted, so that the wavelength of the electron beam is short, and the line width of the pattern is reduced to a great extent. The electron beam exposure is completed sequentially according to the patterns and the sequence in the mask pattern without manufacturing a mask plate. Since the exposure range of the electron gun is limited, the electron beam exposure partitions the mask pattern for exposure. The exposure here adopts a combination of a fixed stage and a movable stage to achieve the optimal effect. The main parameters of the pattern exposure are dose and scanning step size, the basic dose is about 70. Mu.C/cm 2 An acceleration voltage of 20kv is generally adopted when the equipment with the working step length of 10 μm is exposed, and the aperture size of an electron gun is generally 10 μm.
Step 15: and (5) secondary post-baking. And after the previous work is finished, performing post-baking. The post-bake is to react the photosensitive components in the photoresist more thoroughly and form a stable distribution, and its baking temperature is typically 10 ℃ higher than the pre-bake temperature, i.e.: baking on hot plate at 100-110deg.C for 5min, and naturally cooling.
Step 16: and (5) secondary development. Development is a critical step in creating a pattern in the photoresist on the surface of the master. The soluble areas in the photoresist are dissolved by the chemical developer leaving the visible window pattern on the surface of the wafer. The most common development method is soaking, followed by rinsing with deionized water and then spin-drying. The time and temperature of soaking are two very important control factors. Typically MaD developer is used, in which it is allowed to stand for 90s.
Step 17: and (5) secondary inspection. The quality of the fabricated upper layer waveguide was observed with a high magnification microscope. After the photoresist is patterned on the surface of the wafer, the photoresist is inspected in time to determine the quality of the photoresist pattern. The purpose of inspection has two aspects, namely, a silicon wafer with the quality problem of the photoresist is found in time, the process performance of the photoresist is inspected to meet the standard requirement, and if the colloid is determined to be defective, the colloid can be removed by photoresist removal, and the sample wafer is reworked. If the lithographic pattern is defective, it is fatal to the performance of the waveguide and therefore requires inspection prior to etching.
Step 18: and (5) secondary etching. The width of the waveguide is generally a certain difference from the ideal width after development, and besides adjusting the exposure dose and development time, the waveguide can be solved by etching. The etching time is mainly determined by the etching speed and the etching depth, and the etching quality determines the verticality and the roughness of the side wall of the waveguide and determines the performance of the device. The etching here employs Inductively Coupled Plasma (ICP) with SF being selected as the reactant gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The power of the coil RF was 500W, the frequency was 13.56Mhz, the power of the substrate RF was 20W, the frequency was 13.56Mhz, the operating pressure was 1mTorr, the chamber temperature was typically controlled at 65℃and the etch rate was 1.83nm/s.
Step 19: and (5) an upper cover layer. After the secondary etching is finished, removing residual photoresist and reaction products by adopting an oxygen plasma photoresist removing method, and putting the photoresist and reaction products into an N-methyl pyrrolidone (NMP) solution with the temperature of 70 ℃ to shake and remove the residues. And after the residues are removed, depositing a silicon dioxide coating layer with the thickness of 2-3 mu m on the upper layer waveguide by using a chemical vapor deposition method after the upper layer waveguide is manufactured.
Step 20: and after the deposition of the upper coating layer is finished, removing the part of the protruding cladding above the upper waveguide by using a chemical mechanical method.
Therefore, the three-dimensional multi-layer mode multiplexing and de-multiplexing device has the characteristics of easiness in implementation, mature process, good compatibility, high bandwidth and the like, so that the performance of a photon integrated device can be ensured, and a foundation is laid for realizing high-performance optical signal processing chips or devices in optical communication and photon systems.
Claims (5)
1. A three-dimensional multi-layer waveguide mode multiplexer and demultiplexer, comprising: the waveguide structure comprises a substrate layer (1), wherein a lower cladding layer (2) is arranged on the substrate layer, a lower waveguide (4) is arranged on the lower cladding layer (2), an intermediate isolation layer (6) is paved on the lower waveguide (4), an upper waveguide (3) is arranged on the intermediate isolation layer, an upper cover layer (5) is covered on the upper waveguide (3), any side boundary of the lower waveguide (4) is aligned with any side boundary of the upper waveguide (3), and the waveguide width center dislocation of the lower waveguide (4) and the upper waveguide (3) is larger than 0 and smaller than 5 mu m.
2. The three-dimensional multi-layer waveguide mode multiplexing and demultiplexing device according to claim 1, characterized in that the lower layer waveguide (4) and the upper layer waveguide (3) are left side boundary aligned.
3. The three-dimensional multi-layer waveguide mode multiplexing and demultiplexing device according to claim 1, characterized in that the lower layer waveguide (4) and the upper layer waveguide (3) have the same height and different widths.
4. The three-dimensional multi-layer waveguide mode multiplexing and demultiplexing device according to claim 1, characterized in that the lower layer waveguide (4) comprises a first main waveguide section (401), a second main waveguide section (402) and a third main waveguide section (403) for implementing different higher order mode multiplexing and demultiplexing; the upper layer waveguide (3) comprises a first input waveguide (301), a second input waveguide (302) and a third input waveguide (303); any side boundary of the first input waveguide (301) is aligned with any side boundary of the first main waveguide section (401), any side boundary of the second input waveguide (302) is aligned with any side boundary of the second main waveguide section (402), and any side boundary of the third input waveguide (303) is aligned with any side boundary of the third main waveguide section (403); the lower waveguides (4) are arranged in rows and the widths of the lower waveguides are gradually changed according to the arrangement sequence, and are connected by using tapered waveguides.
5. A method of fabricating a three-dimensional multi-layer waveguide mode multiplexer and demultiplexer as claimed in claim 1, comprising the steps of:
step 1: a silicon substrate is taken, the surface of the silicon substrate is treated, a silicon dioxide cladding layer with the thickness of 2-3 mu m is deposited on the surface of the silicon substrate by a chemical vapor deposition (PECVD), the cladding layer is a lower cladding layer, and the reaction gas for depositing silicon dioxide is Silane (SiH) 4 ) And nitric oxide (N) 2 O), in the deposition process, the temperature of the upper stage plate is 300 ℃, the temperature of the lower stage plate is 300 ℃, the power of a radio frequency source is 700W, the pressure of a cavity is 300mTorr, and N 2 O flow rate is 2000sccm, siH 4 The flow rate was 17sccm,
step 2: performing photoresist homogenizing lithography on the lower cladding, and spreading the photoresist on the surface of the chip at a low rotation speed of 1500-1750r/min for 3-5s; then volatilizing the photoresist at the high rotating speed to reach the ideal thickness of 210-230nm, washing off the redundant photoresist at the high rotating speed of 4000-4250r/min and 29-40s, using negative photoresist ma-N2403, having short exposure time and meeting the processing precision requirement,
step 3: carrying out photoetching, preparing a waveguide structure by utilizing photoetching and etching processes, wherein the photoetching equipment adopts EBL as exposure equipment, electron beam exposure is completed sequentially according to patterns and sequences in mask patterns without mask plate manufacture, and the exposure adopts a mode of combining a fixed platform and a movable platform to takeThe optimal effect is obtained, the pattern exposure parameters are dosage and scanning step length, and the dosage is 70 mu C/cm 2 The working step length is 10 mu m, the equipment adopts 20kv accelerating voltage when in exposure, the aperture size of the electron gun is 10 mu m,
step 4: etching adopts Inductively Coupled Plasma (ICP) technology, and SF is selected as reaction gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The flow rate of (2) was 4.9sccm, the power of the coil RF was 500W, the frequency was 13.56Mhz, the power of the substrate RF was 20W, the frequency was 13.56Mhz, the operating pressure was 1mTorr, the chamber temperature was controlled to 65℃and the etching rate was 1.83nm/s,
step 5: removing residual mask from etched sample wafer, depositing silicon dioxide intermediate isolation layer with thickness of 190-210nm, removing protruding portion of intermediate isolation layer by chemical mechanical method,
step 6: performing secondary photoresist homogenizing photoetching on the middle isolation layer, spreading the photoresist on the surface of the chip at a low rotating speed, wherein the speed of the low rotating speed is 1500-1750r/min for 3-5s; then volatilizing the photoresist at the high rotating speed to reach the ideal thickness of 210-230nm, washing off the redundant photoresist at the high rotating speed of 4000-4250r/min and 29-40s, using negative photoresist ma-N2403, having short exposure time and meeting the processing precision requirement,
step 7: performing secondary photoetching step, preparing waveguide structure by using photoetching and etching process, using EBL as exposure equipment, performing electron beam exposure without mask plate, sequentially completing pattern and sequence in mask pattern, and performing exposure by combining fixed platform and movable platform to obtain optimal effect, wherein pattern exposure parameters are dose and scanning step length, and dose is 70 μC/cm 2 The working step length is 10 mu m, the equipment adopts 20kv accelerating voltage when in exposure, the aperture size of the electron gun is 10 mu m,
step 8: the secondary etching adopts Inductively Coupled Plasma (ICP) technology, and the SF is selected by the reaction gas 6 And C 4 F 8 ，SF 6 10.7sccm, C 4 F 8 The power of the coil RF was 500W, the frequency was 13.56Mhz, and the power of the substrate RF was 20W at 4.9sccmThe frequency is 13.56Mhz, the working pressure is 1mTorr, the cavity temperature is controlled to 65 ℃, the etching speed is 1.83nm/s,
step 9: and removing residual mask, depositing a silicon dioxide upper covering layer with the thickness of 2-3 mu m on the sample wafer after the secondary etching, and removing the protruding part of the middle isolation layer by using a chemical mechanical method after the deposition is finished.
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