CN1087504C - High frequency static induction transistor having high output - Google Patents

Abstract

A concave static transistor with high breakdown voltage, comprising: an n-type channel region arranged in an n ⁺ -type drain region, a p ⁺ -type elongated gate region in the channel groove, and a gate region formed in the channel region Parallel n ⁺ -type elongated regions, each of which is disposed between the gate regions, and a p ⁺ -type guard ring region surrounding the gate regions in the channel region. The elongated gate region is coupled with the guard ring region on both sides, and the outermost elongated gate region is respectively coupled with the guard ring region in the longitudinal direction, so as to increase the breakdown voltage of the device. The gate and source contacts are arranged opposite to each other only in the guard ring region to reduce the parasitic capacitance between the gate-drain region and between the gate-source region.

Description

High Frequency Static Sense Transistor for High Output Power

The invention relates to a static induction transistor (SIT), in particular to a high-frequency concave-gate or side-gate static induction transistor with high output power.

Referring to Fig. 20, the prior art SIT will be described. Fig. 20 (A) shows surface gate type SIT, and it comprises, as drain region n ⁺ substrate 101, is arranged on the substrate 101 top as the epitaxial layer 102 of channel region, on the surface of n type epitaxial layer 102 forms n ⁺ source region 103 and p ⁺ gate region 104. According to this surface gate structure, the high frequency characteristics are improved by reducing the gate resistance. Surface-gate SITs operating at about 1 GHz have been provided. Since the P ⁺ gate region 104 with a diffusion depth of 2-3 μm or deeper is set, when the thickness of the n-type epitaxial layer 102 is 20 μm, a breakdown voltage of 200-300V may be obtained. Similarly, when the thickness of the n-type epitaxial layer 102 When it is 6μm, a breakdown voltage of 600V can be obtained.

A recess gate type and a side gate type SIT as shown in FIG. 20(B) and FIG. 20(C) have been proposed as structures for further improving high-frequency characteristics. In the recessed gate type SIT, grooves 105 are formed in n-type epitaxial layer 102 . A P ⁺ gate region 106 is formed on the bottom of the trench 105 . In the side gate type SIT, P ⁺ gate regions 108 are formed at both corners of the trench 107 formed in the n epitaxial layer 102 . Because the two SITs reduce the gate-source capacitance C _gs and the gate-drain capacitance C _gd compared with the surface gate SIT, the power gain almost rises to the upper limit of the UHF frequency band. In the case of a concave gate type SIT, the thickness of the epitaxial layer 102 is about 6-10 μm, the power gain at 1-3 GHz is 7-10 db, and the device may work at the maximum oscillation frequency f _max of several GHZ, the gain becomes 1 (0dB).

In order to improve high-frequency characteristics, gate-source capacitance C _gs and gate-drain capacitance C _gd should be reduced. To reduce C _gd , the diffusion depth Xj of the P ⁺ gate region 106 can be made shallow. Since C _gd increases inversely as the distance between the gate region and the drain region increases, the n epitaxial layer 102 can be made thicker in order to reduce C _gd . However, if the n-epitaxial layer 102 is made thick, the gain is reduced as a result due to the influence of the transit time of electrons from the source region to the drain region. Therefore, C _gd and f _max have a trade-off relationship with the thickness of the n-epitaxial layer 102 .

In order to increase the gate-drain breakdown voltage BV _gd , Xj can be increased. However, the distance between the gate and drain regions can be reduced to increase C _gd . That is to say, there is a trade-off relationship between BV _gd and C _gd and the diffusion thickness Xj of the P ⁺ gate region 106 . As mentioned above, high frequency characteristics have a great relationship with breakdown voltage. BV _gd is the reverse breakdown voltage of the Pn junction between the gate-drain region, thereby determining the maximum voltage (breakdown voltage) suitable for the drain region.

The BV _gd of the actual concave-gate SIT is lower than the theoretical breakdown voltage determined by the planar junction. Apply a voltage to the Pn junction between the gate and drain until it breaks down, and then observe the surface of the SIT with an infrared radiation microscope. It is found that the temperature increases at the outermost portion of the P ⁺ gate region 106. Therefore, the breakdown voltage of the spherical or cylindrical junction region created at the outermost portion instead of the planar junction region between the gate and drain regions decreases. (The part where the theoretical breakdown voltage is obtained) The breakdown voltage decreases.

Because the output power of the SIT increases in proportion to the drain voltage and the drain current, in order to realize a device with high frequency and high output power, the theoretical breakdown voltage determined by the thickness between the gate and drain regions is adopted, but the high frequency characteristics are not reduced, and the best design. However, the actual BV _gd is lower than the theoretical breakdown voltage. Therefore, in order to provide a concave grid SIT with high frequency and high output power, the BV _gd should be increased to the calculated theoretical breakdown voltage. The same process is performed for the side gate type SIT.

Next, the gate and source structures in the SIT will be briefly described with reference to FIG. 21(A). In the area surrounded by a dotted line (element area 120), the P ⁺ gate area and the n ⁺ source area are arranged in parallel, and the gate 108 and the source 109 are respectively arranged on the P ⁺ gate area and the n ⁺ source area. Aluminum (A1) gate contacts 110 and aluminum (A1) source contacts 111 are formed on the outermost element region 120 . The connection region 112 between the gate contact 110 and each gate electrode 108 is indicated by an upper right slash, and the connection portion between the source contact 111 and each source 109 is indicated by a lower left slash. As shown in FIG. 21(B), an oxide film 114 is formed on the epitaxial layer 102, and a gate contact 11 is provided on the oxide film 114. As shown in FIG. Also, although not shown, on the oxide film 114, the source contact 111 is also formed. In the above contact structure, the breakdown voltage between the gate and drain regions is about 200-300V although it depends on the thickness and quality of the oxide layer below each Al contact.

Also, the SIT is constituted by one element region. Because the leakage current is proportional to the entire source length, the entire source length can be increased by increasing the area of the device region 120 to achieve an increase in the source current. However, when the area of the device region 120 is increased, the resistance and inductance of the source and gate regions will be increased; especially when SIT is used in the microwave band, the resistance and inductance greatly affect the operating conditions of the device. Therefore, there is a certain limit to increasing the area of the element region.

An object of the present invention is to provide a recess gate or side gate type SIT which has a high breakdown voltage gate-drain junction and which has improved high frequency characteristics.

Another object of the present invention is to provide a high-frequency concave-gate or side-gate type SIT having a large output power characteristic.

Another object of the present invention is to provide a recess gate or side gate type SIT, which can reduce gate-drain and gate-source parasitic capacitance.

Still another object of the present invention is to provide a recess gate or side gate type SIT which allows a large current to pass and reduces inductance.

The objects and advantages of the present invention can be achieved by the structure described below.

According to a scheme of the present invention, a concave gate or side gate type static induction transistor is provided, which includes a drain region of the first conductivity type, a channel region with the first conductivity type arranged on the drain region, and a plurality of grooves for each groove are all formed in the channel region, a plurality of source regions of the first conductivity type are each arranged in the channel region so as to be arranged between the grooves, and a plurality of gate regions of the second conductivity type are each arranged in the The bottom of each groove, the gate region and the source region arranged parallel to each other, and the guard ring of the second conductivity type arranged in the channel region so as to surround the gate region. In such a structure, the guard ring is arranged such that the outermost gate regions respectively overlap one side of the guard ring in the longitudinal direction, and each gate region is coupled to the guard ring at both sides thereof.

According to another aspect of the present invention, the gate and source electrodes are arranged so as to face each other only in the guard ring region.

The novel and distinctive features of the invention are set forth in the claims appended to this application. The invention itself, together with objects and advantages thereof, may be better understood with reference to the following description of the accompanying drawings.

Fig. 1 (A) is the plan view that schematically represents the first embodiment of SIT of the present invention;

Figure 1(B) is a partially enlarged view of the part of Figure 1(A) surrounded by a circle;

Fig. 2 is a sectional view taken along line II-II' of Fig. 1(B);

3 is a graph showing the relationship between the width L1 and the breakdown voltage between the gate region and the drain region;

FIG. 4 is a graph showing frequency characteristics of SITS power gain;

Fig. 5 is a sectional view schematically showing the second embodiment of the SIT according to the present invention;

Fig. 6 is a sectional view schematically showing the third embodiment of the SIT according to the present invention;

7 to 12 are sectional views showing a process for manufacturing a SIT according to the present invention;

Fig. 13 is a plan view schematically showing the fourth embodiment of the SIT according to the present invention;

Fig. 14 is a sectional view taken along line IVX-IVX' of Fig. 13;

Fig. 15 (A) is a sectional view taken along the line XVA-XVA' of Fig. 13;

Fig. 15 (B) is a cross-sectional view taken along XVB-XVB' of Fig. 13;

Fig. 16(A) is a cutaway sectional view when the contact point extends to the surface of the channel region;

Figure 16(B) is a partial cross-sectional view when the contact point extends to the floating region;

Figure 17 is a cross-sectional view of a SIT with an n ⁺ region as a cutting region;

Fig. 18 is a plan view schematically showing a fifth embodiment having two element regions according to the present invention;

Fig. 19 is a schematic plan view of a SIT with four element areas;

Fig. 20 (A) to (C) is the sectional view that schematically shows known SITS;

FIG. 21(A) is a plan view schematically showing a known SIT;

Fig. 21(B) is a sectional view taken along XXI-XXI' of Fig. 21(A).

Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment of the present invention will be described.

As shown in Figure 1 (A), the concave gate type SIT includes many elongated P ⁺ gate regions 16 (including 16 and 16b), many elongated n ⁺ source regions 18, surrounding the P ⁺ gate region 16 (surrounded by dotted lines part) P ⁺ guard ring region 13 like a belt. The P ⁺ gate region 16 and the n ⁺ source region 18 are arranged such that they are substantially perpendicular to the long sides of the P ⁺ guard ring region 13 and parallel to the short sides of the guard ring region 13 .

As shown in FIG. 1(B), the P ⁺ gate region 16a disposed on the outermost (leftmost) side is connected to the P ⁺ guard ring region 13 in the longitudinal direction, and each P ⁺ gate region 16a disposed between the n ⁺ source regions 18 Gate region 16b is connected to P ⁺ guard ring region 13 at an edge or end. The corners of the P ⁺ guard ring region 13 are rounded to reduce the electric field intensity. Moreover, in order to prevent the gate-source breakdown voltage BV _gs from decreasing, each n ⁺ source region 18 is required to satisfy L ₂ ≥W _gs . In the figure, _L1 represents the width of the P ⁺ guard ring region 13, _L2 represents the distance between the edge of the n ⁺ source region 18 and the P ⁺ guard ring region 13, W _gs represents the n source region 18 and the P ⁺ gate region 16 distances between.

Next, the recess gate type SIT will be described in more detail with reference to FIG. 2, which is a sectional view taken along line II-II' of FIG. 1(B). The concave gate type SIT includes n ⁺ drain region (n ⁺ substrate) 11, n epitaxial layer 12, which is a high-resistance channel region arranged on n ⁺ drain region 11, grooves 14a and 14b are formed in n epitaxial layer 12, The edge film 15 is formed on the n epitaxial layer 12, the P ⁺ gate regions 16a and 16b are formed at the bottom of the grooves 14a and 14b, and the P ⁺ guard ring region 13 is formed in the n epitaxial layer 12 so as to be compatible with the P ⁺ gate region 16a. The peripheral part is connected, and the n ⁺ source region 18 set on the n epitaxial layer 12, the gate electrode 19 and the source electrode 20 respectively set on the P ⁺ gate region 16 and the n ⁺ source region 18, and the drain electrode 20 set on the n ⁺ drain region 11 Pole 21. As the insulating film 15, a SiO ₂ film, a SiN film, a PSG film, or a composite film of these can be utilized.

In FIG. 2, _W1 represents the thickness of the n epitaxial layer 12, _W2 represents the distance between the P ⁺ gate region 16 and the n ⁺ drain region 11, and _W3 represents the distance between the P ⁺ guard ring region 13 and the n ⁺ drain region 11 Xj represents the diffusion depth of the P ⁺ guard ring region 13, Rj represents the curvature radius of the P ⁺ guard ring region 13, and R is about 80% of Xj.

For example, assuming that W ₁ is 9 μm, the depth of groove 14 is 1-1.5 μm, and the diffusion depth of P ⁺ gate region 16 is about 0.5 μm. For a conventional device, without the P ⁺ guard ring region, BV _gd is about 50-60V. On the contrary, for the device of the present invention, the P ⁺ guard ring region 13 is set, its _L1 is 8-13 μm, and Xj is about 2 μm, then BV _gd becomes 120-140V; it is more than twice the relevant parameter value of the conventional device .

In the above structure, the transition region thickness _W2 between n ⁺ drain region 11 and n epitaxial layer 12 is considered to be about 7 µm. In this case, the theoretical breakdown voltage determined by the planar junction region of p ⁺ gate region 16 is about 156V. The structure according to the invention with the P ⁺ guard ring 13 can provide values close to 90% of the theoretical breakdown voltage.

Next, the width L ₁ of the P ⁺ guard ring region 13 is described. If the P ⁺ guard ring region 13 is set in the SIT, a parasitic capacitance C _gd ' will be generated between the P ⁺ guard ring 13 and the n ⁺ drain region 11, unless C _g is between the P ⁺ gate region 16 and the n ⁺ drain region 11 The capacitor C _gd is sufficiently small, otherwise the high-frequency characteristics will be degraded, thereby reducing the power gain. So C _gd ' must be reduced. And to reduce L ₁ as much as possible. However, if L ₁ is too short, the breakdown voltage BV _gd is lowered because the breakdown voltage is determined by the columnar junction region disposed on the periphery of the P ⁺ guard ring region 13 . Therefore, it is necessary to determine the width L ₁ of the P ⁺ guard ring region 13 by considering the relationship between L ₁ and BV _gd .

The impurity concentration of guard ring region 13 may be equal to or less than the impurity concentration of P ⁺ gate regions 16a and 16b. If the impurity concentration of the guard ring region 13 is lower than that of the P ⁺ gate regions 16a, 16b, the depletion layer extends to the P ⁺ guard ring region 13, further increasing breakdown voltage and reducing parasitic capacitance.

Though, in Fig. 1 (A), do not represent grid and source contact point, but, the gate contact point that is connected with an edge of many elongated P ⁺ gate regions 16, and the n ⁺ source region 1 of many elongate An edge-connected source contact is provided on the n epitaxial layer 12 with the P ⁺ guard ring region 13 by using an insulating film so that they are opposed to each other.

Figure 3 shows the relationship between the P ⁺ guard ring width _L1 and the gate-drain breakdown voltage BV _gd in a SIT with a _W1 of 9 μm and a groove 14 depth of 1-1.5 μm, specifying the P ⁺ gate 16 diffusion depth is about 0.5 μm, and Xj is 2 μm. According to FIG. 3 , when L ₁ is about 8 μm or more, BV _gd is saturated. When L ₁ is above 8 μm, the depletion layer extends to the drain region 11, and exceeds the distance W ₂ (approximately 7-7.5 μm) from the P ⁺ gate region 16 to the n ⁺ drain region 11, thereby reducing the surface electric field intensity . This means that the breakdown voltage _BVgd is determined by the planar junction portion of the P ⁺ gate region 16 in the device. Therefore, in order to obtain a predetermined breakdown voltage and simultaneously reduce the parasitic capacitance C _gd ′, it is required that the width L ₁ of the P ⁺ guard ring 13 is almost equal to or slightly larger than W ₂ .

Figure 4 shows the relationship between power gain and frequency, which is calculated by measuring the S-parameters of a concave-grid SIT with 100 elongated source regions in parallel (each source length is 120nμm and the total source length is 1.2cm). The comparison between the SIT of the present invention having L ₁ defined as large at 8 µm and the conventional SIT without the guard ring structure is shown below. The bias conditions are as follows: (the SIT of the present invention has a P ⁺ guard ring, has a large BV _gd , and V _ds is 50V, which is twice that of the conventional SIT) bias condition Vds(V) Id(mA) Vgs(V) SIT of the present invention 50 50 -3.17 Conventional SIT 25 50 -4.45

As shown in Fig. 4, for the most stable gain, the gain is reduced by 0.5db in the inventive SIT due to _Cgd '. However, for the most useful gain, the power gain of the SIT of the present invention is almost equal to that of the conventional SIT, and at some frequencies is greater than that of the conventional SIT, because in addition to C _gd and C _gd ', also affected by The effect of inductance. The SIT breakdown voltage according to the present invention can be increased to more than 2 times the conventional SIT breakdown voltage without degrading the frequency characteristics. This means that the permitted direct current (DC) input of the SIT may be doubled, thus doubling the output power of the invention compared to a SIT with the same source length.

Next, referring to Fig. 5, a second embodiment of the present invention will be described. Parts similar to those in Fig. 2 are denoted by the same reference numerals. P ⁺ floating region 22 has an impurity concentration similar to that of P ⁺ guard ring region 13 formed in n epitaxial layer 12 such that P ⁺ floating region 22 surrounds ^{P + guard} ring region 13 . The P ⁺ floating region 22 can be set 2 times or 3 times, so as to obtain a higher breakdown voltage.

FIG. 6 shows a third embodiment of the present invention in which an n ⁺ region 23 is provided around a p ⁺ guard ring region 13 . It prevents excessive extension of the depletion layer extending from guard ring region 13 and is used as a cutting region along line AA'. When the wafer is diced according to the n ⁺ region 23, it is possible to prevent unintended and increased leakage current. Preferably, the diffusion depth of the n ⁺ region 23 is at least deeper than that of the P ⁺ guard ring region 13 and can reach the n ⁺ drain region 11 . P ⁺ floating region 22 may be provided around guard ring region 13, and n ⁺ region 23 may be provided therearound.

Referring to Fig. 7 to Fig. 12, describe a kind of method of manufacturing SIT of the present invention, it shows the sectional view along line II-II' of Fig. 1 (B).

First, prepare an n ⁺ substrate 11 as a drain region, which is a (100) or (111) plane, and has an impurity concentration of approximately 1×10 ¹⁸ to 1×10 ¹⁹ cm ⁻³ , which is hereinafter referred to as an n ⁺ drain region . A high-resistance n-type epitaxial layer 12 is grown on the n ⁺ drain region 11 by using SiCl ₄ and H ₂ by a vapor phase growth method. The impurity concentration of n epitaxial layer 12 is 1×10 ¹³ cm ⁻³ or less or 1×10 ¹³ to 1×10 ¹⁵ cm ⁻³ . In order to obtain just pinch-off characteristics, the impurity concentration in the lower part of the n-epitaxial layer 1 adjacent to the substrate 11 is 1×10 ¹³ cm ⁻³ , and the impurity concentration in the upper part of the n-epitaxial layer 2-3 μm down from the surface is 5×10 ¹⁴ to 1×10 ¹⁵ cm ^-3 . By design, n-epitaxial layer 12 has a uniform or non-uniform impurity concentration distribution. Using SiO ₂ etc. (not shown) as a mask (Fig. 7, form a P ⁺ guard ring region 13 in the n epitaxial layer 12 by ion implantation and other methods, and its impurity concentration is 1×10 ¹⁷ to 1×10 ²⁰ cm ^-3 .

Next, utilize SiO ₂ film (not shown) as mask, by RIE (reactive ion etching method, in n epitaxial layer 12, form many elongated grooves 14a and 14b as concave grid. Form outermost edge groove 14a, in vertical direction Partially overlap the P ⁺ guard ring region 13 to form a groove 14b, overlapping the P ⁺ guard ring region 13 on both sides (not shown). The grooves 14a and 14b are 2 μm and 1 μm wide and 1-1.5 μm deep, respectively. Groove 14a and groove 14b With an interval of 3-7 μm, RIE utilizes a mixed plasma of SF6 and _O2 gas (Fig. 8).

Then, by oxidizing the n-epitaxial layer 12 in water vapor, an insulating film 15 is formed, for example, a thick oxide film having a thickness of about 0.5-1 [mu]m. RIE uses CF ₄ or a mixed gas of CF ₄ and CHF ₃ to selectively etch the insulating film 15 to expose the n epitaxial layer 12 from the bottom of the groove 14 a and the groove 14 b. Next, boron diffusion and ion implantation are performed on the exposed bottoms of trenches 14a and 14b to provide P ⁺ gate regions 16a and 16b with an impurity concentration of 1×10 ¹⁸ to 1×10 ²⁰ cm ^-3 . In this process, The P ⁺ gate region 16a is connected to the P ⁺ guard ring region 13 . Likewise, the P ⁺ gate region 16b is connected to the P ⁺ guard ring region 13 on both sides (not shown). The diffusion depth of the P ⁺ gate region 16 is about 0.5 μm (FIG. 9).

Next, a mask pattern of a material such as photoresist is formed on the surface of the substrate, and the insulating film 15 is selectively removed by using a method such as RIE to expose the n-type epitaxial layer 12 ( FIG. 10 ). Phosphorous or arsenic ions are implanted into extended n epitaxial layer 12 to provide n ⁺ source regions 18 therein. Thereafter, the mask pattern 17 is removed. If SiO ₂ etc. are used as the ^mask pattern 17, the n ⁺ source region 18 can also be formed by diffusing the n-type impurities contained in the ^polysilicon layer, (Fig. 11). 18, n ⁺ drain region 11 forms gate electrode 19, source electrode 20, and drain electrode 21, (FIG. 12).

Next, a fourth embodiment of the present invention will be described with reference to Figs. 13-17.

As shown in Figure 13, the concave gate type SIT includes many elongated P ⁺ gate regions 37 (including 37a and 37b), many elongated source regions 39, and a rectangular P ⁺ guard ring region 33, which surrounds the P ⁺ gate region 37 (surrounded by dotted lines in the figure), the P ⁺ floating region 34 located on the periphery of the P ⁺ guard ring region 33, the gate electrode wiring layer 40 is arranged on the P ⁺ gate region 37, and is connected to each other on the P ⁺ guard ring region 33 , the source electrode wiring layer 41 is arranged on the n ⁺ source region 39, interconnected on the P ⁺ guard ring region 33, the gate contact point (soldering point) 43 is connected to the gate electrode wiring layer 40, and the source contact point (soldering point) 44 is connected to the The source electrode wiring layer 41 is connected. In this case, gate and source contacts 43 and 44 are provided in the P ⁺ guard ring region 33 .

As apparent from FIG. 13 , the gate electrode wiring layer 40 is indicated by left oblique lines, and the source electrode wiring layer 41 is indicated by right oblique lines. For example, boron-doped polysilicon is used for the gate and source electrode wiring layers 40 and 41, and metal such as Al or Al-Si is used for the gate and source contacts 43 and 44.

P ⁺ gate regions 37 and n ⁺ source regions 39 are alternately arranged in parallel. The P ⁺ gate region 37a disposed on the outermost side is connected to the P ⁺ guard ring region 33 in the longitudinal direction, and each P ⁺ gate region 37b sandwiched between the n ⁺ source regions 39 is connected to the P ⁺ guard ring 33 on both sides. The corners of the P ⁺ guard ring region 33 are rounded so that the electric field intensity is reduced, the opposite two long sides of the P ⁺ gate region 37 and the n ⁺ source region 39 and the P ⁺ guard ring region 33 are perpendicular to each other, and are connected to the gate and the source contact The centerlines of 43 and 44 are symmetrical to each other. The gate and source electrode wiring layers 40 and 41 have a finger electrode structure.

The cross section of the recess gate type SIT will be described with reference to FIG. 14, which is a cross section taken along line IVX-IVX' in FIG. The recessed gate type SIT includes an n ⁺ drain region (n ⁺ substrate) 31, an n epitaxial layer 32 disposed in a high-resistance channel region above the n ⁺ drain region 31, grooves 35a and 35 formed in the n epitaxial layer 32 An insulating film 36 is formed on the n epitaxial layer 32, P ⁺ gate regions 37a and 37b are formed on the n epitaxial layer 32 from the bottom of the grooves 35a and 35b, and a P ⁺ guard ring region 33 is formed in the n epitaxial layer 32, so that in the vertical direction Make it connected to the peripheral part of the P ⁺ gate region 37, form the P ⁺ floating region 34 in the n epitaxial layer 32, set the source region 39 on the n epitaxial layer 32, and set the P ⁺ gate region 37 and the n ⁺ source region 39 Gate and source electrode wiring layers 40 and 41 are respectively deposited on it, and a drain electrode 42 is provided on the n ⁺ drain region 31 . As the insulating film 36, a _SiO2 film, a SiN film, a PSG film, a polyamide film, or a composite film of these is used.

As shown in FIG. 15(A), the P ⁺ gate region 37b and the P ⁺ guard region 33 are connected to each other. Each gate electrode wiring layer 40 is arranged on the P ⁺ gate region 37b, and extends to the P ⁺ guard ring region 33 through the insulating film 36, and the gate contact point 43 is arranged on the gate electrode wiring layer 40 above the P ⁺ guard ring region 33 above. As shown in FIG. 15(B), each source electrode wiring layer 41 provided on the n ⁺ source region 39 extends to the P ⁺ guard ring region 33 through the insulating film 36, and the source contact 44 is formed in the P ⁺ guard ring region 33 above the source electrode wiring 41 .

Gate and source contacts 43 and 44 are deposited on P ⁺ guard ring 33 only, as described above. As shown in FIG. 16(A), if the gate electrode contact 43' extends to the portion between the P ⁺ guard ring region 33 and the P ⁺ floating region 34, the breakdown voltage is lowered at the circle portion A. As shown in FIG. 16(B), if the contact point 43″ reaches or exceeds the P ⁺ floating region 34, the gate-drain breakdown voltage BV _gd is reduced, and the gate-drain capacitance C _gd is increased, thus reducing the Power gain. In addition, a parasitic MOS transistor including P ⁺ guard ring region 33, n epitaxial layer 32 and P ⁺ floating region 34 is produced. Therefore, if the gate-drain breakdown voltage BV _gd is, for example, about 600V, it decreases with time to about 300 V. Therefore, gate and source contacts 43 need to be provided only on the P ⁺ guard ring region 33 .

Moreover, because the outermost part of the P ⁺ gate region 37a is connected to the P ⁺ guard region 33 in the vertical direction, the gate-to-drain breakdown voltage BV _gd is determined by the planar junction part of the P ⁺ gate region 37, which can enhance the BV _gd to almost a theoretical breakdown voltage. However, if the gate-source contacts 43 and 44 are located on the outermost edge of the P ⁺ guard ring region 33, as described above, the breakdown voltage will be reduced. Therefore, if it is desired to increase the breakdown voltage of the SIT, the P ⁺ guard ring region 33 must be provided, and the gate and source contacts 43 and 44 are only provided on the P ⁺ guard ring region 33 .

For example, when the epitaxial layer 32 is 35-55 μm thick, the grooves 35 are 1-1.5 μm deep, and the distance between them is 7-10 μm, the P ⁺ guard ring region 33 in the mask layer is 30-50 μm wide, and the P ⁺ guard ring region 3 diffusion depth is about 5 μm, the concave gate SIT has a gate-drain breakdown voltage BV _gd of about 300-600V, a power gain of 20-25db at 10MHZ, and a power gain of 10-15db at 100MHZ.

Also, as shown in FIG. 17 , n ⁺ region 45 may be provided on the periphery of P ⁺ floating region 34 . When the wafer is diced along the line BB', it is possible to prevent the leakage current from being generated and increased. Preferably, at least the n ⁺ region is diffused deeper than the p ⁺ guard ring region 33 depth.

Next, a fifth embodiment of the present invention will be described.

FIG. 18 shows a SIT, which includes two units 5a and 50b connected in parallel, each unit having a gate and a source, etc., as shown in FIG. 13 . The details of the cells 50a and 50b in FIG. 18 are the same as those in FIG. 13 and are omitted. The P ⁺ guard ring region 33 is continuously arranged so as to define the rectangular cells 50a and 50b. The connected P ⁺ guard ring region 331 .

The source contact 44a of the cell 50a and the source electrode contact 44b of the cell 50b are located almost in the center of the two outer long sides of the P ⁺ guard ring region 33 . Gate contact 43, which is connected to the gate regions of cells 50a and 50b, is in-line (aligned) with source contacts 44a and 44b, and is disposed over common P ⁺ guard ring region 331. As shown in FIG. 18, in each cell, the opposite long sides of the P+ gate region and the n ⁺ source region and the P ⁺ guard ring region 33 are perpendicular to each other, and relative to the center line of the gate and source contact points 43, 44a, 44b is symmetrical. The area of the P ⁺ guard ring region 33 for setting the gate and source contacts 43, 44a, 44b is increased compared to its other parts

Figure 19 shows a SIT comprising 4 parallel units 50a-50d. In this case, as shown in FIG. 18, a rectangular P ⁺ guard ring region 33 is provided so as to define cells 50a to 50d. Source contact 44 and gate contact 43 are provided alternately only on P ⁺ guard ring region 33 .

Thus, by providing gate and source contacts 43 and 44 above the P ⁺ gate guard region 33 having a common portion, a large number of cells 50 can be easily connected in parallel. Considering the current capacity and resistance, etc., two or more contact points can be set in each guard ring area. The P ⁺ guard ring region 33 below the contact has the required structure. Since the channel has high resistance, it is easy to be absorbed in the cell (digestion).

When using SIT at VHF or UHF higher than HF band, the effect of source and gate inductance cannot be ignored. However, a device comprising several small area cells 50 in parallel can reduce undesirable inductance compared to a device structure with only one large area cell. And such devices may operate consistently.

Using processes similar to those shown in Figs. 7-12, it is possible to manufacture the devices shown in the fourth and fifth embodiments.

Although, the recess gate type SIT has been described, similar descriptions apply to the side gate type SIT. Needless to say, the present invention is applicable not only to SIT made of Si but also to compound semiconductors (fabricated devices) made of GaAs, InP, etc.

According to the present invention, in the recess gate or side gate type SIT, a guard ring region is provided around the gate region, thereby significantly increasing the breakdown voltage of the gate-drain junction. With the SIT of the present invention, the voltage applied between the drain and the source can be made more than twice as compared with the conventional SIT without degrading high-frequency characteristics, and a SIT with high output power is provided. The P ⁺ guard ring region is set so as to be coupled with the outermost part of the P ⁺ gate region, and the gate and source contacts are provided only in the P ⁺ guard ring region. Thus, the breakdown voltage can be improved and SIT with excellent high-frequency characteristics can be provided . Also, it is easy to provide small-area cells connected in parallel, thereby increasing the overall source length and reducing inductance.

Those skilled in the art should further understand that the foregoing descriptions are preferred embodiments of the disclosed devices, and various changes and modifications can be made in the present invention without departing from the spirit and scope of the present invention.

Claims (14)

1. A static sensing transistor comprising, a drain region having a first conductivity type; a channel region of the first conductivity type is disposed above the drain region; a plurality of trenches, each trench formed in said channel region; a plurality of source regions, having said first conductivity type, each source region disposed in said channel region so as to be disposed between said plurality of trenches; A plurality of gate regions having a second conductivity type, each gate region is disposed at the bottom of the groove, wherein the plurality of gate regions and the plurality of source regions are arranged parallel to each other; A guard ring region, having the second conductivity type, is arranged in the channel region, and the guard ring region is arranged around the plurality of gate regions, so that the outermost gate regions of the plurality of gate regions are respectively connected to the plurality of gate regions. One side of the guard ring region overlaps, and each of the plurality of gate regions is connected to the guard ring region on two sides. 2. The static induction transistor according to claim 1, wherein said guard ring has a width equal to or greater than a distance between each of said plurality of gate regions and said drain region. 3. The static induction transistor according to claim 1, wherein a floating region having said second conductivity type is provided in said channel region so as to surround said guard ring region. 4. The static induction transistor according to claim 1, wherein a semiconductor region having said first conductivity type is provided in said channel region so as to surround said guard ring region. 5. The static induction transistor according to claim 4, wherein said semiconductor region is used as a cutting region. 6. The static induction transistor according to claim 1, wherein source and gate electrodes having a finger structure are provided in said channel region using an insulating film. 7. A static sensing transistor comprising: a drain region having a first conductivity type; disposing a channel region above said drain region, which has said first conductivity type; a plurality of trenches, each of which is formed in the channel region and has a bottom; a plurality of source regions having said first conductivity type, each source region being disposed above said channel region so as to be disposed between said plurality of grooves, wherein said plurality of grooves and said plurality of grooves are arranged parallel to each other many source regions; a plurality of gate regions, having a second conductivity type, each gate region is disposed on said bottom; The guard ring region disposed in the channel region has the second conductivity type, the guard ring region is arranged to surround the plurality of gate regions, so that the outermost gate regions of the plurality of gate regions are respectively connected to the One side of the guard ring region overlaps each other, and each gate region in the plurality of gate regions is coupled to the plurality of gate regions on both sides thereof; source electrodes, wherein each source electrode is disposed on a corresponding one of the plurality of source regions; gate electrodes, wherein each gate electrode is disposed on a corresponding one of the gate regions; The first and second contact points are provided in the guard ring region with an insulating film, and are respectively connected to the source electrode and the gate electrode. 8. The static induction transistor according to claim 7, wherein each source region of said plurality of source regions and each gate region of said plurality of gate regions are arranged to cross each other. 9. The static sensing transistor according to claim 7, wherein said first and second contact points are arranged opposite to each other. 10. The static sensing transistor according to claim 7, wherein said plurality of gate regions and said plurality of source regions are symmetrical with respect to a line connecting said first and second contact points. 11. A static sensing transistor comprising: a drain region having a first conductivity type; a channel region disposed above the drain region, having the first conductivity type; a guard ring region having a second conductivity type disposed in said channel region so as to define first and second regions separated by a common region of said guard ring region; a plurality of grooves, wherein each groove is formed in said each of said first and second regions and has a bottom; a plurality of source regions having said first conductivity type, each source region being disposed on said each of said first and second regions so as to be disposed between said plurality of grooves, wherein said a plurality of trenches and said plurality of source regions are arranged parallel to each other; a plurality of gate regions, having a second conductivity type, each gate region is disposed on said bottom; source electrodes, wherein each source electrode is disposed over a corresponding one of the plurality of source regions; gate electrodes, wherein each gate electrode is disposed over a corresponding one of the plurality of gate regions; first and second contact points disposed above said guard ring region with an insulating film and connected to said source electrode; A third contact is provided on said common portion of said guard ring region by said insulating film, and is connected to said gate electrode. 12. A static sensing transistor according to claim 11, wherein said first, second and third contacts are aligned (aligned). 13. The static induction transistor of claim 11, wherein said plurality of source regions and said plurality of gate regions are perpendicular to one side of said guard ring region. 14. The static sensing transistor of claim 11 wherein said first and second regions are symmetrical with respect to a common portion of said guard ring region.

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