CN108735757B

CN108735757B - Method of making embedded non-volatile memory

Info

Publication number: CN108735757B
Application number: CN201710340214.7A
Authority: CN
Inventors: 李皞明; 林胜豪; 郑子铭
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2017-04-25
Filing date: 2017-05-15
Publication date: 2021-04-13
Anticipated expiration: 2037-05-15
Also published as: CN108735757A

Abstract

The present invention discloses a method for manufacturing an embedded non-volatile memory. A semiconductor substrate is first provided, having a fin-shaped structure protruding from an insulating layer. A charge storage layer is then formed, spanning the fin-shaped structure. An interlayer dielectric layer is then deposited on the semiconductor substrate. The interlayer dielectric layer is polished until the upper surface of the charge storage layer is exposed. The charge storage layer is then etched, and the charge storage layer is then cut into separate charge storage structures. A high dielectric constant dielectric layer is formed on the charge storage structure, and a word line is then formed on the high dielectric constant dielectric layer.

Description

Method for manufacturing embedded non-volatile memory

Technical Field

The present invention relates to the field of semiconductor fabrication processes, and more particularly, to a method for fabricating an embedded non-volatile memory that is compatible with fin field effect transistor (FinFET) fabrication processes.

Background

As semiconductor logic fabrication processes have advanced to nanotechnology nodes, the structure of transistor devices has also evolved into three-dimensional structures such as fin field effect transistors (finfets) or tri-gate transistors (tri-gates) for increasing the driving current and performance of the transistor devices.

Furthermore, as mobile devices become more popular, the market for integrated circuit chips with embedded flash memory will become more demanding. Accordingly, the present applicant has devised a method of fabricating an embedded non-volatile memory that is compatible with fin field effect transistor (FinFET) fabrication processes.

Disclosure of Invention

The present invention is directed to a method for fabricating an embedded non-volatile memory, which overcomes the disadvantages and drawbacks of the prior art.

According to one embodiment of the invention, a method for manufacturing an embedded non-volatile memory is disclosed. First, a semiconductor substrate having a fin structure protruding from an insulating layer is provided. A charge storage layer is formed across the fin structure. An interlevel dielectric layer is then deposited over the semiconductor substrate. And grinding the interlayer dielectric layer until the upper surface of the charge storage layer is exposed. The charge storage layer is then etched and cut into separate charge storage structures. A high-k dielectric layer is formed over the charge storage structure, and word lines are formed over the high-k dielectric layer.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. The preferred embodiment and drawings are, however, to be considered in all respects as illustrative and not restrictive.

Drawings

Fig. 1 to 5 are schematic diagrams illustrating a method for fabricating an embedded non-volatile memory according to an embodiment of the invention;

fig. 6 is a perspective view of another embodiment of the present invention, illustrating an etch stop layer formed on the dummy gate layer and a sacrificial cap layer formed on the etch stop layer.

Description of the main elements

10 semiconductor substrate

11. 12 fin structure

20 insulating layer

22 dummy gate layer

22a upper surface

22' Charge storage Structure

30 interlayer dielectric layer

40 high dielectric constant dielectric layer

50 photoresist pattern

50a straight line type opening

60 metal layer

60a grid

60b character line

101 logic circuit area

102 embedded non-volatile memory area

110 gate dielectric layer

120 tunneling dielectric layer

220 concave groove

230 groove

t predetermined thickness

M₁、M₂Embedded non-volatile memory

Detailed Description

In the following detailed description of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments in which the invention may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Before further description of the preferred embodiments, reference will now be made to specific terms used throughout.

The term "etching" is used herein generally to describe a process of making a patterned material such that at least a portion of the material is left behind after the etching is completed. For example, it should be understood that a method of etching silicon includes patterning a masking layer (e.g., photoresist or hardmask) over silicon, and then removing the silicon from areas not protected by the masking layer. Thus, at the completion of the etching process, silicon will remain in the areas protected by the mask.

However, in another example, etching may also refer to a method that does not use a mask, but leaves at least a portion of the material after the etching process is complete. The above description is used to distinguish between "etching" and "removing". When a material is "etched," at least a portion of the material is retained after the process is completed. In contrast, when material is "removed," substantially all of the material is removed in the process. However, in some embodiments, "removing" is considered a broad term and may include etching.

The terms "forming," "depositing," or the term "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. Such terminology is intended to describe any possible layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

According to various embodiments, for example, the deposition may be performed in any suitable known manner. For example, deposition may include any process of growing, plating, or transferring material onto a substrate. Some well-known techniques include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), electrochemical deposition (ECD), Molecular Beam Epitaxy (MBE), Atomic Layer Deposition (ALD), plasma enhanced CVD (pecvd), and the like.

The "substrate" as described throughout, most commonly should be a silicon substrate. However, the substrate may be any semiconductor material, such as germanium, gallium arsenide, indium phosphide, and the like. In other embodiments, the substrate may be non-conductive, such as a glass or sapphire wafer.

Fig. 1 to 5 are schematic diagrams illustrating a method for fabricating an embedded non-volatile memory according to an embodiment of the invention. As shown in fig. 1, a semiconductor substrate 10, such as a silicon substrate, having a logic circuit region 101 and an embedded non-volatile memory region 102 is provided. The logic circuit region 101 has a fin structure 11 therein, and the embedded non-volatile memory region 102 has a fin structure 12 therein, wherein the fin structure 11 and the fin structure 12 are both protruded on an insulating layer 20. According to an embodiment of the present invention, the insulating layer 20 may be a trench insulating structure. The

fin structures

11 and 12 are linear fin structures extending along a first direction. In the figure, the

fin structures

11 and 12 are common structures in the FinFET manufacturing process, and the details of the manufacturing process are not repeated.

Next, a dummy gate layer 22, such as a polysilicon layer or silicon nitride, is formed on the

fin structures

11 and 12, wherein the dummy gate layer 22 is linear and extends along a second direction and crosses the

fin structures

11 and 12, and the second direction is perpendicular to the first direction. According to the embodiment of the invention, the dummy gate layer 22 will not be completely removed in the subsequent steps, and the remaining portion is used as a charge storage layer in the embedded non-volatile memory region 102.

According to an embodiment of the present invention, a gate dielectric layer 110 and a tunnel dielectric layer 120 are formed between the dummy gate layer 22 and the

fin structures

11 and 12, respectively. The gate dielectric layer 110 and the tunnel dielectric layer 120 may be silicon oxide layers formed in the same process, such as, but not limited to, silicon dioxide layers formed by in-situ vapor deposition (ISSG) process.

Next, an interlayer dielectric layer 30 is globally deposited on the semiconductor substrate 10. According to an embodiment of the present invention, the interlayer dielectric layer 30 may comprise a silicon oxide layer, for example, deposited by a chemical vapor deposition process. An interlayer dielectric layer 30 covers fin structure 11, fin structure 12, dummy gate layer 22, and insulating layer 20. Then, the interlayer dielectric layer 30 is polished by a Chemical Mechanical Polishing (CMP) process until an upper surface 22a of the dummy gate layer 22 is exposed. At this time, the upper surface of the dummy gate layer 22 is flush with the upper surface of the interlayer dielectric layer 30.

According to another embodiment of the present invention, as shown in fig. 6, an etch stop layer 24 may be additionally formed on the dummy gate layer 22, and then a sacrificial cap layer 26 may be formed on the etch stop layer 24.

The etch stop layer 24 may comprise silicon nitride. The sacrificial cap layer 26 may comprise polysilicon.

As shown in fig. 2, a selective etching process, such as a dry etching process, is then performed to recess and etch the dummy gate layer 22, so that the upper surface 22a of the dummy gate layer 22 is lower than the upper surface of the interlayer dielectric layer 30, thereby forming a recess trench 220. At this time, the dummy gate layer 22 still has a predetermined thickness t directly above the fin structure 12, which may be between 400 a and 500 a, for example. The dummy gate layer 22 remaining in the embedded nvm region 102 after the recess etch is also referred to as a charge storage layer.

As shown in fig. 3, a photoresist pattern 50 is formed on the interlayer dielectric layer 30 and the charge storage layer 22. The photoresist pattern 50 has a linear opening 50a extending along a first direction, wherein the linear opening 50a is parallel to the

fin structures

11 and 12 and is located between the

fin structures

11 and 12 when viewed from top to bottom.

Next, an etching process is performed to selectively etch the charge storage layer 22 through the linear opening 50a, thereby forming the charge storage structures 22' separated from each other. In the etching process, the photoresist pattern 50 does not cover the logic circuit region 101, so that the dummy gate layer 22 in the logic circuit region 101 is completely removed during the etching process, exposing the gate dielectric layer 110, and forming the trench 230. Subsequently, the photoresist layer 50 is removed.

As shown in fig. 4, a high-k dielectric layer 40 is then simultaneously formed on the charge storage structure 22' in the embedded non-volatile memory region 102 and on the gate dielectric layer 110 in the logic circuit region 101. Wherein the high-k dielectric layer 40 may be selected from the group consisting of: hafnium oxide (HfO)₂) Hafnium silicate (HfSiO)₄) Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al)₂O₃) Lanthanum oxide (La)₂O₃) Tantalum oxide (Ta)₂O₅) Yttrium oxide (Y)₂O₃) Strontium titanate oxide (SrTiO)₃) Zirconium silicate (ZrSiO)₄) Hafnium zirconium oxide (HfZrO)₄) Strontium bismuth tantalate (SrBi)₂Ta₂O₉SBT), lead zirconate titanate (PbZr)_xTi_1-xO₃PZT) and barium strontium titanate (Ba)_xSr_1-xTiO₃BST). The high-k dielectric layer 40 formed over the charge storage structure 22' in the embedded nonvolatile memory region 102 serves as a capacitor dielectric layer.

According to an embodiment of the present invention, the high-k dielectric layer 40 may be formed by using a Chemical Vapor Deposition (CVD) method or an Atomic Layer Deposition (ALD) method. According to an embodiment of the present invention, the high-k dielectric layer 40 is also conformally deposited on the top surface of the interlayer dielectric layer 30.

As shown in FIG. 5, a metal layer 60, such as tungsten, titanium nitride, etc., is then formed on the high-k dielectric layer 40. Then, the high-k dielectric layer 40 and the metal layer 60 on the interlayer dielectric layer 30 may be removed by a Chemical Mechanical Polishing (CMP) process, such that the metal layer 60 remaining in the trench 230 and the recess trench 220 respectively form a gate 60a of a logic circuit and a word line 60b of a memory, and thusCompleting the embedded non-volatile memory M₁And M₂And (4) manufacturing.

The invention has the advantages that the embedded non-volatile memory M₁And M₂The fabrication of the memory cell can be integrated with the fabrication process of a fin field effect transistor (FinFET) in the logic circuit region 101, a polysilicon dummy gate layer used in the FinFET fabrication process is used to make a remaining portion of the gate layer serve as a charge storage layer in the embedded non-volatile memory region 102, and then a high-k dielectric layer post-fabrication (HK-last) fabrication process is used to form a capacitor dielectric layer of the embedded non-volatile memory, and finally a metal gate fabrication process is performed to complete a word line in the embedded non-volatile memory region 102 when a metal gate of the logic circuit region 101 is completed.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims

1. A method of making an embedded non-volatile memory, comprising:

providing a semiconductor substrate with a fin structure protruding from an insulating layer;

forming a charge storage layer across the fin structure;

depositing an interlayer dielectric layer on the semiconductor substrate;

grinding the interlayer dielectric layer until an upper surface of the charge storage layer is exposed;

recess-etching the charge storage layer so that the upper surface of the charge storage layer is lower than the upper surface of the interlayer dielectric layer to form a recessed trench;

severing the charge storage layer into separate charge storage structures;

forming a high-k dielectric layer on the charge storage structure; and

A word line is formed on the high-k dielectric layer.

2. The method of making an embedded non-volatile memory as claimed in claim 1, further comprising:

A tunneling dielectric layer is formed between the charge storage layer and the fin structure.

3. The method of fabricating an embedded non-volatile memory as claimed in claim 2, wherein the tunneling dielectric layer comprises a silicon oxide layer.

4. The method of claim 1, wherein the fin-shaped structure is a linear fin-shaped structure extending along a first direction, and the charge storage layer is a linear charge storage layer, extending along a first direction extending in a second direction, wherein the first direction is perpendicular to the second direction.

5. The method of claim 1, wherein the charge storage layer comprises polysilicon.

6. The method of claim 1, wherein the charge storage layer comprises silicon nitride.

7. The method of claim 1, wherein between grinding the interlayer dielectric layer and recess etching the charge storage layer, further comprising:

forming an etch stop layer on the charge storage layer; and

A sacrificial cap layer is formed on the etch stop layer.

8. The method of claim 7, wherein the etch stop layer comprises silicon nitride.

9. The method of claim 7, wherein the sacrificial cap layer comprises polysilicon.

10. The method of claim 1, wherein the high-k dielectric layer is selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO ₄ ), hafnium Oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), strontium titanate oxide ( SrTiO ₃ ), zirconium silicate (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) ) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST).

11. The method of claim 1, wherein the interlayer dielectric layer is ground until the upper surface of the charge storage layer is exposed, and the upper surface of the charge storage layer and the interlayer The upper surface of the dielectric layer is flush.

12. The method of claim 11, wherein the word line comprises metal.

13. The method of claim 12, wherein the upper surface of the word line is flush with the upper surface of the interlayer dielectric layer.

14. The method of making an embedded non-volatile memory of claim 4, wherein the severing the charge storage layer into separate charge storage structures comprises:

forming a photoresist pattern on the interlayer dielectric layer and the charge storage layer, having a linear opening extending along the first direction;

selectively etching the charge storage layer through the linear opening, thus forming the separate charge storage structure; and

The photoresist pattern is removed.