Drawings
Fig. 1 is a schematic diagram of a capacitive image sensor according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a portion of the capacitive image sensor of fig. 1 taken along line a-a';
FIG. 3 is an equivalent circuit of a capacitive image sensor (a pixel) according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of an exemplary implementation of the capacitive image sensor according to an embodiment of the present invention;
FIG. 5 is a block diagram of another embodiment of the display sample and hold circuit, and a connection between the differential amplifier and the sample and hold circuit;
fig. 6 is a flowchart illustrating a step of operating a capacitive sensing unit in the capacitive image sensor according to the first embodiment of the invention;
FIG. 7 is an equivalent circuit of a capacitive image sensor (a pixel) according to a second embodiment of the present invention;
fig. 8 is a flowchart illustrating a step of operating a capacitive sensing unit in the capacitive image sensor according to the second embodiment of the present invention.
Description of the reference numerals
10 capacitive image sensor
12 semiconductor substrate
13 protective layer
14 active semiconductor circuit
15 insulating layer
30 contact pad of input/output interface
40 contact pad of power supply
100 capacitive sensing cell
110 sensing electrode
120 first switch
140 voltage follower
150 driving circuit
160 driving source
165 drive electrode
170 first comparison capacitor
175 driving impedance
190 bias source
200 sample and hold circuit
210 first sampling switch
220 first charge holding capacitor
230 second sampling switch
240 second charge holding capacitor
250a sample-and-hold circuit
250b sample-and-hold circuit
260a voltage follower
260b voltage follower
270a voltage follower
270b voltage follower
280a row selection switch
280b row selection switch
290a row selection switch
290b row selection switch
300 signal adaptation circuit
310 differential amplifier
311 first input node
312 second input node
320A/D converter
330 column selection switch
340 line selection switch
400 control and input/output circuit
410 control and timing logic
420 buffer and I/O link
500 finger
501 ridge part
502 root of valley
510 finger capacitor
600 capacitive sensing cell
610 sense electricity
620 first switch
630 second switch
640 voltage follower
650 sharing switch
670 first comparison capacitor
680 second comparison capacitor
690 bias source
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the capacitive image sensor and the method for obtaining a finger image according to the present invention are described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The present invention will be more specifically described with reference to the following embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram of a capacitive image sensor 10 according to an embodiment of the invention. The capacitive image sensor 10 is used to trace ridges and valleys on the surface of a finger 500, and further converts the result into a noise-reduced image of the fingerprint. The capacitive image sensor 10 includes an array of capacitive sensing cells 100, a plurality of power pads 40, and a plurality of input/output interface pads 30. The output from each capacitive sensing cell 100 represents a corresponding pixel of the fingerprint image.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a portion of the capacitive image sensor shown in fig. 1, taken along line a-a'. A protection layer 13 is disposed on the upper surface of the capacitive image sensor 10 and a fingertip 500 is disposed on the protection layer 13. The protective layer 13 may be made of glass, sapphire, epoxy or paint. The capacitive image sensor 10 includes a semiconductor substrate 12 having an array of the capacitive sensing cells 100 formed thereon. The surface of the fingertip 500 includes a ridge 501 contacting the protective layer 13 and a valley 502 away from the protective layer 13. Each capacitive sensing cell 100 can be used to convert a distance between a portion of the surface of the finger 500 and the top surface thereof into an output potential. 5 capacitive sense cells 100 are shown in FIG. 2, wherein one capacitive sense cell 100 is surrounded by a dashed-line frame. Each capacitive sensing cell 100 includes a sensing electrode 110 in the form of a conductive plate. Beneath the conductive plate is an active semiconductor circuit 14, which is schematically shown in fig. 2 by the slashed area. At least one insulating layer 15 is formed to cover the sensing electrode 110. Details of the active semiconductor circuit 14 will be described in subsequent paragraphs.
Referring to fig. 3, fig. 3 is an equivalent circuit of a capacitive image sensor 10 (a pixel) according to a first embodiment of the invention. The capacitive image sensor 10 includes an array of capacitive sensing cells 100 (enclosed by dashed lines), a driving circuit 150, a plurality of sample-and-hold circuits 200 (enclosed by dotted lines), a plurality of signal conditioning circuits 300 (enclosed by double dashed lines), and a control and input-output circuit 400 (enclosed by double dashed lines). For illustration purposes, fig. 3 shows only one capacitive sensing cell 100, one sample and hold circuit 200, and one signal adaptation circuit 300. The sample-and-hold circuit 200, the signal conditioning circuit 300, the control and input-output circuit 400, a portion of the capacitive sensing cell 100, and a portion of the driving circuit 150 are formed in the active semiconductor circuit 14. Each circuit will be described in detail below.
The capacitive sensing cell 100 includes a sensing electrode 110, a first switch 120, a voltage follower 140, a first comparison capacitor 170, and a bias source 190. A parasitic capacitance representing the sum of the parasitic capacitance between the sensing electrode 110 and other portions (not shown) of the sensing structure not connected thereto may be considered as a portion of the first comparison capacitor 170. A reference capacitor (not shown) having a capacitance CrFormed between ground and the sensing electrode 110, the reference capacitanceThe device is used to store charge during operation. The reference capacitor is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) capacitor, a Polysilicon-dielectric-Polysilicon (PIP) capacitor, or a Metal-dielectric-Metal (MIM) capacitor. The first comparison capacitor 170 is an equivalent capacitor, denoted by CcRepresents the total effect of the parasitic capacitance and the reference capacitor, i.e. Cc=Cr+Cp. Therefore, one node of the first comparison capacitor 170 is electrically connected to the voltage follower 140, and the other node is electrically connected to the ground. In some manufacturing processes, when the parasitic capacitance value is well controlled, the reference capacitor, i.e., C, may not be neededc=Cp. The driving circuit 150 includes a driving source 160 and a driving electrode 165. The driving source 160 is controlled by a control and timing logic 410 and provides a positive or negative waveform (boost or buck signal) to the driving electrode 165 at different times. The first switch 120, the voltage follower 140, the first comparison capacitor 170, and the driving source 160 are formed in the active semiconductor circuit 14. The driving electrode 165 may be an external component electrically connected to the driving source 160 via one of the input/output contact pads 30, such as a conductive strip or a conductive metal ring. The driver electrode 165 may not be part of the chip but may be a component of a capacitive image sensor module that may include a printed circuit board substrate, a plurality of passive electronic components, a capacitive image sensor 10, and encapsulant. When the finger 500 approaches the capacitive image sensor 10, a finger capacitor 510, denoted by CfShown, formed between finger 500 and sensing electrode 110. Meanwhile, a driving impedance 175 is also formed between the finger 500 and the driving electrode 165. The sensing electrode 110 is a metal plate on the upper side of the capacitive sensing cell 100, and is used to form one side of a parallel plate capacitor. Here, the parallel plate capacitor is an equivalent capacitor representing the finger capacitance 510. The other side of the parallel plate capacitor is the surface of the finger 500, which is part of the human body. The drive electrode 165 carries a drive signal and couples the signal to the finger 500. To maximize the drive signal (reduce)Drive impedance 175 value), a large total contact area is required for the drive electrode 165. For example, a metal ring or a plurality of metal strips surrounding the array of capacitive sense cells 100, or an array of electrodes formed alternately between the capacitive sense cells 100, are all suitable forms of the driving electrodes 165, as long as the total area is large enough to reduce the driving impedance 175. The first switch 120 is a MOS device that is used as a switch to connect or disconnect the bias voltage source 190 (in V)biasRepresented) to the sensing electrode 110 and the first comparison capacitor 170. The bias source 190 is used to provide a fixed bias, which in this embodiment is a fixed bias of 1.5V. The voltage follower 140 is a circuit device having an input and an output signal, the output signal following the input signal. Typically, the voltage follower is implemented as a unity gain amplifier. The input node of the voltage follower 140 is connected to the sensing electrode 110, and the output node is connected to the sample-and-hold circuit 200.
The sample-and-hold circuit 200 of fig. 3 is a device for acquiring and holding the output potential from the capacitive sensing cell 100. The sample-and-hold circuit 200 includes a first sampling switch 210, a first charge-holding capacitor 220, a second sampling switch 230, and a second charge-holding capacitor 240. The first sampling switch 210 is formed between the output node of the voltage follower 140 and the first charge holding capacitor 220, and is a MOS device serving as a switch for connecting the output of the voltage follower 140 to the first charge holding capacitor 220. The first charge holding capacitor 220 is a capacitor for acquiring and holding a first output potential (in V) from the voltage follower 140 via the first sampling switch 2101Representation). A node of the first charge holding capacitor 220 is connected to the first sampling switch 210, and the other node is connected to ground. The second sampling switch 230 is formed between the output node of the voltage follower 140 and the second charge holding capacitor 240, and is a MOS device serving as a switch for connecting the output of the voltage follower 140 to the second charge holding capacitor 240. The second charge holding capacitor 240 is a capacitor for acquiring and holding a second output potential (in V) from the voltage follower 140 via the second sampling switch 2302Representation). First, theOne node of the two charge holding capacitors 240 is connected to the second sampling switch 230, and the other node is connected to ground. The first sampling switch 210 and the second sampling switch 230 operate together as a selection switch for the voltage follower 140 to switch the charge holding capacitor.
The signal conditioning circuit 300 is a circuit that amplifies the voltage difference between the first and second output voltages, may have a level shifter, and then converts the result to a digital value. The signal conditioning circuit 300 includes a differential amplifier 310 and an analog-to-digital converter 320. A first input node 311 of the differential amplifier 310 is connected to the first charge holding capacitor 220 and the first sampling switch 210, a second input node 312 of the differential amplifier 310 is connected to the second charge holding capacitor 240 and the second sampling switch 230, and an input node of the differential amplifier 310 is connected to an input node of the analog-to-digital converter 320. The differential amplifier 310 is an amplifier for generating a voltage output proportional to the difference between the first and second output voltages. The analog-to-digital converter 320 converts the output potential of the differential amplifier 310 and generates a binary value representing the potential level.
The control and input/output circuit 400 is a circuit for processing the timing and data input/output of the capacitive image sensor 10. The control and input/output circuit 400 includes a control and timing logic 410 and buffer and input/output link 420. The control and timing logic 410 controls the switches in all of the capacitive image sensors 10. The buffer and input/output port 420 receives the output data of the analog-to-digital converter 320 and stores the data into a buffer, then sends out the data at the appropriate time.
Referring to fig. 4, fig. 4 is a schematic diagram of an exemplary implementation of the capacitive image sensor 10 according to the present invention. The capacitive image sensor 10 includes a two-dimensional array of capacitive sensing units 100 and a plurality of sample-and-hold circuits 200. In this figure, other circuits are not shown. The capacitive sensing cells 100 of the two-dimensional array are enabled in a row-by-row sequence. The capacitive sensing cells 100 in the same column share the same output line through respective column selection signals, and one column is enabled at a time point by the corresponding column selection signal. The column select signal is sent by control and timing logic 410 to control the column select switch 330. Each column output line is connected to a shared sample and hold circuit 200 and a differential amplifier 310. The output of the differential amplifier 310 is multiplexed to a single output signal via a set of column select signals. The column select signals are sent from control and timing logic 410 to control the column select switches 340. Only one of the column select signals is activated at a time to allow the output of the differential amplifier 310 to be sent to the analog-to-digital converter 320 in the signal conditioning circuit 300 in sequence.
Referring to fig. 5, fig. 5 shows another structure of the display sample and hold circuit according to an embodiment of the present invention, and a structure of the connection between the differential amplifier 310 and the sample and hold circuits 250a/250 b. The sample and hold circuits 250a/250b may share the same differential amplifier 310 through additional voltage followers (e.g., 260a and 270a), row select switches (e.g., 280a and 290a) between the charge holding capacitors (220 and 240) and the differential amplifier 310. For example, a voltage follower 260a and a row select switch 280a are formed between the first charge holding capacitor 220 and the differential amplifier 310, and a voltage follower 270a and a row select switch 290a are formed between the second charge holding capacitor 240 and the differential amplifier 310.
A method for operating the capacitive sensor 10 is also disclosed. Referring to fig. 6, fig. 6 is a flowchart illustrating a step of operating the capacitive sensing unit 100 of the capacitive image sensor 10, which includes the steps of:
s01, setting the driving source 160 to a high potential (3V);
s02, resetting the metal plate (sensing electrode 110) to bias by turning on the first switch 120;
s03, closing the first switch 120 to make the metal plate keep floating;
s04, setting the driving source 160 to zero potential (0V);
s05, the first sampling switch 210 is turned on to charge the first charge-holding capacitor 220 to a first output voltage level V1;
S06, the first sampling switch is turned off by the first charge-holding capacitor 220210 to hold the first output potential V1;
S07, setting the driving source 160 to a low potential (-3V);
s08, resetting the metal plate 110 to bias by turning on the first switch 120;
s09, closing the first switch 120 to make the metal plate keep floating;
s10, setting the driving source 160 to zero potential (0V);
s11, the second sampling switch 230 is turned on to charge the second charge-holding capacitor 240 to a second output voltage level V2。
S12, the second sampling switch 230 is turned off by the second charge-holding capacitor 240 to hold the second output potential V2(ii) a And
s13, an output potential is given by the differential amplifier 310, the output potential is proportional to the difference between the first and second output potentials.
Here, steps 1 to 3(S01 to S03) are the first reset phase, steps 4 to 6(S04 to S06) are the first sensing phase, steps 7 to 9(S07 to S09) are the second reset phase, steps 10 to 12(S10 to S12) are the second sensing phase, and step 13 is the final phase. The output potential in step 13 is proportional to the difference between the first output potential and the second output potential, which is the noise reduction value of the pixel (capacitive sensing unit). The noise reduction value represents a distance between the capacitive sensing unit and a surface of a finger portion of the capacitive sensing unit. The order of steps S01-S06 and steps S07-S12 may be interchanged. In other words, a positive waveform and a negative waveform applied by the driving source are used to obtain the noise reduction value regardless of the sequence. For better understanding, the waveform formed in steps 1 to 4 is taken as a first waveform and the waveform in steps 7 to 10 is taken as a second waveform. If the first waveform is a positive waveform, the second waveform is a negative waveform; if the first waveform is a negative waveform, the second waveform is a positive waveform. There may be additional steps to convert the output potential to a digital image, the steps comprising:
s14, collecting the noise reduction values obtained under the corresponding positive and negative waveforms for each pixel in sequence;
s15, converting the noise reduction value into a digital noise reduction value; and
s16, mapping the digital noise reduction values to the positions of the corresponding capacitive sensing units.
For better understanding, the results analysis is shown below. After step S04, the potential of the metal plate should be
Here, V
biasIs the bias voltage source potential (1.5V), Δ V
d1For potential changes caused by a negative waveform (a voltage drop signal) sent by the driving
source 160, C
fIs the value of
finger capacitance 510, (C)
r+C
p) Is a comparison capacitor 170 (C)
pIs the value of the parasitic capacitance, C
rIs the value of the reference capacitor). The effect of the
drive impedance 175 is too small to be negligible. After step S05, the first output potential may be set
To indicate. Here, N is the fixed mode noise caused by the impedance mismatch of the voltage follower circuit and circuit components, G
fIs the gain factor of the voltage follower and is typically less than 1. After step S10, the potential of the metal plate should be
Here,. DELTA.V
d2Is a potential change caused by a positive waveform (a voltage rising signal) transmitted from the driving
source 160. In the present embodiment, Δ V
d1=-ΔV
d2=ΔV
d. After step S11, the second output potential may be set
To indicate.The positive and negative waveforms are symmetrical in shape, being a step function in this embodiment. In the final stage S13, the output of the
differential amplifier 310 may be provided
To indicate. Here, g is the gain factor of the differential amplifier. In the method, the fixed mode noise term (N) is cancelled.
Referring to fig. 7, fig. 7 is an equivalent circuit of a capacitive image sensor 20 (a pixel) according to a second embodiment of the present invention. The only difference from the previous embodiment is the capacitive sensing cell 600. In the present embodiment, the capacitive sensing unit 600 includes a sensing electrode 610, a first switch 620, a second switch 630, a sharing switch 650, a voltage follower 640, a first comparing capacitor 670, a second comparing capacitor 680, and a bias voltage source 690. A parasitic capacitance representing the sum of the parasitic capacitance between the input node of the voltage follower 640 and the other part (not shown) of the sensing structure not connected to it can be considered as a part of the first comparison capacitor 670. The value of the parasitic capacitance is Cp1It may include the parasitic input capacitance of the voltage follower 640, the drain-to-bulk capacitance of the first switch 620 and the sharing switch 650, or the stray capacitance of any device having a node connected to the voltage follower 640. Another parasitic capacitance representing the sum of the parasitic capacitance between the sensing electrode 610 and the other part (not shown) of the sensing structure not connected to it can be considered as a part of the second comparison capacitor 680. The value of the parasitic capacitance is Cp2It is shown that the drain-to-bulk capacitance of the second switch 630 and the sharing switch 650, or the stray capacitance of any device having a node connected to the sensing electrode 610, may be included. A reference capacitor (not shown) having a capacitance Cr1 is formed between ground and the voltage follower 640 to store charge during operation. Another reference capacitor (not shown) having a capacitance Cr2Formed between ground and sense electrode 610 to store charge during operation. Details of the operation will be described laterAs described in the paragraphs. The first and second comparison capacitors (670 and 680) are equivalent capacitors, respectively denoted by Cc1And Cc2Showing that each represents the overall effect of the parasitic capacitance and the reference capacitor, i.e., Cc1=Cr1+Cp1And Cc2=Cr2+Cp2. For the same reasons as in the previous embodiment, the reference capacitor is missing. When the finger 500 approaches the capacitive sensing cell 600, a finger capacitor 510, denoted by CfIndicating, formed therebetween. The sensing electrode 610 is a metal plate on the upper side of the capacitive sensing cell 100, and is used to form one side of a parallel plate capacitor. Here, the parallel plate capacitor is an equivalent capacitor representing the finger capacitance 510. The other side of the parallel plate capacitor is the surface of the finger 500, which is part of the human body. The drive electrode 165 carries a drive signal and couples the drive signal to the finger 500. The first switch 620 is a MOS device and has one end connected to the input node of the voltage follower 640 and one end of the first comparison capacitor 670 for charging or discharging the first comparison capacitor 670. The other terminal of the first switch 620 is connected to a bias source 690, and the other terminal of the first comparison capacitor 670 is connected to ground. The second switch 630 is also a MOS device, one end of which is connected to the sensing electrode 610 and one end of the second comparing capacitor 680, for charging or discharging the sensing electrode 610 and the second comparing capacitor 680. The other terminal of the second switch 630 is connected to ground, and the other terminal of the second comparison capacitor 680 is also connected to ground. The sharing switch 650 is formed between the first comparing capacitor 670 and the second comparing capacitor 680 for sharing charges among the finger capacitor 510, the first comparing capacitor 670 and the second comparing capacitor 680. In this embodiment, the bias voltage is a 2V fixed bias voltage. The voltage follower 640 is a circuit device having input and output signals, the output signal following the input signal. Typically, the voltage follower is implemented as a unity gain amplifier. The input node of the voltage follower 640 is connected to the first comparison capacitor 670, and the output node is connected to the sample-and-hold circuit 200.
A method for operating the capacitive sensor 20 is also disclosed. Referring to fig. 8, fig. 8 is a flowchart illustrating a step of operating the capacitive sensing unit 600 in the capacitive image sensor 20, which includes the steps of:
s31, turning off the first switch and turning on the second and sharing switches to discharge the sensing electrode 610 and the comparison capacitor to zero, and setting the driving source 160 to high potential (1.5V);
s32, turning off the second and sharing switches and turning on the first switch to charge the first comparison capacitor 670 to the bias voltage, and then turning off the first switch;
s33, turning on the sharing switch to share the charges accumulated in the first comparing capacitor 670 to the sensing electrode 610 and the second comparing capacitor 680, and setting the driving source to zero potential (0V) to apply the driving signal;
s34, the first sampling switch 210 is turned on to charge the first charge-holding capacitor 220 to a first output voltage level V1;
S35, the first sampling switch 210 is turned off by the first charge-holding capacitor 220 to hold the first output voltage V1;
S36, turning off the first switch and turning on the second and sharing switches to discharge the sensing electrode 610 and the comparison capacitor to zero potential, and setting the driving source 160 to a low potential (-1.5V);
s37, turning off the second and sharing switches and turning on the first switch to charge the first comparison capacitor 670 to the bias voltage, and then turning off the first switch;
s38, turning on the sharing switch to share the charges accumulated in the first comparing capacitor 670 to the sensing electrode 610 and the second comparing capacitor 680, and setting the driving source to zero potential (0V) to apply the driving signal;
s39, the second sampling switch 230 is turned on to charge the second charge-holding capacitor 240 to a second output voltage level V2;
S40, the second sampling switch 230 is turned off by the second charge-holding capacitor 240 to hold the second output potential V2(ii) a And
s41, an output potential is given by the differential amplifier 310, the output potential is proportional to the difference between the first and second output potentials.
Here, the first and second steps (S31-S32) are a first reset phase, the third to fifth steps (S33-S35) are a first sensing phase, the sixth to seventh steps (S36-S07) are a second reset phase, the eighth to tenth steps (S38-S40) are a second sensing phase, and the step S41 is a final phase. Similarly, the order of steps S31-S35 and steps S36-S40 may be interchanged. The output voltage in step S41 is the noise reduction value of the pixel (capacitive sensing cell). There may be additional steps to convert the output potential into a digital image, these steps being:
s42, collecting the noise reduction values obtained under the corresponding positive and negative waveforms for each pixel in sequence;
s43, converting the noise reduction value into a digital noise reduction value; and
s44, mapping the digital noise reduction values to the positions of the corresponding capacitive sensing units.
For better understanding, the results analysis is shown below. After step S33, the potential of the metal plate should be
Here, V
biasIs the potential of a bias source, C
fIs the value of
finger capacitance 510, C
c1Is the value of the
first comparison capacitor 670, C
c2Is the value of the
second comparison capacitor 680. After step S34, the first output potential may be set
To indicate. Here, N is the fixed mode noise caused by the impedance mismatch of the voltage follower circuit and circuit components, G
fIs the gain factor of the voltage follower and is typically less than 1. After step S38, the potential of the metal plate should be
After step S39, the second output potential may be set
To indicate. In the final stage S41, the output of the
differential amplifier 310 may be provided
To indicate. Here, g is the gain factor of the differential amplifier. In the method, the fixed mode noise term (N) is cancelled.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.