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CN108682684B - Trench gate power MOS transistor containing semi-insulating region and preparation method thereof - Google Patents

Trench gate power MOS transistor containing semi-insulating region and preparation method thereof Download PDF

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CN108682684B
CN108682684B CN201810447385.4A CN201810447385A CN108682684B CN 108682684 B CN108682684 B CN 108682684B CN 201810447385 A CN201810447385 A CN 201810447385A CN 108682684 B CN108682684 B CN 108682684B
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周郁明
王兵
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Anhui University of Technology AHUT
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Abstract

本发明公开了一种含半绝缘区的槽栅功率MOS晶体管及其制备方法，属于高压电力电子技术领域。一种含半绝缘区的槽栅功率MOS晶体管，包括第二导电类型掺杂的源区、第一导电类型掺杂的基区和半绝缘区，第二导电类型掺杂的源区位于并排设置的第一导电类型掺杂的基区和半绝缘区上方，半绝缘区的底部与第二导电类型半导体掺杂的漂移层接触。半绝缘区是先采用离子注入第二导电类型的杂质实现反掺杂形成电中性层，然后依靠离子注入两性杂质元素形成半绝缘区。针对现有技术中槽栅功率MOS晶体管的UIS雪崩耐量低的问题，本发明能显著提高槽栅功率MOS晶体管的UIS雪崩耐量和鲁棒性，提高槽栅功率MOS晶体管抵御大电流能力，提高槽栅功率MOS晶体管的可靠性，并适当提高槽栅功率MOS晶体管的击穿电压。

Figure 201810447385

The invention discloses a trench gate power MOS transistor including a semi-insulating region and a preparation method thereof, belonging to the technical field of high-voltage power electronics. A trench gate power MOS transistor containing a semi-insulating region, comprising a source region doped with a second conductivity type, a base region doped with a first conductivity type, and a semi-insulating region, the source regions doped with the second conductivity type being arranged side by side Above the base region doped with the first conductivity type and the semi-insulating region, the bottom of the semi-insulating region is in contact with the drift layer doped with the semiconductor of the second conductivity type. In the semi-insulating region, firstly, ion implantation of impurities of the second conductivity type is used to realize counter-doping to form an electric neutral layer, and then the semi-insulating region is formed by ion implantation of amphoteric impurity elements. Aiming at the problem of low UIS avalanche resistance of the trench gate power MOS transistor in the prior art, the invention can significantly improve the UIS avalanche resistance and robustness of the trench gate power MOS transistor, improve the ability of the trench gate power MOS transistor to withstand large currents, and improve the The reliability of the gate power MOS transistor is improved, and the breakdown voltage of the trench gate power MOS transistor is appropriately improved.

Figure 201810447385

Description

Trench gate power MOS transistor containing semi-insulating region and preparation method thereof
Technical Field
The invention relates to the technical field of high-voltage power electronics, in particular to a trench gate power MOS transistor containing a semi-insulating region and a preparation method thereof.
Background
With the continuous improvement of the performance requirements of power conversion devices, higher requirements are put on power MOS transistor devices which undertake power conversion functions, one of which is that the power MOS transistor devices have higher avalanche tolerance in the unclamped inductive load switching process (UIS), that is, have higher anti-UIS avalanche breakdown capability, because the energy stored in the inductive load under the UIS condition is required to be completely released by the power MOS transistor when the power MOS transistor devices are turned off, at this time, very high current stress in the circuit easily causes the device failure, and thus the avalanche breakdown tolerance is one of the important indexes which embody the performance of the power MOS transistor.
Researches show that a natural parasitic triode (BJT) is arranged in a groove gate power MOS transistor body, the BJT is composed of a second conduction type doped source region (21), a first conduction type doped base region (22) and a second conduction type doped drift region (12) which form the groove gate power MOS transistor shown in the figure 1, when the groove gate power MOS transistor is conducted, current flows through the base region (22) from the drift region (12) to the source region (21) to generate voltage drop, the voltage drop raises base electrode potential of the BJT to enable an emitter junction of the BJT to be positively biased, accordingly, the conduction probability of the parasitic BJT is increased, the conduction of the BJT greatly increases leakage current of the groove gate power MOS transistor, the temperature in the MOS transistor rises rapidly, and finally the groove gate power MOS transistor is burnt out due to 'heat'. In the prior art, the avalanche tolerance is improved by delaying or inhibiting the conduction angle of the BJT.
Kevin Fischer et al, IEEE TRANSACTIONS ELECTRON DEVICES 1996, Vol.43, No. 6, published article "Dynamics of Power MOSFET Switching throughout Under advanced Inductive Loading Conditions" proposed the shallow P band shown in FIG. 2+A protective layer of DMOSFET structure with shallow P+The high doping concentration of the protective layer reduces the base resistance and the base potential of the parasitic BJT, thereby inhibiting or delaying the conduction of the parasitic BJT in figure 1, eliminating the secondary breakdown of the BJT, improving the avalanche tolerance and robustness of the MOSFET under UIS condition, and improving the reliability of the MOSFET. But can not completely stop the starting of the parasitic BJT, and can not completely avoid the device failure problem caused by avalanche breakdown, and the high-doped narrow P+The protection layer may affect the threshold voltage of the power MOS transistor, which is not favorable for the application of the power MOS transistor.
Chinese invention patent, grant publication number: CN 102832245B, date of authorized announcement: 2014.12.10, respectively; a second conductive type semiconductor doping island region with higher doping concentration is embedded in a second conductive type semiconductor doping column region, meanwhile, a metalized source electrode is made into a groove-shaped structure, a second conductive type semiconductor doping contact region is arranged at the bottom of grooves at two ends of a metalized source electrode and close to the second conductive type semiconductor doping island region, avalanche breakdown current is far away from a base region of a parasitic BJT, and then the avalanche breakdown current path is changed when the super junction MOSFET device is subjected to avalanche breakdown, so that the BJT is prevented from being started due to the fact that the source electrode of the parasitic BJT is positively biased, and the reliability of the device is improved. The patent needs to be specifically designed according to depth, width and concentration, the calculation process is complex, very high avalanche breakdown current is completely possibly diffused to a base region to cause starting of a parasitic BJT, and in addition, the introduction of a high-doped island region can reduce the breakdown voltage of a power MOS transistor device.
Disclosure of Invention
1. Technical problem to be solved by the invention
The invention provides a trench gate power MOS transistor containing a semi-insulating region and a preparation method thereof, aiming at the problem of low avalanche tolerance of the trench gate power MOS transistor in the prior art. The avalanche tolerance and the robustness of the trench gate power MOS transistor UIS can be greatly improved, and the reliability of the trench gate power MOS transistor is greatly improved.
2. Technical scheme
In order to solve the problems, the technical scheme provided by the invention is as follows:
a trench gate power MOS transistor comprising a semi-insulating region comprises a second conduction type doped source region, a first conduction type doped base region and a semi-insulating region, wherein the second conduction type doped source region is positioned above the first conduction type doped base region and the semi-insulating region which are arranged side by side, and the bottom of the semi-insulating region is in contact with a second conduction type doped drift layer.
Preferably, the width of the second-conductivity-type-doped source region is equal to the sum of the widths of the first-conductivity-type-doped base region and the semi-insulating region.
Preferably, the depth of the first-conductivity-type-doped base region is identical to the depth of the semi-insulating region. The effective channel length of the groove gate power MOS transistor is ensured not to be changed due to the introduction of the semi-insulating region, and parameters such as threshold voltage, on-resistance, transconductance and output characteristics of the groove gate power MOS transistor are ensured not to be changed due to the introduction of the semi-insulating region.
Preferably, the first conductivity type is P-type and the second conductivity type is N-type; or the first conduction type is N type, the second conduction type is P type, and the method is suitable for the groove grid power MOS transistors with different conduction channels.
Preferably, the width ratio of the base region doped with the first conductivity type to the source region doped with the second conductivity type is 1: 1-3.
Preferably, the trench gate power MOS transistor is made of a semiconductor material such as bulk silicon, silicon carbide, gallium arsenide, indium phosphide, germanium silicon, and the like, and can be popularized and used in trench gate power MOS transistors made of different semiconductor materials.
A preparation method of a groove gate power MOS transistor containing a semi-insulating region comprises the following steps:
A. implanting impurities of a first conductivity type into a drift region of a second conductivity type;
B. implanting impurity elements of a second conductivity type into the outer side of the narrow base region (22) by using the shielding effect of a mask, wherein the implantation concentration and the implantation depth are consistent with those of the impurities of the first conductivity type implanted by the ions in the step A, and forming an electric neutral region;
C. continuously injecting amphoteric impurity elements on the formed electrically neutral region to form a semi-insulating region;
D. injecting impurities of a second conductive type into the semi-insulating region and the base region doped with the first conductive type to form a source region doped with the second conductive type;
E. forming an insulated gate and a polysilicon region;
F. and forming three metal electrodes of a source electrode, a grid electrode and a drain electrode of the groove grid power MOS transistor.
Step A, implanting impurities of a first conduction type into a drift region of a second conduction type by adopting an ion implantation process;
step B, utilizing the shielding effect of a mask plate, ion-injecting impurity elements of a second conductive type into the outer side of the base region doped with the first conductive type, wherein the injection concentration and the injection depth are consistent with those of the impurities of the first conductive type injected by the ions in the step A, and forming an electric neutral region; and neutralizing carriers of the first conductivity type in the region in a high temperature activated form to form an electrically neutral region;
c, the depth of the implanted amphoteric impurity elements is consistent with that of the electrically neutral region;
and step A, B and C, annealing under the protection of inert gas and at proper temperature.
Step E, forming an insulated gate and a polycrystalline silicon region by utilizing the shielding effect of the mask plate and adopting a grooving process and a thermal oxidation growth process;
and step F, forming three metal electrodes of a source electrode, a grid electrode and a drain electrode of the groove grid power MOS transistor by adopting a film coating process and a metal stripping process.
Preferably, the step a is carried out by implanting impurities of the first conductivity type to form a surface concentration of 2 × 1017cm-3。
Preferably, the implantation of the impurities in steps a and B is a plurality of ion implantations, forming a box-type doping profile.
Preferably, the first-conductivity-type-doped base region and the semi-insulating region have a depth of 0.8um in the substrate.
Preferably, the doping concentration of the first conductivity type doped base region is 5 × 1016cm-3～5×1017cm-3In the meantime.
3. Advantageous effects
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
(1) the invention reduces the area of parasitic BJT, namely reduces the number of parasitic BJT, only there are a few parasitic BJT under the channel area, but because of the great reduction of the number of parasitic BJT, thus reduce the current in the power MOS transistor under UIS condition, has limited the rise of the temperature, the time that the power MOS transistor of the groove gate breaks down avalanche is improved from 8 microseconds to 36 microseconds theoretically, thus has offered the sufficient time for the intervention of the protective circuit;
(2) the invention is characterized in that a semi-insulating region is formed outside a trench gate power MOS transistor channel, and the PN junction outside the channel is changed into a structure of the semi-insulating region/the second conductive type doped drift region, so that the breakdown voltage of the trench gate power MOS transistor can be improved by 35%, and the document of Kevin Fischer et al does not change the PN junction structure of the MOSFET, namely, the breakdown voltage is not influenced;
(3) the semi-insulating region is formed outside the channel, the channel region of the groove grid power MOS transistor is not influenced, and therefore the characteristic parameters of threshold voltage, channel resistance, transfer characteristic, output characteristic, carrier mobility, transconductance and the like of the groove grid power MOS transistor are not influenced;
(4) in the trench gate power MOS transistor with the conventional structure shown in fig. 1, a metal electrode of a source electrode needs to cover a source region and a shallow protective layer, which is short-circuited with the source region and the shallow protective layer so as not to generate a potential difference in the base region, and is one of measures for reducing the conduction probability of a parasitic BJT and improving the robustness+The source region is used for dispersing conductive carriers in the source region, homogenizing current density, reducing current concentration effect and improving avalanche breakdown time of the groove gate power MOS transistor;
(5) the channel region of the trench gate power MOS transistor is not influenced, the avalanche tolerance and the robustness of the trench gate power MOS transistor under the UIS condition can be improved, and the breakdown voltage of the trench gate power MOS transistor can be improved, so that the two purposes are achieved;
(6) the invention is suitable for groove grid power UMOS transistor, groove grid power VMOS transistor and its derivative device made based on various semiconductor materials, P type or N type is also suitable, for the above-mentioned different kinds of devices, only because the structure and name of the device are different, but form this kind of strip groove grid structure, improve UIS avalanche tolerance, improve robustness and reliability, improve the technological process and its characteristic in the aspects such as breakdown voltage, etc. the same;
(7) the depth of the semi-insulating region in the substrate is limited by limiting the ion implantation process and the depth of the first conductive type doped base region, so that the first conductive type doped base region is not affected, the effective channel length of the trench gate power MOS transistor is ensured not to be changed due to the introduction of the semi-insulating region, and parameters such as threshold voltage, on-resistance, transconductance and output characteristics of the trench gate power MOS transistor are ensured not to be changed due to the introduction of the semi-insulating region; the channel current carrier is ensured to be stably transported without exceeding the threshold, otherwise, the formed abrupt junction forms a potential barrier on the current carrier, and the normal work of the device is not facilitated.
Drawings
FIG. 1 is a schematic diagram of a conventional trench-gate power MOS transistor structure and its parasitic BJT;
FIG. 2 is a schematic diagram of a DMOSFET structure with a shallow protective layer;
FIG. 3 is a schematic diagram of a trench-gate power UMOS transistor structure according to the present invention;
fig. 4 is a schematic diagram of the structure of the gate power VMOS transistor of the present invention.
The reference numerals in the schematic drawings illustrate:
10. the semiconductor device comprises a polycrystalline silicon layer, 11, a groove-shaped insulated gate, 12, a second conduction type doped drift layer, 13, a second conduction type doped buffer layer, 14, a second conduction type doped substrate, 21, a second conduction type doped source region, 22, a first conduction type doped base region, 221, a second conduction type doped shallow protection layer, 222, a semi-insulating region, 31, a source electrode, 32, a grid electrode, 33 and a drain electrode.
Detailed Description
For a further understanding of the present invention, reference will now be made in detail to the embodiments illustrated in the drawings.
Example 1
With reference to fig. 3 and 4, the trench gate power MOS transistor including the semi-insulating region of the present embodiment includes the second conductivity type doped source region 21, the first conductivity type doped base region 22, and the semi-insulating region 222, where the second conductivity type doped source region 21 is located above the first conductivity type doped base region 22 and the semi-insulating region 222 that are arranged side by side, and the bottom of the semi-insulating region 222 is in contact with the second conductivity type doped drift layer 12.
The semi-insulating region 222 reduces the area where the parasitic BJT exists, that is, reduces the number of the parasitic BJT, and only a small number of parasitic BJT exists under the channel area, but because the number of the parasitic BJT is greatly reduced, the current in the MOSFET under the UIS condition is reduced, the temperature rise is limited, the time for the MOSFET to generate the avalanche breakdown is increased from 8 microseconds theoretically to 36 microseconds, the time integral of the voltage to the current is increased, the avalanche breakdown energy is increased, and sufficient time is provided for the intervention of the protection circuit.
The paper "Dynamics of Power MOSFET Switching over Undredged Experimental Loading Conditions" is by shallow P+The high doping concentration of the protective layer reduces the base resistance and the base potential of the parasitic BJT, thereby inhibiting or delaying the conduction of the parasitic BJT in figure 1; the invention discloses a super-junction MOSFET device with an optimized avalanche breakdown current path, which is disclosed in the patent with the publication number of CN 102832245B, wherein a second conductive type semiconductor doped island region is added, and the structure of the device is improved, so that the avalanche breakdown current is far away from the base region of a parasitic BJT, and the avalanche breakdown current path when the super-junction MOSFET device is subjected to avalanche breakdown is changed, and the BJT is prevented from being started due to the fact that the source electrode of the parasitic BJT is positively biased, and the reliability of the device is improved. The two documents have the same idea for solving the problems: starting from the conduction or non-conduction of the BJT, reducing the leakage current of the groove gate power MOS transistor; the present invention abandons the above thought, does not consider whether the BJT is turned on or not, introduces the semi-insulating region 222 to solve the problem of low avalanche resistance of the device under the condition that the prior art scheme does not give any technical inspiration, reduces the leakage current of the trench gate power MOS transistor from the viewpoint of reducing the number of parasitic BJTs to improve avalanche resistance, and brings unexpected technical effects on other performance aspects of the device.
The first-conductivity-type-doped base region of conventional structure is divided into a first-conductivity-type-doped base region 22 capable of forming a conductive channel and a semi-insulating region 222. The breakdown voltage is a key parameter of the trench gate power MOS transistor and is determined by PN junctions of the base region doped with the first conduction type and the drift region doped with the second conduction type of the trench gate power MOS transistor.
The semi-insulating region 222 does not damage the first conductivity type doped base region 22 that can form a conductive channel and thus does not affect the critical parameters of the trench gate power MOS transistor such as threshold voltage, transconductance, on-resistance, etc. The channel region of the trench gate power MOS transistor is not influenced, the avalanche tolerance and the robustness of the trench gate power MOS transistor under the UIS condition can be improved, and the breakdown voltage of the trench gate power MOS transistor can be improved.
Example 2
With reference to fig. 3 and 4, the trench gate power MOS transistor including the semi-insulating region according to this embodiment is further improved based on embodiment 1, where the width of the source region 21 doped with the second conductivity type is equal to the sum of the widths of the base region 22 doped with the first conductivity type and the semi-insulating region 222.
The effective width of the conductive channel formed by the base region 22 doped with the first conductivity type is accurately controlled, and is not changed due to the introduction of the semi-insulating region 222, so that parameters such as threshold voltage, on-resistance, transconductance and output characteristics of the trench gate power MOS transistor are ensured not to be changed due to the introduction of the semi-insulating region 222. The channel region of the trench gate power MOS transistor is not influenced, the avalanche tolerance and the robustness of the trench gate power MOS transistor under the UIS condition can be improved, and the breakdown voltage of the trench gate power MOS transistor can be improved.
Example 3
With reference to fig. 3 and 4, the trench gate power MOS transistor including the semi-insulating region according to this embodiment is further improved based on embodiments 1 and 2, and the depth of the first conductivity type doped base region 22 is the same as the depth of the semi-insulating region 222. The width ratio of the first-conductivity-type-doped base region 22 to the second-conductivity-type-doped source region 21 is 1: 1-3. In specific application, 1: 1; 1: 2; 1: 3; 1: 1.5; 1: 2.8, etc.
The effective channel length of the trench gate power MOS transistor is ensured not to be changed due to the introduction of the semi-insulating region 222, and parameters such as threshold voltage, on-resistance, transconductance and output characteristics of the trench gate power MOS transistor are ensured not to be changed due to the introduction of the semi-insulating region. The channel current carrier is ensured to be stably transported without exceeding the threshold, otherwise, the formed abrupt junction forms a potential barrier on the current carrier, and the normal work of the device is not facilitated.
Example 4
With reference to fig. 3 and 4, a trench gate power MOS transistor including a semi-insulating region according to this embodiment is further improved based on embodiments 1, 2 and 3, where the first conductivity type is P-type, and the second conductivity type is N-type; or the first conduction type is N type, the second conduction type is P type, and the method is suitable for the groove grid power MOS transistors with different conduction channels.
Example 5
With reference to fig. 3 and 4, the trench gate power MOS transistor including the semi-insulating region according to this embodiment is further improved on the basis of embodiments 1, 2, 3, and 4, and the trench gate power MOS transistor is made of a semiconductor material such as bulk silicon, silicon carbide, gallium arsenide, indium phosphide, and silicon germanium, and can be popularized and used in trench gate power MOS transistors made of different semiconductor materials.
The trench gate power UMOS transistor, the trench gate power VMOS transistor and derivatives thereof manufactured based on various semiconductor materials are all suitable for use, and the P type or N type is also suitable for use, and for the different types of devices, the process methods and the characteristics in the aspects of forming the trench gate structure, improving avalanche tolerance, robustness and reliability, improving breakdown voltage and the like are the same only because the structures and the names of the devices are different.
Example 6
With reference to fig. 3 and 4, the method for manufacturing a trench gate power MOS transistor including a semi-insulating region according to this embodiment may be used to manufacture a trench gate power MOS transistor including a semi-insulating region according to any one of embodiments 1, 2, 3, 4, and 5, and includes the steps of:
A. implanting impurities of the first conductivity type into the drift region 12 of the second conductivity type; reserving space for the first conductivity type doped base region 22 and the electrically neutral region;
B. implanting impurity elements of a second conductivity type into the outer side of the base region (22) doped with the first conductivity type to form an electrically neutral region;
implanting impurity elements of a second conductivity type at the outer side of the preset base region 22 doped with the first conductivity type, and neutralizing the impurity elements of the first conductivity type implanted in the step a to form an electrically neutral region to prepare for forming the semi-insulating region 222;
C. continuing to implant amphoteric impurity elements on the electrically neutral regions to form semi-insulating regions 222;
D. implanting impurities of a second conductive type on the semi-insulating region 222 and the base region 22 doped with the first conductive type to form a source region 21 doped with the second conductive type;
E. forming an insulated gate 11 and a polysilicon region 10;
F. three metal electrodes of a source 31, a gate 32 and a drain 33 of the trench gate power MOS transistor are formed.
Example 7
With reference to fig. 3 and 4, the method for manufacturing a trench gate power MOS transistor including a semi-insulating region according to this embodiment may be used to manufacture a trench gate power MOS transistor including a semi-insulating region according to any one of embodiments 1, 2, 3, 4, and 5, and is different from embodiment 6 in that:
step a, implanting impurities of a first conductivity type into the drift region 12 of a second conductivity type by using an ion implantation process;
step B, utilizing the shielding effect of a mask plate, ion-injecting impurity elements of a second conductive type into the outer side of the base region 22 doped with the first conductive type, wherein the injection concentration and the injection depth are consistent with those of the impurities of the first conductive type injected by the ions in the step A, so that the impurities of the first conductive type are neutralized, and an electric neutral region is formed; and carriers of the first conductivity type are neutralized in a high temperature activated form to form an electrically neutral region, followed by ion implantation of an amphoteric impurity element to form semi-insulating region 222.
The depth of the amphoteric impurity element injected in the step C is consistent with that of the electric neutral region, so that a semi-insulating region 222 with a determined size and shape is ensured to be formed; and step A, B and C, annealing under the protection of inert gas and at proper temperature.
Step E, forming an insulated gate 11 and a polycrystalline silicon region 10 by using the shielding effect of the mask and adopting a grooving process and a thermal oxidation growth process; and step F, forming three metal electrodes of a source electrode 31, a grid electrode 32 and a drain electrode 33 of the groove grid power MOS transistor by adopting a film coating process and a metal stripping process.
Example 8
With reference to fig. 3 and 4, the method for manufacturing a trench gate power MOS transistor including a semi-insulating region according to this embodiment may be used to manufacture a trench gate power MOS transistor including a semi-insulating region according to any one of embodiments 1, 2, 3, 4, and 5, and is different from embodiments 6 and 7 in that: implanting impurities of the first conductivity type in step A to form a surface having a concentration of 2X 1017cm-3。
The threshold voltage of about 3.5V is obtained, and the requirement of a normal power converter device is met. The concentration of surface impurity elements is used for determining the threshold voltage, the threshold voltage of a normal device is generally 3-5V, the threshold voltage is too low to cause false triggering, and the threshold voltage is too high to increase conduction loss and driving loss.
Example 9
With reference to fig. 3 and 4, the method for manufacturing a trench gate power MOS transistor including a semi-insulating region according to this embodiment may be used to manufacture a trench gate power MOS transistor including a semi-insulating region according to any one of embodiments 1, 2, 3, 4, and 5, and compared with embodiments 6, 7, and 8, the difference is that: and the impurity implantation in the step A and the step B is multiple ion implantation to form box-type doping distribution.
The impurity element implantation processes in the steps A, B and C both adopt an ion implantation process; and the impurity implantation is repeated ion implantation to form box-type doping distribution, and annealing is carried out at a proper temperature under the protection of inert gas after the ion implantation.
Ion implantation is the most common doping method in semiconductor process and the most suitable doping method in the present invention, and diffusion is also the common doping method in semiconductor, but the doping in step A, B, C is implemented on an epitaxial wafer, and ion implantation is the most effective and time-saving method, especially the most suitable method for preparing the third generation semiconductor material silicon carbide with high power, and the diffusion process is almost not feasible, and high-energy ion implantation is necessary to implement the impurity element implantation in steps A, B and C.
The semiconductor doping formed by single ion implantation is often gaussian distributed, the box-type distribution is generally formed by multiple ion implantation, the doping distribution of the second conductivity type in the drift layer 12 of the second conductivity type semiconductor doping of the purchased epitaxial wafer is often uniform, so that the uniform doping in the drift layer 12 of the second conductivity type semiconductor doping can be completely neutralized only by the box-type doping formed by multiple ion implantation in the step a. Further, the ion implantation process is also performed multiple times in step B, so that the insulating region 222 and the second conductive type semiconductor doped drift layer 12 formed in this way form a structure of an insulating layer/second conductive type semiconductor doped drift layer 12 with higher insulating strength, which is beneficial to improving the blocking voltage of the MOS transistor. After ion implantation, annealing is needed to activate the implanted ions, otherwise active doping cannot be formed, i.e. no effect is achieved; the temperature is typically several hundred degrees and varies from substrate material to substrate material.
Example 10
With reference to fig. 3 and 4, the method for manufacturing a trench gate power MOS transistor including a semi-insulating region according to this embodiment may be used to manufacture a trench gate power MOS transistor including a semi-insulating region according to embodiments 1, 2, 3, 4, and 5, and compared with embodiments 6, 7, 8, and 9, the difference is that: the first conductivity type doped base region 22 and semi-insulating region 222 are 0.8um deep in the substrate.
The depth of the semi-insulating region 222 is also limited by the ion implantation process, and the two ensure that the effective channel length of the trench gate power MOS transistor is not changed due to the introduction of the semi-insulating region 222, and ensure that the parameters of the trench gate power MOS transistor, such as the threshold voltage, the on-resistance, the transconductance, and the output characteristic, are not changed due to the introduction of the semi-insulating region. The channel current carrier is ensured to be stably transported without exceeding the threshold, otherwise, the formed abrupt junction forms a potential barrier on the current carrier, and the normal work of the device is not facilitated.
Example 11
With reference to fig. 3 and 4, the method for fabricating a trench-gate power MOS transistor including a semi-insulating region according to this embodiment can be used to fabricate a trench-gate power MOS transistor including a semi-insulating region according to embodiments 1, 2, 3, 4, and 5, and embodiments 6,7. 8, 9, 10 compare, the difference lies in: the doping concentration of the first conductivity type doped base region 22 is 5 × 1016cm-3～5×1017cm-3In the meantime, the doping concentration of the base region 22 doped with the first conductivity type can be selectively controlled to be 5 × 10 in specific application16cm-3、6×1016cm-3、1×1017cm-3、2×1017cm-3、3×1017cm-3、4×1017cm-3、5×1017cm-3And the concentration parameter is used for determining the threshold voltage of the groove gate power MOS transistor.
The doping concentration of the second conductivity type semiconductor doped source region 21 is generally high concentration, (1-5) × 1019cm-3About, when the specific application, the doping concentration can be selected to be 1 × 1019cm-3、2×1019cm-3、3×1019cm-3、4×1019cm-3、5×1019cm-3、1.5×1019cm-3、2.4×1019cm-3And the ohmic contact resistance of the MOSFET device can be reduced, and the emission efficiency can be increased.
Example 12
This embodiment provides an N-channel trench-gate power UMOS transistor and a method for manufacturing the same, referring to fig. 3, a trench-gate power UMOS transistor is provided, in which a drift layer 12 doped with a second conductivity type, a buffer layer 13 doped with the second conductivity type, a substrate 14 doped with the second conductivity type and a drain 33 are sequentially connected, a gate 32 is disposed on the top of a polysilicon layer 10, the polysilicon layer 10 is U-shaped, the outside of the polysilicon layer 10 is surrounded by a trench-type insulated gate 11, a region formed by the polysilicon layer 10 and the trench-type insulated gate 11 is located in the middle of the top of the drift layer 12 doped with the second conductivity type, a semi-insulating region 222 and a base region 22 doped with a first conductivity type are symmetrically disposed on both sides of the region formed by the polysilicon layer 10 and the trench-type insulated gate 11 on the top of the drift layer 12 doped with the second conductivity type, a source region 21 doped with the second conductivity type is located on the top of the base region 22 and the semi-insulating, the top of the second conductivity type doped source region 21 is provided with a source 31.
The first conduction type is P type, and injects trivalent element boron or aluminum, the second conduction type is N type, injects pentavalent element nitrogen or phosphorus, the groove grid power UMOS transistor is made of one of bulk silicon, silicon carbide, gallium arsenide, indium phosphide, germanium silicon semiconductor material.
A preparation method of an N-channel groove gate power UMOS transistor comprises the following preparation steps:
1) selecting N-type SiC epitaxial wafer with doping concentration of 5 × 1017cm-3Corresponding to the substrate 14 doped with the second conductivity type, 3 x 1018cm-3N of (A)+Buffer layer (corresponding to buffer layer 13 doped with the second conductivity type), 1 × 1016cm-3N of (A)-A drift layer (corresponding to the drift layer 12 doped with the second conductivity type);
2) implanting boron ions or aluminum ions to form a P base region on the SiC epitaxial wafer by adopting an ion implantation process at room temperature for three times, wherein the dosage range of the implanted boron ions or aluminum ions is 1 multiplied by 1010～1×1014cm-2In specific application, the ion dosage can be selected as follows: 1X 1010cm-2、2×1011cm-2、1×1012cm-2、1×1013cm-2、1×1014cm-2And the like.
After ion implantation, annealing under the vacuum condition of argon protection and covering a carbon film on the surface of an epitaxial layer (corresponding to the drift layer 12 doped with the second conductive type), wherein the annealing temperature is 1500 ℃, and the annealing time is about 30 minutes, so that the activation of implanted boron ions or aluminum ions is fully ensured, and no volatilization escape exists;
3) formation of semi-insulating regions 222;
a. utilizing the shielding effect of a mask plate to implant quinvalent element nitrogen or phosphorus with the same concentration and depth as those of the P base region formed in the step 2) at the outer side of the channel region (corresponding to the base region 22 doped with the first conductive type), namely, the concentration is 1 multiplied by 1010～1×1014cm-2Forming an electrically neutral region;
b. continuing to ion implant an amphoteric dopant-vanadium over the formed electrically neutral region to form a semi-insulating region 222, the amphoteric dopant being implanted to a depth consistent with the electrically neutral region;
c. and implanting pentavalent nitrogen or phosphorus on the semi-insulating region 222 and the base region 22 doped with the first conductivity type by using three ion implantation processes at room temperature to form a source region (corresponding to the source region 21 doped with the second conductivity type) of the UMOS transistor, wherein the implantation energy is between 10keV and 50keV, and specifically, the implantation energy is 10keV, 50keV, 20keV, 15keV and other values. After ion implantation, annealing is carried out under the vacuum condition of argon protection and carbon film covering on the surface of the epitaxial layer, the annealing temperature is 1500 ℃, the time is about 30 minutes, and the activation of implanted nitrogen ions or phosphorus ions is fully ensured without volatilization escape.
4) Forming a U-shaped groove structure by adopting a grooving process, growing an oxide layer by wet-oxygen oxidation at 950 ℃, and then thinning the thickness of the U-shaped oxide layer on the inner wall side of the groove gate to 50nm by adopting a corrosion process to form an oxide layer (corresponding to a groove-shaped insulated gate 11) of the groove gate power UMOS transistor;
5) depositing polysilicon in the U-shaped groove of the gate by adopting a PECVD (plasma enhanced chemical vapor deposition) mode to form a polysilicon layer 10;
6) preparing an ohmic electrode;
and plating a metal layer on the SiC epitaxial wafer under the protection of a mask by utilizing a magnetron sputtering process to form a source electrode 31, a grid electrode 32 and a drain electrode 33 in the graph of fig. 3, and then performing rapid annealing in an annealing furnace by utilizing argon as protective gas at the temperature of 1160 ℃ for 6 minutes to form ohmic contact with good performance.
The avalanche breakdown time of the groove gate power UMOS transistor prepared by the method is 36 microseconds, and the breakdown voltage is improved by 35%.
Example 13
This embodiment provides a P-channel trench-gate power UMOS transistor and a method for manufacturing the same, and with reference to fig. 3, the structure of the P-channel trench-gate power UMOS transistor in embodiment 12 is similar to that of the P-channel trench-gate power UMOS transistor in embodiment 12, where the first conductivity type is N-type, and the pentavalent element nitrogen or phosphorus is implanted, and the second conductivity type is P-type, and the trivalent element boron or aluminum is implanted, and the trench-gate power UMOS transistor is made of one of bulk silicon, silicon carbide, gallium arsenide, indium phosphide, and silicon germanium semiconductor materials.
A preparation method of a P-channel groove gate power UMOS transistor comprises the following preparation steps:
1) selecting P-type SiC epitaxial wafer with doping concentration of 5 × 1017cm-3P-type substrate (corresponding to the second conductivity type doped substrate 14), 3 x 1018cm-3P of+Buffer layer (corresponding to buffer layer 13 doped with the second conductivity type), 1 × 1016cm-3P of-A drift layer (corresponding to the drift layer 12 doped with the second conductivity type);
2) implanting nitrogen or phosphorus on the SiC epitaxial wafer by adopting an ion implantation process at room temperature for three times to form an N base region, wherein the dosage range of the implanted nitrogen or phosphorus is 1 multiplied by 1010～1×1014cm-2In specific application, the ion dosage can be selected as follows: 1X 1010cm-2、2×1011cm-2、1×1012cm-2、1×1013cm-2、1×1014cm-2And the like. After ion implantation, annealing under the vacuum condition of argon protection and covering a carbon film on the surface of an epitaxial layer (corresponding to the drift layer 12 doped with the second conductive type), wherein the annealing temperature is 1500 ℃, and the annealing time is about 30 minutes, so that the activation of the implanted nitrogen or phosphorus is fully ensured, and no volatilization escape exists;
3) formation of semi-insulating regions 222;
a. injecting boron or aluminum with the same concentration and depth as the N base region formed in the step 2 into the outer side of the channel region (corresponding to the base region 22 doped with the first conductive type) by using the shielding effect of the mask plate to form an electric neutral region;
b. continuing to ion implant an amphoteric dopant-vanadium over the formed electrically neutral region to form a semi-insulating region 222, the amphoteric dopant being implanted to a depth consistent with the electrically neutral region;
c. implanting boron or aluminum on the semi-insulating region 222 and the first conductive type doped base region 22 by adopting an ion implantation process at room temperature for three times to form a source region (corresponding to the second conductive type doped source region 21) of the UMOS transistor, wherein the implantation energy is between 10keV and 50keV, and after ion implantation, annealing is performed under the vacuum conditions of argon protection and carbon film covering on the surface of an epitaxial layer, the annealing temperature is 1500 ℃, the annealing time is about 30 minutes, and the activation of implanted nitrogen ions or phosphorus ions is fully ensured without volatilization escape.
4) Forming a U-shaped groove structure by adopting a grooving process, growing an oxide layer by wet-oxygen oxidation at 950 ℃, and then thinning the thickness of the U-shaped oxide layer on the inner wall side of the groove gate to 50nm by adopting a corrosion process to form an oxide layer (corresponding to a groove-shaped insulated gate 11) of the groove gate power UMOS transistor;
5) depositing polysilicon in the U-shaped groove of the gate by adopting a PECVD (plasma enhanced chemical vapor deposition) mode to form a polysilicon layer 10;
6) preparing an ohmic electrode;
and plating a metal layer on the SiC epitaxial wafer under the protection of a mask by utilizing a magnetron sputtering process to form a source electrode 31, a grid electrode 32 and a drain electrode 33 in the graph of fig. 3, and then performing rapid annealing in an annealing furnace by utilizing argon as protective gas at the temperature of 1160 ℃ for 6 minutes to form ohmic contact with good performance.
The avalanche breakdown time of the groove gate power UMOS transistor prepared by the method is 36 microseconds, and the breakdown voltage is improved by 35%.
Example 14
This embodiment provides an N-channel trench gate power VMOS transistor and a method for fabricating the same, referring to fig. 4, an N-channel trench gate power VMOS transistor is formed by sequentially connecting a second conductive type doped drift layer 12, a second conductive type doped buffer layer 13, a second conductive type doped substrate 14 and a drain 33, wherein a gate 32 is disposed on a top of a polysilicon layer 10, the polysilicon layer 10 is triangular, the outside of the polysilicon layer 10 is surrounded by a trench type insulated gate 11 except the top, a region formed by the polysilicon layer 10 and the trench type insulated gate 11 is located in the middle of the top of the second conductive type doped drift layer 12, a semi-insulating region 222 and a first conductive type doped region 22 are symmetrically disposed side by side on two sides of the region formed by the polysilicon layer 10 and the trench type insulated gate 11 on the top of the second conductive type doped drift layer 12, a second conductive type doped source region 21 is located on top of the first conductive type doped base region 22 and the semi-insulating region 222 disposed side by side, the top of the second conductivity type doped source region 21 is provided with a source 31.
The first conduction type is P type, and injects trivalent element boron or aluminum, the second conduction type is N type, injects pentavalent element nitrogen or phosphorus, the groove grid power UMOS transistor is made of one of bulk silicon, silicon carbide, gallium arsenide, indium phosphide, germanium silicon semiconductor material.
A preparation method of an N-channel groove gate power VMOS transistor comprises the following preparation steps:
1) selecting N-type SiC epitaxial wafer with doping concentration of 5 × 1017cm-3Corresponding to the substrate 14 doped with the second conductivity type, 3 x 1018cm-3N of (A)+Buffer layer (corresponding to buffer layer 13 doped with the second conductivity type), 1 × 1016cm-3N of (A)-A drift layer (corresponding to the drift layer 12 doped with the second conductivity type);
2) implanting boron or aluminum to form a P base region on the SiC epitaxial layer by adopting an ion implantation process at room temperature for three times, wherein the dosage range of the implanted boron ions or aluminum ions is 1 multiplied by 1010～1×1014cm-2In specific application, the ion dosage can be selected as follows: 1X 1010cm-2、2×1011cm-2、1×1012cm-2、1×1013cm-2、1×1014cm-2And the like. After ion implantation, annealing under the vacuum condition of argon protection and carbon film covering on the surface of the epitaxial layer, wherein the annealing temperature is 1500 ℃, and the annealing time is about 30 minutes, so that the activation of the implanted boron ions or aluminum ions is fully ensured, and no volatilization escape exists;
3) formation of semi-insulating regions 222;
a. utilizing the shielding effect of a mask plate to implant quinvalent element nitrogen or phosphorus with the same concentration and depth as those of the P base region formed in the step 2) at the outer side of the channel region (corresponding to the base region 22 doped with the first conductive type), namely, the concentration is 1 multiplied by 1010～1×1014cm-2Forming an electrically neutral region;
b. continuing to ion implant an amphoteric dopant-vanadium over the formed electrically neutral region to form a semi-insulating region 222, the amphoteric dopant being implanted to a depth consistent with the electrically neutral region;
c. implanting quinvalent elements of nitrogen or phosphorus on the semi-insulating region 222 and the base region 22 doped with the first conductive type by adopting an ion implantation process at room temperature for three times to form a source region (corresponding to the source region 21 doped with the second conductive type) of the VMOS transistor, wherein the implantation energy is between 10keV and 50keV, and after ion implantation, annealing is carried out under the vacuum condition of argon protection and carbon film covering on the surface of an epitaxial layer, wherein the annealing temperature is 1500 ℃ and the time is about 30 minutes, so that the implanted nitrogen ions or phosphorus ions are fully ensured to be activated and not volatilized and escaped.
4) Forming a V-shaped groove structure by adopting a grooving process, growing an oxide layer by wet-oxygen oxidation at 950 ℃, and then thinning the thickness of the V-shaped oxide layer on the inner wall side of the groove gate to 50nm by adopting a corrosion process to form an oxide layer (corresponding to the groove-shaped insulated gate 11 in the figure 4) of the groove gate power VMOS transistor;
5) depositing polysilicon in the V-shaped groove of the grid in a PECVD (plasma enhanced chemical vapor deposition) manner to form a polysilicon layer 10;
6) preparing an ohmic electrode;
and plating a metal layer on the SiC epitaxial wafer under the protection of a mask by utilizing a magnetron sputtering process to form a source electrode 31, a grid electrode 32 and a drain electrode 33 in the graph of FIG. 4, and then performing rapid annealing in an annealing furnace by utilizing argon as protective gas at the temperature of 1160 ℃ for 6 minutes to form ohmic contact with good performance.
The avalanche breakdown time of the trench gate VMOS transistor shown in FIG. 4 prepared by the method is 36 microseconds, and the breakdown voltage is improved by 35%. ' Qiyi
Example 15
The present embodiment provides a P-channel trench-gate power VMOS transistor and a method for manufacturing the same, and with reference to fig. 4, the structure of the P-channel trench-gate power VMOS transistor is the same as that of the trench-gate power VMOS transistor in embodiment 14, where the first conductivity type is N-type, and the pentavalent element nitrogen or phosphorus is injected, the second conductivity type is P-type, and the trivalent element boron or aluminum is injected, and the trench-gate power VMOS transistor is made of one of bulk silicon, silicon carbide, gallium arsenide, indium phosphide, and silicon germanium semiconductor materials.
A preparation method of a P-channel groove gate power UMOS transistor comprises the following preparation steps:
1) selecting P-type SiC epitaxial wafer with doping concentration of 5 × 1017cm-3P-type substrate (corresponding to the second conductivity type doped substrate 14), 3 x 1018cm-3P of+Buffer layer (corresponding to buffer layer 13 doped with the second conductivity type), 1 × 1016cm-3P of-A drift layer (corresponding to the drift layer 12 doped with the second conductivity type);
2) implanting nitrogen or phosphorus to form an N base region on the SiC epitaxial layer by adopting an ion implantation process at room temperature for three times, wherein the dosage range of the implanted nitrogen or phosphorus is 1 multiplied by 1010～1×1014cm-2In specific application, the ion dosage can be selected as follows: 1X 1010cm-2、2×1011cm-2、1×1012cm-2、1×1013cm-2、1×1014cm-2And the like. After ion implantation, annealing under the vacuum condition of argon protection and carbon film covering on the surface of the epitaxial layer, wherein the annealing temperature is 1500 ℃, and the annealing time is about 30 minutes, so that the activation of the implanted nitrogen or phosphorus is fully ensured, and no volatilization escape exists;
3) formation of semi-insulating regions 222;
a. implanting boron or aluminum with the same concentration and depth as those of the N base region formed in step 2) outside the channel region (corresponding to the base region 22 doped with the first conductivity type) by using the shielding effect of the mask, i.e., with a concentration of 1 × 1010～1×1014cm-2Forming an electrically neutral region;
b. continuing to ion implant an amphoteric dopant-vanadium over the formed electrically neutral region to form a semi-insulating region 222, the amphoteric dopant being implanted to a depth consistent with the electrically neutral region;
c. implanting boron or aluminum on the semi-insulating region 222 and the first conductive type doped base region 22 by adopting an ion implantation process at room temperature for three times to form a source region (corresponding to the second conductive type doped source region 21) of the VMOS transistor, wherein the implantation energy is between 10keV and 50keV, annealing is performed under the vacuum conditions of argon protection and carbon film covering on the surface of an epitaxial layer after ion implantation, the annealing temperature is 1500 ℃, and the annealing time is about 30 minutes, so that the activation of the implanted boron or aluminum is fully ensured and no volatile escape exists.
4) Forming a V-shaped groove structure by adopting a grooving process, growing an oxide layer by wet-oxygen oxidation at 950 ℃, and then thinning the thickness of the V-shaped oxide layer on the inner wall side of the groove gate to 50nm by adopting a corrosion process to form an oxide layer (corresponding to the groove-shaped insulated gate 11 in the figure 4) of the groove gate power VMOS transistor;
5) depositing polysilicon in the V-shaped groove of the grid in a PECVD (plasma enhanced chemical vapor deposition) manner to form a polysilicon layer 10;
6) preparing an ohmic electrode;
and plating a metal layer on the SiC epitaxial wafer under the protection of a mask by utilizing a magnetron sputtering process to form a source electrode 31, a grid electrode 32 and a drain electrode 33 in the graph of FIG. 4, and then performing rapid annealing in an annealing furnace by utilizing argon as protective gas at the temperature of 1160 ℃ for 6 minutes to form ohmic contact with good performance. The avalanche breakdown time of the trench gate VMOS transistor shown in FIG. 3 prepared by the method is 36 microseconds, and the breakdown voltage is improved by 35%.
The present invention and its embodiments have been described above schematically, without limitation, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. Therefore, if the person skilled in the art receives the teaching, without departing from the spirit of the invention, the person skilled in the art shall not inventively design the similar structural modes and embodiments to the technical solution, but shall fall within the scope of the invention.

Claims (10)

1. A trench gate power MOS transistor comprising a semi-insulating region, comprising a source region (21) doped with a second conductivity type, a base region (22) doped with a first conductivity type and a semi-insulating region (222), wherein the source region (21) doped with the second conductivity type is located above the base region (22) doped with the first conductivity type and the semi-insulating region (222) which are arranged side by side, and the semi-insulating region is generated by the following steps: A. implanting impurities of a first conductivity type into a drift region (12) of a second conductivity type; B. implanting impurity elements of a second conductivity type into the outer side of the base region (22) doped with the first conductivity type to form an electrically neutral region; C. continuing to implant amphoteric impurity elements on the electrically neutral regions to form semi-insulating regions (222); the bottom of the semi-insulating region (222) is in contact with a drift region (12) doped with the second conductivity type.
2. A trench-gate power MOS transistor comprising a semi-insulating region according to claim 1, characterized in that the width of the source region (21) doped with the second conductivity type is equal to the sum of the widths of the base region (22) doped with the first conductivity type and the semi-insulating region (222).
3. A trench-gate power MOS transistor comprising a semi-insulating region according to claim 1, characterized in that the depth of the first conductivity type doped base region (22) is the same as the depth of the semi-insulating region (222).
4. The power MOS transistor with trench gate having semi-insulating region of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type.
5. A trench-gate power MOS transistor comprising a semi-insulating region according to claim 1, characterized in that the ratio of the widths of the first conductivity type doped base region (22) and the second conductivity type doped source region (21) is 1: 1-3.
6. The power MOS transistor with trench gate having semi-insulating region as claimed in any of claims 1-5, wherein the power MOS transistor with trench gate is made of a semiconductor material selected from bulk silicon, silicon carbide, gallium arsenide, indium phosphide and silicon germanium.
7. A preparation method of a groove gate power MOS transistor containing a semi-insulating region is characterized by comprising the following steps:
A. implanting impurities of a first conductivity type into a drift region (12) of a second conductivity type;
B. implanting impurity elements of a second conductivity type into the outer side of the base region (22) doped with the first conductivity type to form an electrically neutral region;
C. continuing to implant amphoteric impurity elements on the electrically neutral regions to form semi-insulating regions (222);
D. implanting impurities of a second conductivity type into the semi-insulating region (222) and the base region (22) doped with the first conductivity type to form a source region (21) doped with the second conductivity type;
E. forming an insulated gate (11) and a polysilicon region (10);
F. three metal electrodes of a source (31), a grid (32) and a drain (33) of the groove grid power MOS transistor are formed.
8. The method of claim 7, wherein the depth of the impurity element of the second conductivity type implanted in step B is substantially the same as the depth of the impurity element of the first conductivity type ion-implanted in step A.
9. The method of claim 7, wherein the implanting of the impurity in steps A and B is a plurality of ion implantations to form a box-type doping profile.
10. Method for manufacturing a trench-gate power MOS transistor comprising a semi-insulating region according to claim 7, characterized in that the doping concentration of the doped base region (22) of the first conductivity type is 5 x 1016cm-3～5×1017cm-3In the meantime.
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