CN108681516B

CN108681516B - Method for improving transmission speed of MIPI protocol layer, MIPI interface for quick transmission and computer readable storage medium

Info

Publication number: CN108681516B
Application number: CN201810279140.5A
Authority: CN
Inventors: 夏群兵; 梁丕树; 朱道林
Original assignee: Shenzhen Aixiesheng Technology Co Ltd
Current assignee: Shenzhen Aixiesheng Technology Co Ltd
Priority date: 2018-03-30
Filing date: 2018-03-30
Publication date: 2021-05-18
Anticipated expiration: 2038-03-30
Also published as: CN108681516A

Abstract

The invention relates to the technical field of data transmission of display screen interfaces, in particular to a MIPI (mobile industry processor interface) for fast transmission. When the data transmission of the protocol layer is carried out, a parallel structure is adopted, a plurality of data from different channels of the physical layer are respectively written into different first-in first-out queues FIFO, then the written data are respectively read from the first-in first-out queues FIFO, the difference between the clock frequency BYTE _ CLK of the written data and the clock frequency D _ CLK of the read data is not large, frequency doubling processing is not needed, and the design difficulty and the process requirement are greatly reduced. And the frequency multiplication processing of HS _ CLK clock frequency is not needed when the data are read in parallel, so that the method is easy to realize and is beneficial to improving the transmission speed of MIPI.

Description

Method for improving transmission speed of MIPI protocol layer, MIPI interface for quick transmission and computer readable storage medium

Technical Field

The invention relates to the technical field of data transmission of display screen interfaces, in particular to a MIPI (mobile industry processor interface) for fast transmission.

Background

Display screens with resolutions higher than HD have become the mainstream in the market. In the aspect of display screen interfaces, the conventional interfaces such as RGB, DBI and the like cannot meet the requirements of high resolution and high refresh rate. The MIPI interface has become a standard configuration of a high-resolution display screen due to the advantages of simple connection structure, high transmission speed, strong anti-interference capability and the like. The resolution is higher and higher from VGA to WQHD, and the requirement on the speed of an MIPI interface is stricter and stricter. There are generally two methods for implementing high resolution through an MIPI interface: firstly, the MIPI transmission speed is improved; the other is to use multiple sets of MIPI, however, connecting multiple sets of MIPI makes the circuit complicated and costly, and is only considered if the transmission speed of the MIPI cannot be increased.

The MIPI is a protocol for transmitting video display data, a physical layer PHY of the MIPI provides synchronous physical connection between a host and a slave, a common physical layer PHY configuration comprises a clock channel and one to four data channels, the clock channel is unidirectional, and the data channels can be unidirectional or bidirectional. Taking the four-channel MIPI in fig. 1 as an example, in the conventional design method, the processing of the Protocol layer is to concatenate the data sent in parallel by the PHY layer with a higher frequency clock, that is, the data sent in parallel by the PHY layer is written into a FIFO at a clock frequency BYTE _ CLK, and then the data is serially read out from the FIFO to the Protocol of the Protocol layer for processing with a faster clock frequency HS _ CLK, where a specific implementation manner of serial transmission of BYTE data is shown in fig. 2. The HS _ CLK clock frequency needs to be multiplied, so that the HS _ CLK clock frequency is kept to be N (1-4) times of the first-in first-out queue FIFO clock frequency BYTE _ CLK, wherein N is the number of channels of the physical layer PHY. The higher the number of channels, the faster the HS _ CLK frequency required by the protocol layer, and the more difficult the implementation of the process, which greatly limits the transmission speed of MIPI.

Disclosure of Invention

The invention aims to provide a method for improving the transmission speed of an MIPI protocol layer and an MIPI interface for realizing quick transmission by the method.

The invention realizes the improvement of the transmission speed of the MIPI protocol layer through the following steps,

a data writing step: respectively writing a plurality of data from different channels of a physical layer into different first-in first-out queues (FIFO) in a protocol layer;

a parallel reading step: reading the written data from the first-in first-out queues FIFO respectively;

if the data is written into a FIFO at the clock frequency BYTE _ CLK in the data writing step, the data is read out from the FIFO at the clock frequency D _ CLK in the parallel reading step, the clock frequency D _ CLK being equal to the clock frequency BYTE _ CLK or lower than twice the clock frequency BYTE _ CLK.

Preferably, in the data writing step, the data from the different channels of the physical layer are written into the FIFO in one-to-one correspondence to the channels of the physical layer at the same clock frequency BYTE _ CLK.

Preferably, in the parallel reading step, data is read from each FIFO at the same clock frequency D _ CLK.

Preferably, the number of the first-in first-out queue FIFOs is greater than or equal to the number of channels of the physical layer.

Preferably, further comprising the step of performing after the parallel read-out step,

a data packet obtaining step: transmitting the data read from the respective first-in first-out queues FIFO to a Protocol of a Protocol layer for processing the data;

MIPI identification: the Protocol of the Protocol layer identifies the received Data, divides the received Data into different Data packets according to the first-in first-out queue FIFO of the Data source, and arranges all the Data packets from the first-in first-out queue FIFO of the same channel corresponding to the physical layer according to the clock sequence, thereby obtaining the Data Lane of each channel of the physical layer.

Preferably, the total number of physical layer channels is defined as X, DT _ LN is a channel marking value in the current data packet, and CNT is the number of bytes of the long packet minus the packet header; the MIPI identification step includes the sub-steps of,

data packet identification: the Protocol of the Protocol layer identifies the length of the current data packet;

DATAID positioning step: if the current data packet is identified as a long packet, the following data transmitted by the A1 th time (CNT + DT _ LN)/X clocks is determined as DATAID data, and the value CDT of the channel where the DATAID data of the long packet is located is the remainder obtained by dividing CNT by X.

Preferably, if the current packet is identified as an EOT short packet in the packet identification step, the DATA transmitted by the subsequent 1 st bit clock of the current channel DT _ LN is determined as DATA ID DATA in the subsequent DATAID locating step.

Preferably, if the current packet is identified as a short packet other than EOT in the packet identification step, in the subsequent DATA ID locating step, the DATA transmitted at the subsequent a2 th clock (4-X) is determined as DATA ID DATA, and the value DDT of the channel in which the DATA ID DATA of the short packet other than EOT is located is equal to the channel flag value DT _ LN in the current packet.

The invention also provides a computer readable storage medium, in which a program is stored, and when the program is processed and executed, the method for improving the transmission speed of the MIPI protocol layer is realized.

The invention also provides a fast-transmitting MIPI interface comprising a processor and the above computer-readable storage medium, a computer program on the computer-readable storage medium being executable by the processor.

Has the advantages that: the invention adopts a parallel structure when data transmission is carried out between a physical layer and a protocol layer, a plurality of data from different channels of the physical layer are respectively written into different first-in first-out queues FIFO, and then the written data are respectively read from the first-in first-out queues FIFO, the difference between the clock frequency BYTE _ CLK of the written data and the clock frequency D _ CLK of the read data is not large, frequency doubling processing is not needed, and the design difficulty and the process requirement are greatly reduced. When data are read in parallel, frequency multiplication processing of HS _ CLK clock frequency is not needed, the method is easy to realize, and the transmission speed of MIPI can be improved.

Drawings

Fig. 1 is a schematic diagram of serial transmission of Byte data at the protocol layer of a three-channel MIPI.

Fig. 2 is a schematic diagram of data serial transmission at the protocol layer of a four-lane MIPI.

Fig. 3 is a schematic diagram of parallel transmission of data at the protocol layers of a four-lane MIPI.

Fig. 4 is a diagram of a DATA ID positioning flow for parallel transmission by a single channel MIPI protocol layer.

Fig. 5 is a diagram illustrating a DATA ID location process for parallel transmission by two-channel MIPI protocol layers.

Fig. 6 is a schematic diagram of a DATAID positioning process for parallel transmission of three-channel MIPI protocol layers.

Fig. 7 is a diagram illustrating a DATAID positioning procedure for parallel transmission at a four-lane MIPI protocol layer.

Detailed Description

The invention is further described with reference to the following examples.

As shown in fig. 3, the fast-transmission MIPI interface can achieve the improvement of the transmission speed of the MIPI protocol layer by the following steps.

A data writing step: respectively writing a plurality of data from different channels of a physical layer into different first-in first-out queues (FIFO);

a data packet obtaining step: transmitting the data read from each FIFO queue to the Protocol of the Protocol layer;

MIPI identification: the Protocol of the Protocol layer identifies the received Data and stores the received Data as Data packets of channels corresponding to the FIFO of the Data source respectively, and the Data packets are arranged according to the clock to obtain the Data Lane of each channel.

By the method for improving the transmission speed of the MIPI protocol layer, a parallel structure is adopted during data transmission of the protocol layer, a plurality of data from different channels of the physical layer are respectively written into different first-in first-out queues (FIFO), then the written data are respectively read from the FIFO, the difference between the clock frequency BYTE _ CLK of the written data and the clock frequency D _ CLK of the read data is not large, frequency doubling is not needed, and design difficulty and process requirements are greatly reduced. When data are read in parallel, frequency multiplication processing of HS _ CLK clock frequency is not needed, the method is easy to realize, and the transmission speed of MIPI can be improved.

If the data is written into a first-in first-out queue FIFO at the clock frequency BYTE _ CLK in the data writing step, the data is read out from the first-in first-out queue FIFO at the clock frequency D _ CLK in the parallel reading step, wherein the clock frequency D _ CLK is equal to or slightly larger than the clock frequency BYTE _ CLK.

In the data writing step, data from different channels of the physical layer are written into first-in first-out queues (FIFO) corresponding to the channels of each physical layer by using the same clock frequency BYTE _ CLK; in the parallel reading step, data is also read from each FIFO at the same clock frequency D _ CLK. And the number of the first-in first-out queues FIFO of the protocol layer is equal to the number of the channels of the physical layer, so that the multiple channels of the physical layer can transmit data simultaneously, and the number of the first-in first-out queues FIFO of the protocol layer can be larger than the number of the channels of the physical layer.

Although the parallel structure method can improve the processing speed, the method brings difficulties to DATAID positioning, ECC and CHECKSUM calculation, and the problems are related to the number of channels in work. The protocol layer performs further processing on the data to be transmitted from the physical layer channel, defining how the byte stream is composed into data packets, and how the header of each packet is generated. The protocol layer of the sender generates a packet header and error correction information; the data is transmitted to the receiving party, the information in the packet header is analyzed, and the information of the error correction part is used for testing the integrity of the data transmission.

Specifically, the long packet format: a long packet consists of a 32-bit (4Byte) header, an N-Byte data field, and a 16-bit CRC; a short packet contains only a 32-bit (4Byte) header. Wherein, the packet header is composed of 8-bit data identifier + 16-bit count value + 8-bit ECC; the DATA identifier DATA ID is constituted by a 2-bit virtual channel number + 6-bit DATA type. The 8-bit ECC enables the first 24 bits (8-bit data identifier + 16-bit counter value) of the packet header to be detected when two-bit errors occur in the transmission process and to be directly corrected when one-bit errors occur. The 16-bit CRC is a 16-bit cyclic redundancy check code and can indicate whether the received packet data is erroneous during transmission.

Defining the total number of physical layer channels as X, DT _ LN as the channel marking value in the current data packet, CNT as the number of bytes of the long packet after deducting the packet header. DT _ LN ═ 0, indicating that DATAID is in channel 1; DT _ LN ═ 1, indicating DATA ID is in lane 2; DT _ LN ═ 2, indicating DATA ID is in the third channel; DT _ LN equals 3, indicating DATA ID is in channel 4. CNT indicates the number of bytes (including cheksum) that will be sent later after the header of the long packet is sent out.

The MIPI identification step also comprises a DATA packet identification step, a DATA ID positioning step and a verification step.

Specifically, if the Protocol of the Protocol layer recognizes that the current packet is a long packet, it determines that the DATA transmitted by the following a1 ═ X clocks (CNT + DT _ LN)/X clocks is DATA ID DATA, and the value CDT of the channel where the DATA ID DATA is located is the remainder obtained by dividing CNT by X; if the Protocol of the Protocol layer identifies that the current DATA packet is an EOT short packet, determining that DATA transmitted by a subsequent 1 st bit clock of the current channel DT _ LN is DATA ID DATA in a subsequent DATA ID positioning step; if the Protocol of the Protocol layer recognizes that the current DATA packet is a short packet but not an EOT, in the subsequent DATAID locating step, it is determined that the DATA transmitted by the subsequent a2 th (4-X) clock is DATA ID DATA, and the value DDT of the channel in which the DATA ID DATA is located is equal to the channel flag value DT _ LN in the current DATA packet.

The checking step includes the CHECKSUM and CRC check. The CHECKSUM judges whether the data transmission is finished according to the number of channels, the last clock and the DT _ LN, if the data transmission is finished, the calculation is also finished, and the 16-bit result is the CHECKSUM. The CRC _ END is used to determine which channel ENDs, and the CRC _ END is 0, which indicates that the last BYTE is in the 1 st channel; CRC _ END ═ 1, indicating that the last BYTE is in lane 2; CRC _ END ═ 2, indicating that the last BYTE is on the third channel; CRC _ END ═ 3, indicating that the last BYTE is on lane 4.

As shown in fig. 4, in the process of parallel transmission in a single-channel MIPI Protocol layer, X is 1, a Protocol in the Protocol layer performs sequence judgment after acquiring a DATA packet, continues to identify the DATA packet after the sequence judgment is successful, and judges whether the DATA packet only includes a 32-bit (4Byte) header under the current clock, that is, judges whether the DATA packet is a short packet, and if not, indicates that the DATA packet is normally transmitted.

As shown in fig. 5, in the process of parallel transmission of the dual-channel MIPI Protocol layer, X is 2, and after acquiring a data packet, the Protocol of the Protocol layer sequentially performs sequence determination and short packet determination. If the DATA packet is judged to be a short packet, judging whether the short packet is EOT under the current channel DT _ LN, finishing the judging process if the short packet is confirmed to be EOT, and confirming that the DATA transmitted by the 1 st bit clock is DATA ID DATA, wherein the value corresponding to CRC _ END is the position of the channel where the last DATA is located. If the DATA packet is determined to be a short packet but not an EOT, the DATA transmitted by the following a2 th (4-X) clock is determined to be DATA ID DATA, and the value DDT of the channel in which the DATA ID DATA is located is equal to the channel marker value DT _ LN in the current DATA packet. And then, jumping back to the current channel DT _ LN to judge the short packet again until the data packet is judged to be an EOT short packet. If the DATA packet is judged to be a long packet, the clock position of the DATA identifier DATA ID is calculated according to the condition that A1 is equal to (CNT + DT _ LN)/2, the value of A1 can also be adjusted according to the actual arrangement condition of the DATA packet, at this time, the value CDT of the channel DT _ LN where the DATA ID DATA is located is obtained according to the remainder of dividing CNT by 2 (namely X is equal to 2), and the short packet judgment is continued to be carried out under the channel value until the DATA packet is judged to be an EOT short packet.

The three-channel and four-channel MIPI protocol layer parallel transmission flows shown in fig. 6 and 7 can be analogized from the two-channel MIPI protocol layer parallel transmission process of fig. 5.

Claims

1. The method for improving the transmission speed of the MIPI protocol layer is characterized by comprising the following steps,

if the data is written into a first-in first-out queue FIFO at the clock frequency BYTE _ CLK in the data writing step, the data is read out from the first-in first-out queue FIFO at the clock frequency D _ CLK in the parallel reading step, wherein the clock frequency D _ CLK is equal to the clock frequency BYTE _ CLK or lower than twice the clock frequency BYTE _ CLK;

further comprising the following steps performed after the parallel read-out step,

MIPI identification: the Protocol of the Protocol layer identifies the received Data, divides the received Data into different Data packets according to the first-in first-out queue FIFO of the Data source, and arranges all the Data packets from the first-in first-out queue FIFO of the same channel corresponding to the physical layer according to the clock sequence, thereby obtaining the Data Lane of each channel of the physical layer;

defining the total number of physical layer channels as X, DT _ LN as a channel marking value in the current data packet, and CNT as the number of bytes of the long packet after deducting the packet header; the MIPI identification step includes the sub-steps of,

and a step of positioning the DATA ID: if the current DATA packet is identified as a long packet, the DATA transmitted by the following A1 th time (CNT + DT _ LN)/X clocks is determined as the DATA ID DATA, and the value CDT of the channel where the DATA ID DATA of the long packet is located is the remainder obtained by dividing CNT by X.

2. The method of increasing the transmission speed of MIPI protocol layer of claim 1, wherein in the data writing step, the data from different channels of the physical layer are written into the FIFO queue corresponding to the channels of the physical layer one by one with the same clock frequency BYTE _ CLK.

3. The method for increasing the transmission speed of MIPI protocol layers in accordance with claim 1 or 2, wherein in the parallel reading step, data is read from each FIFO queue at the same clock frequency D _ CLK.

4. The method for increasing the transmission speed of the MIPI protocol layer according to claim 1, wherein the number of the first-in first-out queues (FIFO) is larger than or equal to the number of the channels of the physical layer.

5. The method of claim 1, wherein if the current packet is identified as an EOT short packet in the packet identifying step, the DATA transmitted by the 1 st bit clock of the current channel DT _ LN is determined as DATAID DATA in the subsequent DATA ID locating step.

6. The method of claim 1, wherein if the current packet is identified as a non-EOT short packet in the packet identifying step, the DATA transmitted at the following a2 ═ 4-X number of clocks is determined as DATA ID DATA in the following DATA ID locating step, and a value DDT of a channel on which the DATA ID DATA of the non-EOT short packet is located is equal to a channel flag value DT _ LN in the current packet.

7. A computer-readable storage medium, in which a program is stored, and when the program is executed by a processor, the program implements the method for increasing the transmission speed of the MIPI protocol layer according to any one of claims 1 to 6.

8. A fast-transmitting MIPI interface, comprising a processor and the computer-readable storage medium of claim 7, a computer program on the computer-readable storage medium executable by the processor.