CN108666366A - A superjunction lateral high voltage device with stepped buried oxide layer - Google Patents

Abstract

The invention relates to the technical field of semiconductor power devices, and relates to a super-junction lateral high-voltage device with a stepped buried oxide layer. The lateral high-voltage device with a stepped buried oxide layer of the present invention introduces a stepped buried oxide layer between the N-type drift region and the P-type substrate, and gradually increases from source to drain to better optimize the charge distribution in the drift region , shielding the substrate-assisted depletion effect, so that the superjunction layer achieves charge balance and increases the lateral breakdown voltage of the device. In addition, the stepped buried oxide layer also plays the role of fixing holes, so that the concentration of holes on the interface of the buried layer is greatly increased, so that the electric field of the buried layer is increased, and the vertical breakdown voltage of the device is improved. The beneficial effect of the invention is that it has high pressure resistance and reduces the difficulty of the process at the same time.

Description

A superjunction lateral high voltage device with stepped buried oxide layer

technical field

The invention belongs to the technical field of power semiconductors, and relates to a super-junction lateral high-voltage device with a stepped buried oxide layer.

Background technique

Power semiconductor devices, as the core devices of power electronic systems, are indispensable and important electronic components in modern life. With the broadening of the scope of application, its application field extends from household consumer electronics equipment to various industrial equipment, energy and aerospace and other fields. In recent years, with the rapid development of science and technology, semiconductor technology has gradually formed two branches: one is based on large-scale integrated circuits, which realizes the storage, processing and conversion of information; the other is based on power semiconductor devices. , used in power supply and control circuits to realize the processing and transformation of electric energy.

The full name of a power device is a power semiconductor device or a semiconductor power device. Simply put, it is a semiconductor device that performs power processing and has the ability to handle high voltage and high current. With the development of society, power devices are developing in the direction of high withstand voltage BV and low specific on-resistance R _on,sp . For the currently researched silicon material devices, the specific on-resistance R _on,sp and the withstand voltage BV are related to the power of 2.5 ("silicon limit"), and a high specific on-resistance will reduce the performance of the device.

The miniaturization and integration of power electronic systems has proposed an important direction for the development of power semiconductor devices: intelligent power integrated circuits. It requires the integration of low-voltage circuits such as protection, control, detection, and drive, and high-voltage power devices on a unified chip. Therefore, the size of power devices is required to be smaller and smaller, and the performance of the devices is getting better and better.

Academician Chen Xingbi proposed super-junction power devices, which further optimized the relationship between withstand voltage and specific on-resistance. The superjunction technology is used in the device, that is, the single doped drift region is replaced by highly doped P and N strips. For N-type LDMOS, when the device is in the on state, the highly doped N strips can provide a low-resistance channel, effectively reducing the specific on-resistance of the device. When the device is in the off state, the highly doped P and N strips deplete each other, and the ionized donor ions in the N strip terminate in the ionized acceptor ions in the P region, which increases the surface electric field of the device and enhances the withstand voltage of the device. . However, there is a substrate-assisted depletion effect in conventional super-junction devices, that is, there will be a vertical PN junction between the N-type drift region and the P-type substrate, which will destroy the charge balance between the South P and N bars in the super-junction layer and reduce the performance of the device. pressure resistance. The superjunction lateral high-voltage device with a stepped buried oxide layer is characterized by a stepped buried oxide layer between the P-type substrate and the N-type drift region, which optimizes the charge distribution in the drift region. In addition, the stepped buried oxide layer also plays the role of fixing holes, so that the concentration of holes on the interface of the buried layer is greatly increased, so that the electric field of the buried layer is increased, and the vertical withstand voltage of the device is improved.

Contents of the invention

The purpose of the application of the present invention is to add a stepped buried oxide layer between the N-type drift region and the P-type substrate to improve the withstand voltage of the device and alleviate the "silicon limit" of the device. Step buried oxygen divides the drift region into three parts according to the depth and gradually increases from the source to the drain. The compensation of the drift region to the superjunction layer increases from the source to the drain, optimizes the device charge distribution, and shields the substrate auxiliary The depletion effect can realize the charge balance of the superjunction layer, increase the electric field on the surface of the device, and enhance the lateral withstand voltage of the device. In addition, the stepped buried oxide layer can fix holes in the upper interface of the buried layer, increase the electric field of the buried layer, and improve the withstand voltage of the device.

Technical scheme of the present invention:

A super-junction lateral high-voltage device with a stepped buried oxide layer, its cell structure includes a P-type substrate 1, a buried oxide layer 23, and an N-type drift region 31, wherein the N-type drift region 31 includes a P-type well region 41 , super junction layer 71 , and second N-type heavily doped region 34 .

specific,

The P-type body region 41 includes a P-type heavily doped region 41 and a first N-type heavily doped region 32 , the upper end of which is a source terminal electrode 52 .

specific,

The P-type body region 41 and the polysilicon gate are isolated by the dielectric 21 .

specific,

The super junction layer 71 includes an N-type doped region 33 and a P-type doped region 43 .

specific,

The upper surface of the second N-type heavily doped region 34 is the drain terminal electrode 53 .

specific,

The drain electrode 53 and the polysilicon electrode 61 are separated by the dielectric 22 .

specific,

A drain field plate 81 is provided on the upper surface of the dielectric isolation layer 22 , and the drain field plate 81 is connected to the drain terminal electrode 53 .

specific,

The buried oxide layer 23 isolates the P-type substrate 1 and the N-type drift region 31 , and is distributed according to the step depth gradually increasing from the source end to the drain end, and the steps have three layers in total.

Compared with the prior art, the above-mentioned technical solution has the following advantages:

The invention provides a super junction lateral high voltage device with a stepped buried oxide layer, which introduces a stepped buried oxide layer between the N-type drift region and the P-type substrate. Compared with the traditional technology, the present invention introduces the step-buried oxide layer. The main advantages are: (1) isolation of the N-type drift region and the P-type substrate; (2) step-type distribution, optimizing the charge distribution in the drift region, so that the drift region The charge compensation of the superjunction layer is gradually increased from the source end to the drain end, shielding the auxiliary depletion effect of the device substrate, and realizing the charge balance of the superjunction layer; (3) The buried oxide layer distributed in steps can fix the holes on the upper interface of the buried layer, Increase the charge concentration at the interface of the buried layer to enhance the withstand voltage of the device.

Description of drawings

Fig. 1 is the structural representation of embodiment 1;

Fig. 2 is the structural representation of embodiment 2;

Fig. 3 is the structural representation of embodiment 3;

Fig. 4 is the structural representation of embodiment 4;

Fig. 5 is the structural representation of embodiment 5;

Fig. 6 is the structural representation of embodiment 6;

Fig. 7 is a schematic diagram of the structure of a conventional super-junction lateral high-voltage power device.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Example 1

As shown in FIG. 1 , a superjunction lateral high-voltage device with a stepped buried oxide layer includes a stepped buried oxide layer 23 on a P-type substrate 1 and an N-type drift region 31 disposed on the upper end of the buried oxide layer 23, The N-type drift region 31 is provided with a P-type body region 41, a superjunction layer 71 and a second N-type heavily doped 34, and the P-type body region 41 includes mutually independent first N-type heavily doped regions 42 and a P-type heavily doped region 32, the upper end of the P-type body region 41 is provided with an active metal 52 and a gate oxide layer 21, and the upper end of the gate oxide layer 21 is provided with a polysilicon gate electrode 61, and the super junction layer 71 includes N-type doped strips 33 and P-type doped strips 43, the upper end surface of the second N-type heavily doped 34 is provided with a drain metal 53, and a dielectric layer is passed between the drain metal 53 and the gate oxide layer 21 22, and the upper end surface of the dielectric isolation layer 22 is provided with a drain field plate 81.

Example 2

As shown in FIG. 2 , this embodiment is basically the same as Embodiment 1, except that the shape of the buried oxide layer between the P-type substrate 1 and the N-type drift region 31 becomes a partial step. Compared with Example 1, the self-heating effect of the device is reduced.

Example 3

As shown in FIG. 3 , this embodiment is basically the same as Embodiment 1, except that the super junction layer 71 is located inside the N-type drift region 31 of the device.

Example 4

As shown in FIG. 4 , this embodiment is basically the same as Embodiment 1, except that the super junction layer in the N-type drift region 31 becomes a partial super junction layer, which is located in the left half of the drift region.

Example 5

As shown in FIG. 5 , this embodiment is basically the same as Embodiment 1, except that part of the super junction layer 71 is inside the N-type drift region 31 and is located on the left half of the drift region.

Example 6

As shown in FIG. 6 , this embodiment is basically the same as Embodiment 1, except that the P-bar 43 of the superjunction layer is replaced by a high-K material, which reduces the difficulty of the process.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (2)

1. A kind of oxygen buried layer 23 1. super-junction laterally high tension apparatus with ladder oxygen buried layer, including in P type substrate 1, stepped with And the N-type drift region 31 in 23 upper end of ladder oxygen buried layer is set, it is provided with the areas PXing Ti 41, superjunction floor in the N-type drift region 31 71 and the second N-type heavy doping 34, the areas PXing Ti 41 include that mutually independent first N-type heavily doped region 42 and p-type are heavily doped Miscellaneous area 32,41 upper end of the areas the PXing Ti setting active Metal 52 and gate oxide 21,21 upper end of the gate oxide are provided with more Crystal silicon gate electrode 61, the superjunction layer 71 include that n-type doping item 33 and p-type adulterate item 43,34 upper end of the second N-type heavy doping Face is provided with drain metal 53, is isolated by dielectric layer 22 between the drain metal 53 and gate oxide 21, the medium every 22 upper surface of absciss layer is provided with drain electrode field plate 81.
2. 2. a kind of super-junction laterally high tension apparatus with ladder oxygen buried layer according to claim 1, which is characterized in that described Stepped oxygen buried layer 23, between P type substrate and N-type drift region 31.