CN108665924A - Arrayed silicon-based programmable optical memory chip - Google Patents

Abstract

A kind of array silicon substrate programmable optical storage chip includes successively：Simultaneously decomposing module, the photoelectric conversion module of array, the electric treatment of array and memory module, the Electro-optical Modulation module of array, delay and the adjustable reading optical signal of amplitude and the synthesis module of going here and there of going here and there of optical signal is written.The integrated optical circuit element that module has under its command is integrated in integrated circuit component on the chip system being made of with control chip optical chip, electric storage chip and electrically amplified driving.The input and output of high-speed optical signal are realized by fiber coupling.Electricity memristor and optical delay line are used in combination the present invention, realize the optical random access of ultrahigh speed large capacity, have important supporting role for the exchange of the full light light of large capacity in optical communication system.Chip integration is high, CMOS good compatibilities, is convenient for low-coat scale volume production, has practical value outstanding.

Description

Arrayed silicon-based programmable optical memory chip

technical field

The invention belongs to the field of optical communication, in particular to an arrayed silicon-based programmable optical storage chip.

Background technique

After nearly 30 years of research on optical fiber Dense wavelength division multiplexing (DWDM, Dense wavelength division multiplexing), time division multiplexing technology (OTDM, Optical time division multiplexing), and Erbium Doped Fiber Amplifier (EDFA, Erbium Doped Fiber Amplifier), a single It has become possible to transmit Peta (1e15) bit data on optical fibers, but the fast optical switching of Peta bits lacks a reliable solution, which directly limits the development of a new generation of optical networks.

Although the switching speed (switching speed) of traditional optical circuit switching (OCS, optical circuit switching) continues to increase, it is limited by optical loss, and the size of its optical switching matrix (matrix size) cannot be expanded infinitely. Optical packet switching (OPS, optical packet switching) is obviously subject to the problem of switching speed. Improved optical label switching (OLS, optical label switching), optical burst switching (OBS, optical burst switching), etc., even if a large-scale high-speed optical switching matrix is solved, it is still difficult to solve large-capacity, including OPS, OLS, OBS, etc. Packet contention conflicts and synchronous switching in optical switching, because when data from different input channels needs to reach the same output channel, packet conflicts are unavoidable.

The core reason for the above problems is that the existing technology can only pass through the limited delay of light (true delay) and low-depth buffer (conditional emergency), and the cost and price paid are very high: the fiber delay line can increase the delay time through physical stretching , but the loss and signal quality deteriorate; optical slowing technology uses material nonlinearity or structural dispersion to produce a certain delay, but it needs to break through the power threshold of the material or structure and requires a high-power laser, which is unsustainable! The above-mentioned technologies are not highly controllable to data, which is stretched in download and upload applications with high synchronization requirements! In the final analysis, the biggest limitation of the all-optical approach is that we lack a mature and reliable optical random access memory (o-RAM, optical random access memory), and our alternatives all have their own shortcomings.

On the basis of this consensus, in recent years, researchers have made breakthroughs in optical random access memory through two main approaches: one is all-optical random access memory (AO-RAM, All-Optical RAM), and the other is optoelectronic random access memory. Hybrid Random Access Memory (OE-RAM, OptoElectronic RAM).

The common point of all-optical random-access memory (AO-RAM) can be simply summarized as using the switching of different modes of the resonator or alternating modulation to keep the data in the traveling wave state continuously, and realize the bistable all-optical data trigger storage. However, there are many technical problems exposed. The main manifestations are that the state locking of the resonant cavity structure is heavily dependent on the ambient temperature and trigger optical power, and the traveling wave alternating structure has problems such as high power consumption and poor scalability.

In contrast, optoelectronic hybrid random access memory (OE-RAM), although it loses the transparency advantage of all-optical work, has two significant advantages: First, it can use electrical domain nanotechnology and its integration process The continuous innovation of the market occupies the market with strong competitiveness—for example, the current large-capacity optical communication network mainly relies on electrical storage for optical information exchange, that is, the optical-electrical-optical switching architecture. In other words, all communication networks and ultra- In addition to e-RAM, there is no alternative technology for random access storage in computing. Secondly, at the nanoscale, the "particle nature" and quantum effect characteristics of light and electricity converge, and the trend of fusion of the two is becoming more and more obvious. However, the electrical domain memory used in the existing optoelectronic hybrid random storage implementation scheme is relatively backward, and the speed, power consumption, cost, unit size and integration level of the overall system have not yet constituted significant advantages.

Contents of the invention

In view of the defects existing in the above-mentioned existing implementation schemes, the present invention provides an arrayed silicon-based programmable optical memory chip, which is an optical random access memory that realizes monolithic hybrid integration through an optical-electrical-optical architecture: specifically In other words, the present invention is aimed at the application of large-scale optical switching, based on silicon-based CMOS technology, with the help of integrated optical circuits and integrated circuits to realize miniaturized storage units and chip-based storage systems. It plays a vital technical support role for optical communication systems and networks above 100Gbps. It has extremely high application value.

To achieve the above object, the technical solution of the present invention is as follows:

An arrayed silicon-based programmable optical storage chip is characterized in that the chip includes a serial-parallel decomposition module for writing optical signals, a photoelectric conversion module, an electrical processing and storage module, an electro-optical modulation module, and an optical readout module with adjustable delay. The signal parallel-serial synthesis module, the serial-parallel decomposition module includes N high-speed optical switches, the photoelectric conversion module includes N arrayed photoelectric conversion structures, and the electrical processing and storage module includes N arrayed Memristor, the electro-optic modulation module includes N arrayed electro-optic modulation structures, the optical signal parallel-serial synthesis module includes N high-speed optical switches, and is driven by corresponding optical chips, electrical storage chips and electrical amplifiers The upper and lower stacked chips form three layers with the control chip to form N optical-electrical-optical structural channels, where N≥4, and the stacked chips are electrically connected by through holes or via holes.

The phase modulation of the interference arm of the high-speed silicon-based optical switch optical path of the serial-parallel decomposition module is realized based on the reverse PN junction.

The photoelectric conversion module realizes high-speed photoelectric conversion through a reverse-biased avalanche diode structure.

The electrical processing and storage module uses a metal-resistive variable dielectric layer-metal sandwich structure.

The electro-optic modulation module adopts a traveling-wave electro-optic modulator based on an MZI structure, and the phase modulation of the interference arm of the traveling-wave electro-optic modulator is realized based on a reverse PN junction.

The optical signal parallel-serial combination module adopts an adjustable waveguide delay line structure to realize synchronization in the optical domain.

The electrical processing and storage module includes a transimpedance amplifier for amplifying current.

The electro-optical modulation module also includes an adjustable optical delay line and an adjustable optical attenuator, which are used to adjust the delay amount of each optical signal and ensure energy balance between channels.

The optical signal input/output of the serial-parallel decomposition module, the electro-optic modulation module, and the optical signal parallel-serial synthesis module adopts horizontal coupling or vertical coupling to realize the connection between the external optical signal and the planar optical waveguide. The horizontal coupling described above is realized by a lens and an inverted tapered mode speckle converter on a chip, and the vertical coupling is realized by a planar optical fiber and a grating coupler on a chip.

The optical fiber and the waveguide are fixed by means of ultraviolet curing glue.

Compared with the prior art, the present invention has beneficial effects mainly reflected in the following aspects:

1. The photoelectric hybrid random access memory (OE-RAM) of the present invention can provide optical random read, and can provide a high-speed and large-capacity optical cache system for large-scale optical switching; in addition, the system structure all adopts a silicon-based substrate to realize a single On-chip photoelectric hybrid integration, compact structure, large storage capacity, compatible with CMOS technology, which is conducive to mass production and reduces costs.

2. The present invention uses microstrip lines for radio frequency microwave transmission and resistive variable memory ideas to solve the problem of slow power storage reading speed caused by the bottleneck of power domain transmission bandwidth and large capacitance of storage materials, thereby realizing fast power storage functions. Compared with traditional optical delay or caching methods, it can greatly increase the storage time of optical signals. Compared with traditional SRAM and DRAM storage, it has the advantages of small size, high density and large capacity expansion.

3. In the present invention, three layers of optical chip, electric storage chip and electric amplifier drive and control chip are formed into upper and lower laminated chips, which is the so-called 3D hybrid integrated chip, which avoids possible equipment cross-contamination during hybrid integration, reduces the difficulty of processing, and also Taking into account the decomposition of driving current, speed, heat and other issues, avoiding the heat generated by the electrical chip from affecting the normal operation of the optical chip.

4. The chip packaging method based on horizontal coupling or vertical coupling of the present invention can be flexibly and stably applied to a wide range of applications, and provides a reliable way for the integrated optical connection of read-write integrated large-capacity optical storage.

Description of drawings

FIG. 1 is a structural diagram of an embodiment of an arrayed silicon-based programmable optical memory chip according to the present invention.

FIG. 2 is a schematic diagram of hybrid integration of an embodiment of an arrayed silicon-based programmable optical memory chip according to the present invention.

FIG. 3 is a schematic structural diagram of a silicon-based optical switch according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of the working mechanism of the photoelectric conversion module according to the embodiment of the present invention.

FIG. 5 is a structure diagram of a resistive memory unit, an equivalent circuit diagram and a storage system structure thereof according to an embodiment of the present invention.

FIG. 6 is a structural diagram and a simulation diagram of a junction region of an electro-optical phase modulator according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a transimpedance amplifier according to an embodiment of the present invention.

Detailed ways

In order to further clarify the purpose, technical solution and core advantages of this solution, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Please note that the following specific examples are for illustrative purposes only, and are not intended to limit the present invention. At the same time, as long as the technical features involved in the various embodiments do not constitute a conflict with each other, they can be combined with each other.

Referring to Figure 1, the arrayed silicon-based programmable optical memory chip of the present invention is mainly divided into five parts according to its functional characteristics: an optical signal serial-parallel decomposition module 101, a photoelectric conversion module 102, an electrical processing and storage module 103, and an electro-optic modulation module 104 and optical signal parallel-serial synthesis module 105.

First, the optical signal data stream is input from the silicon waveguide public bus (Bus), and the signal corresponds to N optical switches according to the bit. When the first bit signal reaches the Nth optical switch, turn on the N optical switches at the same time to download the current N-bit data. After the data download is completed, the optical switch is turned off immediately, and the previous download process is repeated after the next set of data is ready. The high-speed optical signal serial-to-parallel conversion realized by the method can reduce the speed of the high-speed optical signal to the original 1/N, which is convenient for subsequent processing and storage. It should be noted that this process requires the propagation time of the optical signal on the bus waveguide between two adjacent optical switches to be strictly equal to the time slot of one bit of optical signal. In order to adapt to signals of different rates, we add adjustable delay lines within the channel to achieve dynamic and precise synchronization.

Next, the optical signal downloaded from the bus by serial-to-parallel conversion will enter the photoelectric conversion module 102 in its channel. This module realizes high-sensitivity photoelectric conversion by means of the avalanche gain effect of the reverse-biased PN junction, and converts the input optical signal into a photocurrent signal. , and sent to the electrical processing and storage module 103.

The input photocurrent is amplified by the transimpedance amplifier and then sent to the memristor in its channel, causing a conductive channel in the resistive layer in the metal layer-resistive dielectric layer-metal layer (MIM, Metal-Insulator-Metal) sandwich structure The formation or fracture of the dielectric material finally realizes the conversion of the resistance of the dielectric material between the high-resistance state and the low-resistance state, thereby storing this bit of optical signal in the corresponding memristor unit.

Afterwards, under the read trigger command, the data in the memristor enters the electro-optic modulation module 104 again through the transimpedance amplifier in the form of current. The electro-optical modulation module first downloads the optical carrier from another silicon waveguide bus by means of a fast optical switch, and then modulates the electrical signal of this channel to the optical domain by means of a modulator, thereby completing the parallel readout function of low-speed optical data.

Finally, the optical signal parallel-serial synthesis module 105 performs time delay and amplitude adjustment on these low-speed optical signals, and synthesizes N parallel data into one output to obtain an optical signal stored for a period of time to realize the required optical buffer.

On the basis of the above scheme, the optical storage system includes four or more programmable channels in the form of an array, and realizes large capacity, high speed and random read and write at the same time. At the same time, each channel also includes adjustable optical delay lines and A variable optical attenuator (VOA) is used to adjust the delay and ensure the balance of optical power on each channel.

On the basis of the above scheme, the integrated optical device uses silicon-based optoelectronic active devices and passive devices, and is realized by means of CMOS compatible technology; the described amplifier, driving and control circuit is realized by traditional CMOS circuit.

On the basis of the above scheme, the arrayed optoelectronic hybrid integrated chip uses the structure shown in Figure 3 to use the optical chip, the electrical storage chip, and the electrical amplifier drive and control chip as three layers to form upper and lower stacked chips, which reduces the difficulty of processing, and at the same time It also considers the decomposition of driving current, speed, heat and other issues, so as to avoid the heat generated by the electrical chip from affecting the normal operation of the optical chip.

On the basis of the above scheme, the serial-parallel decomposition module adopts the Mach-Zehnder optical switch structure shown in Figure 3, which uses the carrier dispersion effect to change the phase of one arm of the Mach-Zehnder interferometer, thereby changing the interference at the output end Light energy intensity completes the gating operation of the signal, and the signal is decomposed in units of bits and downloaded to each channel to realize serial parallel decomposition and speed reduction.

On the basis of the above scheme, the photoelectric conversion writing operation adopts a PN diode structure. By applying a reverse bias voltage, when an optical signal is input, a photocurrent will be generated to complete the conversion from an optical signal to an electrical signal. The working mechanism diagram is shown in Figure 4 shown. In order to improve the photoelectric conversion efficiency, the avalanche gain effect can be used, that is, a high electric field is formed in the PN junction, and photogenerated electrons and holes (absorbed through surface states and intermediate energy levels) are accelerated in this region to obtain high energy. If the carrier energy is high enough, it will collide with silicon lattice atoms, ionizing the bound electrons, thereby creating an electron-hole pair in the conduction and valence bands. The carriers generated by the collision will also be accelerated and continue to collide with other silicon lattice atoms, further generating electron-hole pairs.

On the basis of the above scheme, the structure of the resistive variable memory unit and its storage system is shown in Figure 5. A layer of silicon oxide is grown on the silicon base, and then sputtered to form a MIM structure, that is, a metal-resistive medium layer-metal structure. Sandwich structure, for the needs of fast storage, this embodiment will use the transition metal binary oxide as the main material, and combine the PN diode structure to design the memristive memory unit to form a TR (transistor+resistor) formed by connecting a transistor and a resistor in series. )structure. The transistor plays the role of selection and isolation. When operating on the resistance unit, the transistor is turned on, so that the unit to be operated is selected; when operating on other resistance units, the transistor is turned off, avoiding misoperation of surrounding units and generating reading Crosstalk, play the role of isolation. FIG. 5 also shows a corresponding equivalent circuit diagram and a memory array diagram formed by extending multiple cells.

On the basis of the above solution, the electro-optic modulation module 104 mainly adopts the traveling-wave electro-optic modulator based on the MZI structure shown in FIG. 3 , the core of which is the phase modulation of the interference arm. FIG. 6 is a schematic diagram of a phase modulator based on an inverted PN junction. Since holes have better refractive index modulation efficiency than electrons, a design with higher concentration of N-type doping than P-type doping can be used to obtain higher modulation efficiency (reduce driving voltage and increase extinction ratio) and Small carrier absorption loss (reduce device insertion loss).

On the basis of the above scheme, the optical signal parallel-serial synthesis module 105 converts multiple low-speed optical signals into serial high-speed signals. This module mainly completes the dynamic adjustment of time and amplitude. The time adjustment is mainly to realize the The equal-interval output synthesis ensures that the rate of the output optical signal is the same as that of the input optical signal. Since the whole system adopts the electrical storage method, electrical signals can be read randomly. Therefore, the combination of output optical data signals on the bus waveguide can also be realized by changing the electrical reading time of the data. In order to reduce the pressure of electrical processing, we adopt a combination of two structures, combining optical delay and electrical reading random Complete time division multiplexing.

On the basis of the above scheme, a transimpedance amplifier is used to increase the intensity of the electrical signal in both the photoelectric writing and electro-optic reading processes. The transimpedance amplifier is one of the amplifiers, which is defined according to the type of its input and output signals. When the input is a current signal and the output is a voltage signal, A=Y (voltage)/X (current), which has the dimension of resistance, Therefore, it is generally called a transimpedance amplifier. Due to its advantages of high bandwidth, it is widely used in optoelectronic chips and systems. The basic schematic of the transimpedance amplifier is shown in Figure 7. Three aspects need to be considered in the design: low noise figure and high gain, good input and output impedance matching and sufficient linear range, low supply voltage and low power consumption. In a word, the arrayed silicon-based programmable optical memory chip realized according to the present invention can provide random reading and writing of high-speed optical signals, and can realize wavelength transparency within the designed wavelength range (eg communication window C-band: 1530nm-1560nm). At the same time, it also has the advantages of fast speed, scalability, small size, low cost, high integration, reliable and complete packaging, and easy mass production.

Those in the scientific research or industry departments in the same field can easily understand that the above content is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention etc., should be included within the protection scope of the present invention.

Claims (10)

1. a kind of array silicon substrate programmable optical storage chip, which is characterized in that the chip includes that the string of optical signal is written and divides Solution module (101), photoelectric conversion module (102), electric treatment and memory module (103), Electro-optical Modulation module (104) and delay can The reading optical signal of tune and synthesis module (105) of going here and there, the string and decomposing module (101) include N number of high-speed optical switch, described Photoelectric conversion module (102) include N number of array photovoltaic conversion structure, the electric treatment and memory module (103) packet The memristor of N number of array is included, the Electro-optical Modulation module (104) includes the Electro-optical Modulation structure of N number of array, described Optical signal and synthesis module (105) of going here and there includes N number of high-speed optical switch, and by corresponding optical chip, electric storage chip and electrically amplified Driving and three layers of chip of control form chips stacked on top of one another and constitute N number of optical-electrical-optical structure channel, wherein N >=4, stacked die it Between electrical connection realized by through-hole or via.

2. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the string and decomposing module (101) the interfere arm phase-modulation of high speed silicon substrate photoswitch light path is realized based on reversed PN junction.

3. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the photoelectric conversion module (102) high speed optoelectronic conversion is realized by reverse-biased avalanche diode structure.

4. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the electric treatment and storage Module (103) uses the sandwich structure of metal-resistive dielectric layer-metal.

5. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the Electro-optical Modulation module (104) use the travelling-wave electrooptic modulator based on MZI structures, the travelling-wave electrooptic modulator, interfere arm phase-modulation be based on it is anti- It is realized to PN junction.

6. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the optical signal and conjunction of going here and there The synchronization of area of light is realized using adjustable waveguide delay line structure at module (105).

7. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the electric treatment and deposit Module (103) is stored up, including the trans-impedance amplifier changed for realizing current signal to voltage signal.

8. array silicon substrate programmable optical storage chip as claimed in claim 6, which is characterized in that the Electro-optical Modulation mould Block (105), while including variable optical delay line and adjustable optical attenuator (VOA), for realizing the tune of every road optical signal retardation Section, and ensure each interchannel balancing energy.

9. array silicon substrate programmable optical storage chip as described in claim 1, which is characterized in that the string simultaneously decomposes mould Block (101), the Electro-optical Modulation module (104) and the optical signal and go here and there synthesis module (105) optical signal input/it is defeated Go out using horizontal coupling or the vertical coupled connection realized between external optical signal and planar optical waveguide, the horizontal coupling is adopted It is realized with the back taper spot-size converter on lens and chip, the vertical coupled grating using on plane optical fiber and chip Coupler.

10. array silicon substrate programmable optical storage chip as described in any one of claim 1 to 9, which is characterized in that described It is fixed by way of uv-curable glue between optical fiber and waveguide.