CN108630661A - Method for forming semiconductor element pattern - Google Patents

Abstract

The invention discloses a method for forming a semiconductor element pattern, which comprises the following steps: providing a substrate material layer with a first area and a second area; arranging a plurality of first mandrels above the base material layer and corresponding to the first areas; arranging a plurality of second mandrels above the base material layer and corresponding to the second areas; forming first side wall spacers on the side walls of the first mandrels and second side wall spacers on the side walls of the second mandrels, wherein the first side wall spacers form a first pattern, the second side wall spacers form a second pattern, and the second side wall spacers positioned between two adjacent second mandrels are mutually fused; and transferring a first pattern including the first sidewall spacers and a second pattern including the second sidewall spacers to the base material layer to form a patterned base material layer.

Description

Method for forming semiconductor element pattern

technical field

The invention relates to a method for forming a pattern, and in particular to a method for forming a pattern of a semiconductor element capable of producing an easily recognizable pattern.

Background technique

In recent years, semiconductor devices have been increasingly reduced in size. For semiconductor technology, continuously reducing the size of semiconductor structures, improving speed, increasing performance, increasing density and reducing the cost per unit integrated circuit have become important development goals of semiconductor technology. As the size of semiconductor devices shrinks, the electronic characteristics of the devices must also be maintained or even improved, so as to meet the requirements of the applied electronic products in the market. For example, if the layer structure and components of the semiconductor device are defective or damaged, it will have a non-negligible impact on the electronic characteristics of the device. Therefore, it is one of the important issues that need to be paid attention to in the manufacture of semiconductor devices.

Taking a patterning process of a semiconductor device such as a FinFET process as an example, a sidewall image transfer (SIT) process is usually used to fabricate the fin structure. The pattern of the mandrel is used to define related marking patterns of related elements (such as fins) in the active area and cutting lines in the peripheral area. In existing mandrel layout designs, the boundary of the scribe pattern is too small to be detected by optical sensors, and this problem will become more serious when manufacturing small-sized semiconductor devices. Poorly recognizable logo patterns in the manufacturing process may affect product yield.

Contents of the invention

The invention provides a method for forming a pattern of a semiconductor element, which can improve the recognition degree of the formed pattern to be detected.

According to an embodiment, a method for forming a pattern of a semiconductor element is provided, comprising: providing a base material layer having a first region and a second region; arranging a plurality of first mandrels above the base material layer and corresponding to the first region ; setting a plurality of second mandrels above the base material layer and corresponding to the second region; forming a first sidewall spacer on the sidewall of the first mandrel, and forming a second sidewall spacer on the sidewall of the second mandrel Sidewalls, wherein the first sidewall spacers form a first pattern, the second sidewall spacers form a second pattern, and the second sidewall spacers located between two adjacent second mandrels merging with each other; and transferring the first pattern including the first sidewall spacers and the second pattern including the second sidewall spacers to the base material layer to form a patterned base material layer.

In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings. However, the protection scope of the present invention should be defined by the appended claims.

Description of drawings

1A to 1G are schematic diagrams of a method for forming a pattern of a semiconductor element according to an embodiment of the present invention;

Fig. 2 is a top view of an identification pattern of one application example of the present invention;

Fig. 3 is a top view of multiple second mandrels in one of the application examples of the present invention;

Fig. 4A is a top view of multiple second mandrels in another application example of the present invention;

FIG. 4B is a schematic diagram of another structure of the second mandrel along line 4B-4B in FIG. 4A .

Symbol Description

A1: First area

A2, A2': the second area

11: base material layer

11': patterned base material layer

131-133: first mandrel

131a-133a: upper surface of the first mandrel

141-143, 441, 442, 443, 444, 445, 446: Second mandrel

141a-143a: upper surface of the second mandrel

443g, 444g: Small segments of the second mandrel

S1: first gap

S2: second gap

CD1: first critical dimension

CD2: Second Critical Dimension

15: spacer material layer

t1: Thickness of the spacer material layer

17: Gap filling layer

17': Gap fill pattern

17a: Top surface of void fill pattern

151-153, 36, 46: first sidewall spacer

151a-153a: upper surface of first sidewall spacer

161-163: Second sidewall spacer

161a-163a: upper surface of second sidewall spacer

18: First Groove

19: Second groove

t2: width of the second trench

B1: the first block

B2: the second block

B3: The third block

M2-1: First group of second mandrel

M2-2: Second Group of Second Mandrels

M2-3: The third group of the second mandrel

D1: first direction

D2: Second direction

Detailed ways

In the following disclosure, a method for forming a pattern proposed by an embodiment will be described in detail with reference to the accompanying drawings, especially a method for forming a pattern of a semiconductor element that can generate an easily identifiable pattern. The forming method of the embodiment can be applied to many different types of semiconductor elements, such as (but not limited to) fin field effect transistor manufacturing process or pattern recognition in other manufacturing processes, making the pattern of the predetermined area such as the peripheral area or cutting The alignment marks associated with the scribeline region can become more pronounced after formation, for example, the width of the alignment marks increases, so that the optical sensor can detect the alignment marks more easily. Therefore, by applying the method of the embodiment of the present invention, good critical dimension (CD) control can be obtained, thereby improving the recognition of the pattern to be detected to maintain a high product yield. The method of the embodiment of the present invention is particularly suitable for application in the manufacturing process of small-sized semiconductor elements or semiconductor devices with reduced feature elements, so as to improve the recognition of finer patterns to be detected.

The following describes several groups of implementation aspects of the present invention with reference to the accompanying drawings to illustrate related forming methods and configurations. Relevant steps and structural details such as applicable steps, related layers and materials, and spatial configuration of elements (ex: mandrel) are described in the following embodiments, but the present invention is not limited to the above-mentioned aspects. The invention does not represent all possible embodiments. In the embodiments, the same or similar symbols are used to indicate the same or similar parts. Furthermore, other implementation aspects not proposed in the present invention may also be applicable. Those in the relevant field can change and modify the structures of the embodiments without departing from the spirit and scope of the present invention, so as to meet the needs of practical applications. The accompanying drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios in the accompanying drawings are not drawn according to the proportion of the actual product. Therefore, the specification and illustrations are only used to describe the embodiments, not to limit the protection scope of the present invention.

Furthermore, the ordinal numbers used in the description and claims, such as "first", "second", "third", etc., are used to modify the elements of the claims, which do not imply and represent that the claimed elements have Any previous ordinal numbers do not represent the order of a claimed element with another claimed element, or the order of the manufacturing method, and the use of these ordinal numbers is only used to enable a claimed element with a certain designation to have the same Named request elements make a clear distinction.

1A-1G illustrate a method for forming a pattern of a semiconductor device according to an embodiment of the present invention. In one embodiment, the layout in two regions (for example, the first region A1 and the second region A2) such as the mandrel pattern design is taken as an example to provide an illustration, but the pattern layout during the actual application of the present invention is not limited thereby. . As shown in FIG. 1A, a base material layer (base material layer) 11 is provided, and the base material layer 11 has, for example, a first area A1 and a second area A2; and a plurality of first mandrels (first mandrels) such as 131- 133 and a plurality of second mandrels (second mandrels) 141-143 above the base material layer 11, and the first mandrels 131-133 correspond to the first area A1, and the second mandrels 141-143 correspond to the second area A2 .

Wherein, there is a first gap (firstspacing) S1 between two adjacent first mandrels (such as first mandrels 131 and 132), and between two adjacent second mandrels (such as second mandrels 141 and 142) There is a second spacing (secondspacing) S2 between them. The accompanying drawings only show one implementation. Of course, according to the needs of actual application conditions, the spacing between the first mandrels and the spacing between the second mandrels can be modified or changed; for example, the spacing between adjacent first mandrels can be the same or different. The distances between adjacent second mandrels may be the same or different; moreover, the first gap S1 of the embodiment may be greater than, substantially equal to or smaller than the second gap S2. Furthermore, one of the first mandrels (for example, the first mandrel 132 ) has a first critical dimension (first critical dimension) CD1 along the Y direction, and one of the second mandrels (for example, the second mandrel 142 ) has a first critical dimension (first critical dimension) CD1 along the Y direction. ) along the Y direction has a second critical dimension (second critical dimension), CD2, according to actual application conditions, the critical dimension of each mandrel can be modified or changed, and the first critical dimension (ex: CD1) may be larger than, basically is equal to or smaller than the second critical dimension (ex: CD2). The changes between the first gap S1, the second gap S2, the first critical dimension and the second critical dimension are as long as the second sidewall spacers formed between the second mandrels can be merged with each other. Applicable (whereas the second sidewall spacer fused here corresponds to the pattern to be detected that is easily identifiable to be formed later; detailed description is given in the following paragraphs).

In this embodiment, the second mandrels such as 141-143 are arranged closer than the first mandrels such as 131-133 (that is, the first gap S1 is greater than the second gap S2), and the second mandrels such as 141- 143 also increases in width (that is, the first critical dimension CD1 is smaller than the second critical dimension CD2 ) is an example for illustration with reference to FIGS. 1A to 1G .

As shown in FIG. 1B , a spacer material layer 15 (spacer material layer) is formed on the first mandrels such as 131-133 and the second mandrels such as 141-143, wherein the spacer material layer 15 has a thickness t1. And, as shown in FIG. 1C, a first sidewall spacer (first sidewall spacers) such as 151, 152, 153 is formed on the sidewall of the first mandrel 131-133, and a second sidewall spacer (second sidewall spacers) is formed. ) such as 161, 162, 163 on the side walls of the second mandrels 141-143, and the second side wall spacers between adjacent two second mandrels are fused with each other (that is, combined or merged) (merge) , as shown by the second sidewall spacers 162 and 163 fused to each other in FIG. 1C .

In one embodiment, the width of the second gap S2 is no more than twice the thickness of one of the first sidewall spacers (eg 151 or 152 or 153 ). In one embodiment, the width of the second gap S2 is substantially equal to twice the thickness of a first sidewall spacer 151/152/153 (S2 is approximately 2×t1). In one embodiment, the width of the second gap S2 is equal to the thickness t1 of one of the first sidewall spacers (such as 151 or 152 or 153 ). However, the present invention is not limited to the above-mentioned exemplified aspects, but the ratio of the second gap S2 to the thickness t1 of the first sidewall spacer can be modified or changed according to the actual application conditions, as long as it can be formed on the adjacent sidewall spacers. The sidewall spacers between the two second mandrels can be fused with each other as an application.

As shown in FIG. 1D, a gap filling layer 17 is deposited to cover the first sidewall spacers 151-153, the first mandrels 131-133, the second sidewall spacers 161-163 and the second core Axes 141-143 above. Thereafter, a part of the gap-filling layer 17 is removed, for example, the gap-filling layer 17 is polished by chemical mechanical polishing (CMP) to expose at least the first sidewall spacers 151-153 and the second sidewall spacers 161-163. On the upper surface, a gap filling pattern (gap filling pattern) 17' is formed between adjacent first sidewall spacers (such as between the first sidewall spacers 151 and 152, and the first sidewall spacers 152 and 153) space. As shown in FIG. 1E, after grinding, the upper surfaces 151a-153a of the first sidewall spacers 151-153, the upper surfaces 161a-163a of the second sidewall spacers 161-163, and the first mandrels 131-133 are exposed. and the upper surfaces 141a-143a of the second mandrels 141-143. In one embodiment, the upper surface 17a of the void-filling pattern 17' is, for example, compatible with the upper surfaces 151a-153a of the first sidewall spacers 151-153, the upper surfaces 161a-163a of the second sidewall spacers 161-163, The upper surfaces 131a-133a of the first mandrels 131-133 and the upper surfaces 141a-143a of the second mandrels 141-143 are substantially flush.

Furthermore, as shown in FIG. 1D, since the second sidewall spacers between the adjacent second mandrels 141-143 have been fused to fill up the spaces at these positions, when depositing the gap-filling layer 17 It cannot be filled between the adjacent second mandrels 141 - 143 , and can only be formed above the second sidewall spacers such as 162 and 163 . Therefore, after the subsequent part of the step of removing the gap-filling layer 17, the gap-filling pattern 17' is also located outside the second mandrel 141-143, as shown in FIG. 1E. Pattern transfer is then performed.

As shown in FIG. 1F , the first sidewall spacers 151 - 153 and the second sidewall spacers 161 - 163 are removed. At this time, the base material layer 11 includes a void-filling pattern 17', first mandrels 131-133, and second mandrels 141-143.

As shown in FIG. 1G, the base material layer 11 is etched using the gap-filling pattern 17', the first mandrels 131-133 and the second mandrels 141-143 as a mask to form a patterned base material layer ( patterned base material layer) 11'. Accordingly, the first pattern including the first sidewall spacers 151-153 and the second pattern including the second sidewall spacers 161-163 and the void-filling pattern 17' are transferred to the base material layer 11 in the transferring step. After the pattern transfer is complete, the void-fill pattern 17', the first mandrels 131-133, and the second mandrels 141-143 are removed. In addition, in the embodiment, the base material layer 11/patterned base material layer 11' may include one or more materials used to form semiconductor elements, such as a silicon substrate material, an oxide material, a polysilicon material or Other materials are not particularly limited in the present invention.

As shown in FIG. 1G, the patterned base material layer 11' includes a plurality of first trenches (first trenches) 18 disposed in the first region A1 and corresponding to the first pattern (i.e. first sidewall spacers 151-153), And a plurality of second trenches 19 are disposed in the second region A2 and correspond to the second pattern (i.e. second sidewall spacers). Since the second groove 19 corresponds to the position of the fused sidewall spacer, a wider groove (relative to the first groove 18) will be formed after the pattern transfer, as the pattern to be identified during application (ex: The recognition pattern of the cutting line) can effectively improve the pattern recognition. In one embodiment, the width of at least one of the second grooves 19, such as the width t2 (along the Y-direction), is greater than the width of at least one of the first grooves 18 (for example, equal to the thickness t1 of the spacer material layer 15) . In one embodiment, the width (ex: width t2 ) of each second trench 19 is larger than the width (ex: width t1 ) of each first trench 18 .

1A-1G in the above example, the second mandrels 141-143 are arranged closer than the first mandrels 131-133 (i.e. S1>S2) and the width of the second mandrels 141-143 is larger than that of the first mandrels. The width of the mandrels 131-133 (i.e. CD2>CD1) is described as an example, but the present invention is not limited thereto. In other embodiments, the second mandrel 141-143 may not be widened, that is, its width is substantially equal to that of the first mandrel 131-133, but the second mandrel 141-143 is arranged to be wider than the first mandrel. The mandrels 131-133 are tighter so that the second sidewall spacers can fuse with each other.

In an application example, the first region A1 is, for example, a cell region or an active region, and the second region A2 is, for example, a peripheral region or a scribe line region, and as shown in FIG. 1G The second groove 19 shown is, for example, an identification pattern used as a cutting line. However, the invention is not limited to this application. In other applications, both the first area A1 and the second area A2 may correspond to areas of the identification pattern. Please refer to FIG. 2 , which shows a top view of an identification pattern of one application example of the present invention. Wherein, the sidewall spacers corresponding to the mandrels of the first area A1 are not fused with each other, but the sidewall spacers corresponding to the mandrels of the second area A2 are fused with each other, so the first identification pattern shown in FIG. 2 The region A1 includes a pattern of narrow grooves (such as the aforementioned first groove 18), and the second region A2 of the identification pattern includes a pattern of wide grooves (such as the aforementioned second groove 19, corresponding to the sidewall spacers fused with each other). .

In addition, in other application examples of the present invention, a plurality of groups of second mandrels can also be formed when viewed from a top view, and these groups can be arranged regularly (such as a matrix arrangement) or irregularly, and The second sidewall spacers 36 between groups of adjacent second mandrels are fused to each other. FIG. 3 is a top view of a plurality of second mandrels in one application example of the present invention. In one embodiment, a plurality of second mandrels are located in the second area A2' (you can also refer to the description of the structure and steps of the second mandrels 141-142 and other related components in the aforementioned second area A2), such as Including the first group (first group of the second mandrels) M2-1 corresponding to the second mandrels of the first block (first block) B1, the second group of the second mandrels corresponding to the second block (second block) B2 The group M2-2 and the third group M2-3 corresponding to the second mandrel of the third block B3. The first block B1 is adjacent to the second block B2, and the third block B3 is adjacent to the second block B2. Seen from above, the second mandrels (ex: M2-1, M2-3, M2-3) extend along the first direction D1 (for example, the X-direction), and the first group of the second mandrels The group M2-1, the second group M2-2 of the second mandrel, and the third group M2-3 of the second mandrel are distributed along the second direction D2 (ex: Y-direction) so as to be in the first zone respectively The block B1 to the third block B3 are distributed into three mandrel columns. Taking the distribution of the mandrels of two block-shaped areas as an example, such as the adjacent first block B1 and the second block B2, the first group M2-1 of the second mandrel is aligned with the second group M2-1 of the second mandrel. Group M2-2 (FIG. 3); the second sidewall spacers 36 between the first group M2-1 of the adjacent second mandrel and the second group M2-2 of the second mandrel are mutually Fusion with each other to form an easily recognizable pattern after pattern transfer. Of course, the application of the present invention is not limited thereto, and the positions of the cores of the groups of adjacent second mandrels can also be staggered from each other or arranged in other ways.

In addition, in other application aspects, the second mandrel may further include a plurality of small segments. Please refer to FIG. 4A and FIG. 4B . FIG. 4A is a top view of multiple second mandrels in another application example of the present invention. FIG. 4B is a schematic diagram of another structure of the second mandrel along line 4B-4B in FIG. 4A . The second mandrels 441-446 shown in FIG. 4A extend along the first direction D1 (ex: X-direction) and are arranged in rows along the second direction D2 (ex: Y-direction). The adjacent second cores For example (but not limited to), there is a second gap S2 between the shafts 441-446, and the second sidewall spacers 46 between adjacent second mandrels 441-446 are fused with each other (details of related content can be obtained from Refer to the content of the foregoing embodiments, and details are not repeated here). In another embodiment, the second mandrel, such as the second mandrel 443 and 444 shown in FIG. 4B , respectively includes a plurality of small segments (small segments) 443g and 444g spaced apart from each other along the first direction D1 ( ex: X-direction) distribution; and the adjacent small segments 443g and 444g can be aligned with each other or staggered, which is not limited in the present invention.

According to the above, a method for forming a pattern of a semiconductor element proposed in the embodiment can make the pattern of the predetermined area, such as the relevant alignment marks of the peripheral area or the scribe line area, become more prominent after formation (such as the alignment marks) increased width) so that the patterning can be more easily detected by the optical sensor for detection. Therefore, by applying the method of the embodiment of the present invention, good critical dimension control can be obtained, thereby improving the recognition of the pattern to be detected to maintain a high product yield. The method of the embodiment of the present invention is particularly suitable for application in the manufacturing process of small-sized semiconductor elements or semiconductor devices with reduced feature elements, so as to improve the recognition of finer patterns to be detected, and has no adverse effect on the electrical properties of other elements. Furthermore, the method proposed in the embodiment forms semiconductor device patterns in simplified and efficient steps, which not only can effectively improve pattern recognition, but also is compatible with existing manufacturing processes, and is very suitable for mass production.

Other embodiments, such as the position structure and arrangement of different areas or blocks and mandrels in the layout, may also be applicable, and the distribution of mandrels in each area or block in the application can be appropriately selected according to the needs of actual applications. with change. Therefore, the structures or patterns shown in the figures are for illustration only, and are not intended to limit the protection scope of the present invention. In addition, those skilled in the art should know that the shapes and positions of the components in the embodiments are not limited to the ones shown in the illustrations, and are also based on actual application requirements and/or manufacturing steps without departing from the spirit of the present invention. Adjust accordingly.

Although the present invention has been disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Those skilled in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (18)

1. A method for forming a semiconductor element pattern, comprising: providing a base material layer having a first region and a second region; disposing a plurality of first mandrels above the base material layer and corresponding to the first region; disposing a plurality of second mandrels above the base material layer and corresponding to the second region; forming first sidewall spacers on the sidewalls of the first mandrels, and forming second sidewall spacers on the sidewalls of the second mandrels, wherein the first sidewall spacers form a first pattern, the second sidewall spacers form a second pattern, and the second sidewall spacers between two adjacent second mandrels are fused with each other; and transferring the first pattern including the first sidewall spacers and the second pattern of the second sidewall spacers to the base material layer to form a patterned base material layer. 2. The forming method of claim 1, further comprising: Before transferring the first pattern and the second pattern, the first sidewall spacers and the second sidewall spacers are removed. 3. The forming method according to claim 1, wherein the patterned base material layer comprises: A plurality of first grooves are disposed in the first region and correspond to the first pattern; and A plurality of second grooves are disposed in the second region and correspond to the second pattern. 4. The forming method according to claim 3, wherein a width of each of the second trenches is greater than a width of each of the first trenches. 5. The forming method according to claim 1, wherein a first gap between two adjacent first mandrels is larger than a second gap between two adjacent second mandrels. 6. The forming method of claim 5, wherein the width of the second gap is no more than twice the thickness of one of the first sidewall spacers. 7. The forming method of claim 5, wherein a width of the second gap is equal to a thickness of one of the first sidewall spacers. 8. The forming method of claim 1, wherein one of the first mandrels has a first critical dimension, one of the second mandrels has a second critical dimension, and the first critical dimension size is equal to the second critical dimension. 9. The forming method of claim 1, wherein one of the first mandrels has a first critical dimension, one of the second mandrels has a second critical dimension, and the first critical dimension size is less than the second critical dimension. 10. The forming method according to claim 1, wherein the first mandrels have a first distribution density, the second mandrels have a second distribution density, and the first distribution density is smaller than the second distribution density density. 11. The forming method according to claim 1, wherein the patterned base material layer in the second region comprises at least: a first block comprising a first group of the second mandrels; and a second block, adjacent to the first block, the second block includes a second group of the second mandrels; The second sidewall spacers between the first group of the adjacent second mandrels and the second group of the second mandrels are fused with each other. 12. The forming method according to claim 11, wherein the second mandrels extend along a first direction, and the first group of the second mandrels and the first group of the second mandrels The two groups are distributed along a second direction to form two mandrel rows respectively in the first block and the second block. 13. The forming method of claim 12, wherein the first group of the second mandrels is aligned with the second group of the second mandrels. 14. The forming method of claim 1, wherein the second mandrels extend along a first direction, and the first group of the second mandrels and the first group of the second mandrels The two groups are distributed along a second direction, wherein one of the second mandrels includes a plurality of small segments distributed along the first direction and the small segments are separated from each other. 15. The forming method of claim 1, further comprising: forming a void-filling pattern in spaces between adjacent first sidewall spacers; removing the first sidewall spacers and the second sidewall spacers before transferring the first pattern and the second pattern; and The base material layer is etched using the gap filling pattern, the first mandrels and the second mandrels as a mask to form the patterned base material layer. 16. The forming method according to claim 1, wherein the first area is a memory area, and the second area is a scribe line area. 17. The forming method according to claim 1, wherein the first region and the second region are located in a peripheral region and respectively correspond to different parts of a transfer pattern. 18. The forming method according to claim 1, wherein the base material layer is a silicon substrate.