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CN108630599A - The forming method of chip - Google Patents

The forming method of chip Download PDF

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Publication number
CN108630599A
CN108630599A CN201710173741.3A CN201710173741A CN108630599A CN 108630599 A CN108630599 A CN 108630599A CN 201710173741 A CN201710173741 A CN 201710173741A CN 108630599 A CN108630599 A CN 108630599A
Authority
CN
China
Prior art keywords
chip
wafer
forming method
etching solution
raceway groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710173741.3A
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Chinese (zh)
Inventor
马岳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SAE Technologies Development Dongguan Co Ltd
Original Assignee
SAE Technologies Development Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SAE Technologies Development Dongguan Co Ltd filed Critical SAE Technologies Development Dongguan Co Ltd
Priority to CN201710173741.3A priority Critical patent/CN108630599A/en
Publication of CN108630599A publication Critical patent/CN108630599A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

The forming method of the chip of the present invention, including:A wafer is provided, the wafer has opposite first surface and second surface;Cutting being carried out to the second surface from the first surface and forming several raceway grooves, the depth of the communication is less than the thickness of the wafer;And the wafer is etched along the raceway groove using etching solution so that the depth of the raceway groove is gradually increased up to equal with the thickness of the wafer, to which separation forms multiple chips.Its avoidable chip of the present invention causes chip fragmentation in forming process, to ensure the yields of chip.

Description

The forming method of chip
Technical field
The present invention relates to the forming method of chip more particularly to a kind of sides that semiconductor crystal wafer is divided into multiple chips Method.
Background technology
In semiconductor crystal wafer processing, integrated circuit is formed in (to be also known as by the wafer that silicon or other semi-conducting materials form Make substrate) on.In general, various semiconductors, conductor or insulation material layer are used to form integrated circuit.Using various already known processes come Such material is adulterated, deposits and etches, to form integrated circuit.Each wafer forms a large amount of respective regions through processing, and region contains There is the integrated circuit of referred to as crystal grain.
After integrated circuit formation process, individual crystalline grains are separated from each other for encapsulation or with unencapsulated by " cutting " wafer Form is in larger circuit.Wafer thinning, wafer cutting and chip point are generally comprised in existing method for cutting chip From and etc..First, keep its thinning after chip back surface being ground using emery wheel, then pad pasting is carried out in active face, carry out again later The action of cutting is to be separated into multiple chips and die bonding film.Common cutting method is to use physics mode, such as with cutter Sawing.When carrying out sawing, the diamond tip saw of high rotating speed rotation per minute contacts crystal column surface and along Cutting Road sawing crystalline substance Circle.However, a very big problem for physics sawing is to be easy to cause chip fragmentation, to cause the fracture of internal wiring to cause to collect It is invalid at circuit.
So there is an urgent need for a kind of forming method of improved chip, with the defect more than overcoming.
Invention content
The purpose of the present invention is to provide a kind of forming methods of chip, can avoid chip and cause crystalline substance in forming process Piece fragmentation, to ensure the yields of chip.
To achieve the above object, the forming method of chip of the invention includes the following steps:
A wafer is provided, the wafer has opposite first surface and second surface;
Cutting being carried out to the second surface from the first surface and forming several raceway grooves, the depth of the communication is less than institute State the thickness of wafer;And
Along the raceway groove wafer is etched using etching solution so that the depth of the raceway groove be gradually increased until It is equal with the thickness of the wafer, to which separation forms multiple chips.
Compared with prior art, method for forming chip of the present invention forms depth less than wafer thickness on the surface of wafer first Raceway groove, then using etching method to the layer body on raceway groove one by one etch removal so that separation forms multiple independent cores Piece, the present invention avoids the wafer fragmentation that blade rotation generates in traditional physics cutting, while reducing the internal stress of wafer, subtracts Its few deformation, to ensure the yields of chip.
Preferably, the wafer is sequentially formed with passivation layer, metal layer, resistance by the first surface to the second surface Barrier and oxide layer, wherein carried out in the step of cutting forms several raceway grooves from the first surface to the second surface, The depth of the raceway groove is suitable for the exposure passivation layer.
Preferably, being etched to the passivation layer using the first etching solution until the exposure metal layer.
Preferably, first etching solution includes sulfuric acid, potassium nitrate and ammonium acid fluoride.
Preferably, being etched to the metal layer using the second etching solution until the exposure barrier layer.
Preferably, second etching solution includes potassium hydroxide.
Preferably, being etched to the barrier layer using third etching solution until the exposure oxide layer.
Preferably, the third etching solution includes ammonium hydroxide and hydrogen peroxide.
Preferably, being etched to the oxide layer using the 4th etching solution until the depth of the raceway groove is equal to the crystalline substance Round thickness.
Preferably, carrying out cutting to the second surface from the first surface using laser beam forms the raceway groove.
Specific implementation mode
The forming method of the chip of the present invention is described further with reference to embodiment, but is not so limited this hair It is bright.
One embodiment of the forming method of the chip of the present invention includes the following steps:
A wafer is provided, the wafer has opposite first surface and second surface;
Cutting being carried out to the second surface from the first surface and forming several raceway grooves, the depth of the communication is less than institute State the thickness of wafer;And
Along the raceway groove wafer is etched using etching solution so that the depth of the raceway groove be gradually increased until It is equal with the thickness of the wafer, to which separation forms multiple chips.
Specifically, the first surface of wafer is the one side with integrated circuit, the frequently referred to front of wafer, the second table on the contrary Face is the reverse side of wafer.It is cut from first surface to second surface, preferably, using laser beam to the fate of wafer Domain is emitted to form raceway groove.Specifically, the power of laser beam is 20W~30W, and the rate of wavelength 1060nm, etching are 12 μm/s~15 μm/s.In this step, the depth of raceway groove is less than the thickness of wafer, that is, the raceway groove (Cutting Road) does not run through Wafer causes chip to detach, this purpose is to enter the passivation layer that the glass surface of wafer exposes wafer.As one embodiment, Wafer is sequentially formed with passivation layer, metal layer, barrier layer and oxide layer by first surface to second surface.In other embodiment In, it may include other layer of body.
Then, in an etching step, each layer body of wafer is etched successively on raceway groove using different etching solutions, To make the depth of raceway groove be gradually increased up to equal with the thickness of wafer, to which separation forms multiple chips.Specifically, it uses First etching solution is etched the passivation layer of wafer the metal layer until exposure wafer, which includes sulfuric acid, nitre The mixed solvent of sour potassium and ammonium acid fluoride, etching period are 30~35 seconds, and the temperature of mixed solvent is 20~25 degree.Then, Metal layer is etched using the second etching solution until barrier layer is exposed, preferably, second etching solution includes potassium hydroxide Solution, for example, a concentration of 15%~20% potassium hydroxide solution, etching period be 10~25 seconds, etching solution temperature be 60~80 Degree.Then, barrier layer is etched up to exposure oxide layer using the third etching solution including ammonium hydroxide and hydrogen peroxide, Time is 20~30 seconds, and etching solution temperature is 20~25 degree.Finally, oxide layer is etched with the 4th etching solution, the 4th It is etched to hydrofluoric acid solution, such as the concentration ratio of hydrofluoric acid and water ranging from 0.9:100~1.1:100, the time is 2~4 minutes, The temperature of etching solution is 25~30 degree.In this way, each layer body of the wafer on raceway groove can be etched one by one, to wafer realization point From to form multiple independent chips.
Certainly, it in etching step of the invention, can be selected different in response to quantity and the structure difference of the layer body of wafer Etching solution, until wafer is kept completely separate at raceway groove.
Preferably, further include water treatment steps and baking step after etching is completed.Specifically, it is rinsed with deionized water Chip, processing time are 10~15 minutes, then, processing are dried with dryer, the time is 10~15 minutes, temperature 80 ~100 degree.
In conclusion method for forming chip of the present invention forms the ditch that depth is less than wafer thickness on the surface of wafer first Road then etches the layer body on raceway groove removal using the method for etching and then separation forms multiple independent chips one by one, this Invention avoids the wafer fragmentation that blade rotation generates in traditional physics cutting, while reducing the internal stress of wafer, reduces it Deformation, to ensure the yields of chip.
Above disclosed is only presently preferred embodiments of the present invention, cannot limit the right of the present invention with this certainly Range, therefore according to equivalent variations made by scope of the present invention patent, be still within the scope of the present invention.

Claims (10)

1. a kind of forming method of chip, which is characterized in that include the following steps:
A wafer is provided, the wafer has opposite first surface and second surface;
Cutting being carried out to the second surface from the first surface and forming several raceway grooves, the depth of the communication is less than the crystalline substance Round thickness;And
The wafer is etched along the raceway groove so that the depth of the raceway groove is gradually increased until with institute using etching solution The thickness for stating wafer is equal, to which separation forms multiple chips.
2. the forming method of chip as described in claim 1, it is characterised in that:The wafer is by the first surface to described Second surface is sequentially formed with passivation layer, metal layer, barrier layer and oxide layer, wherein from the first surface to described second Surface carried out in the step of cutting forms several raceway grooves, and the depth of the raceway groove is suitable for the exposure passivation layer.
3. the forming method of chip as claimed in claim 2, which is characterized in that further include:Using the first etching solution to described Passivation layer is etched until the exposure metal layer.
4. the forming method of chip as claimed in claim 3, it is characterised in that:First etching solution includes sulfuric acid, nitric acid Potassium and ammonium acid fluoride.
5. the forming method of chip as claimed in claim 3, which is characterized in that further include:Using the second etching solution to described Metal layer is etched until the exposure barrier layer.
6. the forming method of chip as claimed in claim 5, it is characterised in that:Second etching solution includes potassium hydroxide.
7. the forming method of chip as claimed in claim 5, which is characterized in that further include:Using third etching solution to described Barrier layer is etched until the exposure oxide layer.
8. the forming method of chip as claimed in claim 7, it is characterised in that:The third etching solution include ammonium hydroxide with And hydrogen peroxide.
9. the forming method of chip as claimed in claim 7, which is characterized in that further include:Using the 4th etching solution to described Oxide layer is etched until the depth of the raceway groove is equal to the thickness of the wafer.
10. the forming method of chip as described in claim 1, it is characterised in that:Using laser beam from the first surface to The second surface carries out cutting and forms the raceway groove.
CN201710173741.3A 2017-03-22 2017-03-22 The forming method of chip Pending CN108630599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710173741.3A CN108630599A (en) 2017-03-22 2017-03-22 The forming method of chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710173741.3A CN108630599A (en) 2017-03-22 2017-03-22 The forming method of chip

Publications (1)

Publication Number Publication Date
CN108630599A true CN108630599A (en) 2018-10-09

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Country Status (1)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144126A (en) * 1999-11-12 2001-05-25 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method
US6465158B1 (en) * 1999-10-26 2002-10-15 Disco Corporation Semiconductor wafer dividing method
CN1515026A (en) * 2002-02-28 2004-07-21 ������������ʽ���� Separation method of semiconductor wafer
CN101088157A (en) * 2004-11-01 2007-12-12 Xsil技术有限公司 Increasing die strength by etching during or after dicing
CN101399196A (en) * 2007-09-29 2009-04-01 中芯国际集成电路制造(上海)有限公司 Coarsening processing method for backing side of wafer
CN102544035A (en) * 2010-11-24 2012-07-04 美商豪威科技股份有限公司 Wafer dicing using scribe line etch
CN102969236A (en) * 2011-09-01 2013-03-13 株式会社迪思科 Wafer dividing method
CN104465360A (en) * 2014-12-25 2015-03-25 安徽安芯电子科技有限公司 Wafer and etching method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465158B1 (en) * 1999-10-26 2002-10-15 Disco Corporation Semiconductor wafer dividing method
JP2001144126A (en) * 1999-11-12 2001-05-25 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method
CN1515026A (en) * 2002-02-28 2004-07-21 ������������ʽ���� Separation method of semiconductor wafer
CN101088157A (en) * 2004-11-01 2007-12-12 Xsil技术有限公司 Increasing die strength by etching during or after dicing
CN101399196A (en) * 2007-09-29 2009-04-01 中芯国际集成电路制造(上海)有限公司 Coarsening processing method for backing side of wafer
CN102544035A (en) * 2010-11-24 2012-07-04 美商豪威科技股份有限公司 Wafer dicing using scribe line etch
CN102969236A (en) * 2011-09-01 2013-03-13 株式会社迪思科 Wafer dividing method
CN104465360A (en) * 2014-12-25 2015-03-25 安徽安芯电子科技有限公司 Wafer and etching method thereof

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Application publication date: 20181009

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