CN108628774B - Memory control circuit unit, memory storage device and signal receiving method - Google Patents
Memory control circuit unit, memory storage device and signal receiving method Download PDFInfo
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Abstract
本发明提供一种存储器控制电路单元、存储器存储装置及信号接收方法。在一范例实施例中，存储器控制电路单元的存储器接口电路接收来自易失性存储器的第一信号并响应于存储器接口电路的内部阻抗而将第一信号的电压值调整至一电压范围，其中此电压范围的中间值不等于一预设电压值，且此预设电压值为存储器接口电路的供应电压的电压值与参考接地电压的电压值的总和的一半。此外，存储器接口电路还根据第一信号与内部参考电压之间的电压相对关系产生输入信号。
The present invention provides a memory control circuit unit, a memory storage device and a signal receiving method. In an exemplary embodiment, the memory interface circuit of the memory control circuit unit receives the first signal from the volatile memory and adjusts the voltage value of the first signal to a voltage range in response to the internal impedance of the memory interface circuit, wherein the The middle value of the voltage range is not equal to a predetermined voltage value, and the predetermined voltage value is half of the sum of the voltage value of the supply voltage of the memory interface circuit and the voltage value of the reference ground voltage. In addition, the memory interface circuit also generates the input signal according to the voltage relative relationship between the first signal and the internal reference voltage.
Description
Technical Field
The present invention relates to a signal receiving technology, and in particular, to a memory control circuit unit, a memory storage device, and a signal receiving method.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Some types of memory devices are configured with volatile memories such as a rewritable nonvolatile memory module and a Dynamic Random Access Memory (DRAM) to provide long-term storage and temporary buffering of data. In a memory device equipped with a volatile memory, a terminating resistor is generally provided in a memory interface circuit as a signal receiving end of the volatile memory in order to maintain signal quality of a high-speed signal from the volatile memory. However, the setting of the termination resistor also increases the power consumption of the signal receiving end.
Disclosure of Invention
The invention provides a memory control circuit unit, a memory storage device and a signal receiving method, which can reduce power consumption when a memory interface circuit receives signals from a volatile memory.
An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a volatile memory, the memory control circuit unit including a memory controller and a memory interface circuit. The memory interface circuit is connected to the memory controller. The memory interface circuit is to receive a first signal from the volatile memory. The memory interface circuit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit. The middle value of the voltage range is not equal to the preset voltage value. The preset voltage value is half of the sum of the voltage value of the supply voltage of the memory interface circuit and the voltage value of the reference grounding voltage. The memory interface circuit is also used for generating an input signal according to the voltage relative relation between the first signal and an internal reference voltage.
In an exemplary embodiment of the invention, the memory interface circuit includes an impedance element for providing the internal impedance, wherein a first terminal of the impedance element is connected to a receiving path of the first signal, and a second terminal of the impedance element is connected to the supply voltage or the reference ground voltage.
In an exemplary embodiment of the invention, the memory interface circuit is further configured to receive a second signal from the volatile memory before receiving the first signal. The memory interface circuit is also used for performing voltage division operation on the second signal to generate the internal reference voltage.
In an exemplary embodiment of the invention, the memory interface circuit is further configured to send a predetermined read command sequence to instruct reading of predetermined data of the volatile memory. The volatile memory is used for generating the second signal according to the preset reading instruction sequence.
In an exemplary embodiment of the present invention, the memory interface circuit includes a comparison circuit. The comparison circuit is used for comparing the internal reference voltage with the voltage value of the first signal to generate the input signal.
In an exemplary embodiment of the present invention, the memory interface circuit includes a first connection interface, a second connection interface, and a reference voltage generator. The first connection interface is used for connecting to the memory controller. The second connection interface is used for connecting to the volatile memory. The reference voltage generator is connected to the first connection interface and the second connection interface. The reference voltage generator is used for detecting the internal impedance through the first connecting interface, detecting the external impedance of the volatile memory through the second connecting interface and generating the internal reference voltage according to the detection result.
In an exemplary embodiment of the present invention, the reference voltage generator includes a voltage detection circuit for detecting a first voltage of an impedance element in the memory interface circuit in response to the internal impedance and the external impedance. A voltage value of the first voltage positively correlates to the voltage value of the supply voltage.
In an exemplary embodiment of the invention, the reference voltage generator further includes a voltage divider circuit and a voltage output circuit. The voltage division circuit is connected to the voltage detection circuit and is used for performing voltage division operation on a second voltage at the output end of the voltage detection circuit. The voltage output circuit is connected to the voltage dividing circuit and is used for responding to a third voltage of an output end of the voltage dividing circuit to generate the internal reference voltage.
Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a volatile memory, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable nonvolatile memory module and the volatile memory. The memory control circuit unit is used for receiving a first signal from the volatile memory. The memory control circuit unit is also used for responding to the internal impedance of the memory control circuit unit and adjusting the voltage value of the first signal to a voltage range. The middle value of the voltage range is not equal to the preset voltage value. The preset voltage value is half of the sum of the voltage value of the supply voltage of the memory interface circuit and the voltage value of the reference grounding voltage. The memory control circuit unit is also used for generating an input signal according to the voltage relative relation between the first signal and an internal reference voltage.
In an exemplary embodiment of the present invention, the memory control circuit unit includes an impedance element for providing the internal impedance. A first end of the impedance element is connected to a receiving path of the first signal, and a second end of the impedance element is connected to the supply voltage or the ground reference voltage.
In an exemplary embodiment of the invention, the third terminal of the impedance element is configured to receive an enable signal, wherein the impedance element provides the internal impedance in response to the enable signal.
In an exemplary embodiment of the invention, the enabling time of the enabling signal is positively correlated to the total number of the binary bits continuously transmitted via the first signal.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to receive a second signal from the volatile memory before receiving the first signal. The memory control circuit unit is also used for performing voltage division operation on the second signal to generate the internal reference voltage.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to send a predetermined read command sequence to instruct reading of predetermined data of the volatile memory. The volatile memory is used for generating the second signal according to the preset reading instruction sequence.
In an exemplary embodiment of the present invention, the memory control circuit unit includes a comparison circuit. The comparison circuit is used for comparing the internal reference voltage with the voltage value of the first signal to generate the input signal.
In an exemplary embodiment of the invention, the volatile memory is configured to provide an external impedance. The voltage value of the first signal is also adjusted to the voltage range in response to the external impedance.
Another exemplary embodiment of the present invention provides a signal receiving method for a memory storage device including a volatile memory, the signal receiving method including: receiving, by a memory interface circuit, a first signal from the volatile memory; adjusting a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, wherein a middle value of the voltage range is not equal to a preset voltage value, and the preset voltage value is half of a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage; and generating an input signal according to the voltage relative relation between the first signal and the internal reference voltage.
In an exemplary embodiment of the present invention, the signal receiving method further includes: the internal impedance is provided by an impedance element of the memory interface circuit, wherein a first end of the impedance element is connected to a receive path of the first signal and a second end of the impedance element is connected to the supply voltage or the ground reference voltage.
In an exemplary embodiment of the present invention, the signal receiving method further includes: receiving an enabling signal from the third end of the impedance element; and providing, by the impedance element, the internal impedance in response to the enable signal.
In an exemplary embodiment of the present invention, the signal receiving method further includes: controlling an enabling time of the enabling signal so that the enabling time is positively correlated to a total number of the plurality of binary bits continuously transmitted via the first signal.
In an exemplary embodiment of the present invention, the signal receiving method further includes: receiving, by the memory interface circuit, a second signal from the volatile memory prior to receiving the first signal; and performing a voltage division operation on the second signal to generate the internal reference voltage.
In an exemplary embodiment of the present invention, the signal receiving method further includes: sending a preset reading instruction sequence to indicate to read preset data of the volatile memory; and generating, by the volatile memory, the second signal according to the preset read instruction sequence.
In an exemplary embodiment of the present invention, the step of generating the input signal according to the voltage relative relationship between the first signal and the internal reference voltage comprises: comparing the internal reference voltage to the voltage value of the first signal; and generating the input signal according to the comparison result.
In an exemplary embodiment of the present invention, the signal receiving method further includes: providing an external impedance by the volatile memory; and adjusting the voltage value of the first signal to the voltage range in response to the external impedance.
In an exemplary embodiment of the invention, the volatile memory includes a fourth generation double data rate synchronous dynamic random access memory.
Based on the above, the present invention proposes to provide a specific receiving end circuit in the memory interface circuit to adjust the voltage value of the first signal from the volatile memory to the voltage range and to analyze the first signal using a suitable internal reference voltage. Therefore, the correctness of the generated input signal can be maintained, and the power consumption when the first signal is received can be reduced.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention.
FIG. 2 is a schematic diagram of a memory interface circuit according to an exemplary embodiment of the invention.
Fig. 3 is a diagram illustrating a first signal according to an exemplary embodiment of the present invention.
FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an exemplary embodiment of the invention.
FIG. 5 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention.
Fig. 6 is a diagram illustrating a first signal according to another exemplary embodiment of the present invention.
FIG. 7 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention.
Fig. 8 is a diagram illustrating a first signal according to another exemplary embodiment of the present invention.
FIG. 9 is a schematic diagram of a memory storage device according to another exemplary embodiment of the invention.
Fig. 10 is a flowchart illustrating a signal receiving method according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 90: memory storage device
11. 904: memory control circuit unit
111: memory controller
112: memory interface circuit
12. 908: volatile memory
21. 22, R1, R2, R3, R4: impedance element
23: comparison circuit
ENA, ENB, SRX, SIN, VREF, V1, V2, V3: signal
TA, TB: transistor with a metal gate electrode
OPA: operational amplifier
VDD: supply voltage
GND: reference ground voltage
40: reference voltage generating circuit
41: voltage detection circuit
42: voltage divider circuit
43: voltage output circuit
VCEN: preset voltage
VIH: upper critical voltage
VIL: lower critical voltage
902: connection interface unit
906: rewritable nonvolatile memory module
S1001: step (receiving a first signal from the volatile memory by the memory interface circuit)
S1002: step (adjusting the voltage value of the first signal to a voltage range in response to the internal impedance of the memory interface circuit)
S1003: step (generating an input signal based on a voltage-related relationship between the first signal and an internal reference voltage)
Detailed Description
The present invention will be described in more detail with reference to exemplary embodiments, but the present invention is not limited to the exemplary embodiments. Also, suitable combinations between the exemplary embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
FIG. 1 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 1, a memory storage device 10 includes a memory control circuit unit 11 and a volatile memory 12. The memory control circuit unit 11 may be packaged as a chip or composed of electronic circuits arranged on at least one circuit board. In the exemplary embodiment, the volatile Memory 12 is a fourth generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR 4 SDRAM). In another exemplary embodiment, the volatile memory 12 may also include other types of volatile memory, such as third generation double data rate synchronous dynamic random access memory (DDR 3SDRAM), etc. In addition, the total number of volatile memories 12 may be one or more.
The memory control circuit unit 11 and the volatile memory 12 are mounted on one or more circuit boards in the memory storage device 10. The memory control circuit unit 11 supports a data access operation to the volatile memory 12. In an example embodiment, the memory control circuit unit 11 is regarded as a control chip of the volatile memory 12, and the volatile memory 12 is regarded as a cache memory or a buffer memory (buffer) of the memory control circuit unit 11.
The memory control circuit unit 11 includes a memory controller 111 and a memory interface circuit 112. The memory controller 111 is connected to a memory interface circuit 112. The memory controller 112 is used to control the volatile memory 12. In an example embodiment, the memory controller 112 is also referred to as a dynamic random access memory controller (DRAM controller).
The memory interface circuit 112 is used to connect the memory controller 111 to the volatile memory 12. When data is to be read from the volatile memory 12 or stored in the volatile memory 12, the memory controller 111 sends a command sequence to the volatile memory 12 through the memory interface circuit 112. When the volatile memory 12 receives the command sequence, the volatile memory 12 stores write data corresponding to the command sequence or returns read data corresponding to the command sequence to the memory controller 111 via the memory interface circuit 112. Further, in the memory interface circuit 112, write data or read data is transmitted in the form of a data signal. For example, the data signal may be used to transmit binary bit data comprising a binary bit "1" and a binary bit "0".
In the exemplary embodiment, the volatile memory 12 is a double data rate synchronous dynamic random access memory (ddr sdram), and therefore both the rising edge (rising edges) and the falling edge (falling edges) of the clock signal of the memory interface circuit 112 can be used to analyze (e.g., sample) the data signal from the volatile memory 12. In other words, the memory interface circuit 112 may perform two data writes or reads to the volatile memory 12 within one clock cycle.
In the present exemplary embodiment, memory interface circuit 112 conforms to a Stub Series Terminated Logic (SSTL) I/O standard, such as SSTL-2, SSTL-3, SSTL-15, or SSTL-18, for example. In the present exemplary embodiment, the memory interface circuit 112 includes a connection interface 1311 (also referred to as a first connection interface) and a connection interface 1312 (also referred to as a second connection interface). The connection interface 1311 is used to connect the memory controller 111 and the memory interface circuit 112, and the connection interface 1312 is used to connect the memory interface circuit 112 and the volatile memory 12. In the present exemplary embodiment, the connection interface 1312 includes a plurality of conductive pins (pins). The memory interface circuit 112 is connected to the volatile memory 12 via such conductive pins. In the exemplary embodiment, the conductive pins include at least one pin (also referred to as a data pin) for transmitting data signals. For example, the data pin may be a DQ pin. Thus, data signals can be transmitted between the memory interface circuit 112 and the volatile memory 12 via the data pin. In another exemplary embodiment, the conductive pins may also include other functional pins as long as the connection standard is met. In addition, in an exemplary embodiment, the connection interface 1311 may also include at least one conductive pin. The total number of conductive pins in the connection interface 1311 may be the same or different from the total number of conductive pins in the connection interface 1312.
FIG. 2 is a schematic diagram of a memory interface circuit according to an exemplary embodiment of the invention. Referring to fig. 1 and 2, the memory interface circuit 112 receives a signal SRX (also referred to as a first signal) from the volatile memory 12. The memory interface circuit 112 then analyzes the signal SRX and generates a signal SIN (also referred to as an input signal). For example, the memory controller 111 can recognize that the binary bit data represented by the signal SRX is a binary bit "0" or "1" according to the pattern of the signal SIN.
In the present exemplary embodiment, the memory interface circuit 112 includes an impedance element 21, an impedance element 22 and a comparison circuit 23. The comparison circuit 23 is connected to the impedance element 21 and the impedance element 22. A first terminal of the impedance element 21 is connected to the reception path of the signal SRX, and a second terminal of the impedance element 21 is connected to the supply voltage VDD of the memory interface circuit 112. In addition, the first terminal of the impedance element 22 is also connected to the receiving path of the signal SRX, and the second terminal of the impedance element 22 is connected to the ground reference voltage GND of the memory interface circuit 112. From another perspective, the impedance elements 21 and 22 are connected in series between the supply voltage VDD and the ground reference voltage GND of the memory interface circuit 112.
In the present exemplary embodiment, the impedance element 21 includes at least one transistor TA, and the impedance element 22 includes at least one transistor TB. The transistors TA and TB may provide the equivalent impedance of the internal impedance together or separately. However, in another exemplary embodiment, the impedance elements 21 and 22 may also include at least one resistor or other electronic elements for providing a resistance value or a reactance value, respectively.
In the present exemplary embodiment, the third terminal of the impedance element 21 is configured to receive the signal ENA, and the third terminal of the impedance element 22 is configured to receive the signal ENB. The signal ENA is an enable signal for activating the impedance element 21, and the signal ENB is an enable signal for activating the impedance element 22. The impedance element 21 is activated when receiving the signal ENA. If the impedance element 21 is activated, a path (also referred to as a first impedance path) between the receiving path of the signal SRX and the supply voltage VDD is turned on, and the signal SRX is affected by the impedance provided by the impedance element 21. Conversely, if the signal ENA is not received, the impedance element 21 is not activated and the signal SRX is not affected by the impedance provided by the impedance element 21. In other words, the impedance element 21 may provide an internal impedance to the receive path of the signal SRX in response to the signal ENA.
On the other hand, when the signal ENB is received, the impedance element 22 is activated. If the impedance element 22 is activated, a path (also referred to as a second impedance path) between the receiving path of the signal SRX and the ground reference voltage GND is turned on, and the signal SRX is affected by the impedance provided by the impedance element 22. Conversely, if the signal ENB is not received, the impedance element 22 is not activated, and the signal SRX is not affected by the impedance provided by the impedance element 22. In other words, impedance element 22 may provide an internal impedance to a receive path of signal SRX in response to signal ENB.
Fig. 3 is a diagram illustrating a first signal according to an exemplary embodiment of the present invention. Referring to fig. 2 and 3, if the impedance elements 21 and 22 are activated (i.e., the signals ENA and ENB are present at the same time) within a certain time range, the voltage of the signal SRX is adjusted to a voltage range (also referred to as a predetermined voltage range) in response to the impedance provided by the impedance elements 21 and 22. The upper threshold voltage of the predetermined voltage range is close to (or equal to) the voltage value of the supply voltage VDD, and the lower threshold voltage of the predetermined voltage range is close to (or equal to) the voltage value of the ground reference voltage GND, as shown in fig. 3. In other words, under the influence of the impedance commonly provided by the impedance elements 21 and 22, the voltage value of the signal SRX fluctuates between the voltage value of the supply voltage VDD and the voltage value of the ground reference voltage GND. However, it should be noted that the voltage value of the signal SRX is not higher than the voltage value of the supply voltage VDD nor lower than the voltage value of the ground reference voltage GND.
On the other hand, a signal VREF (also referred to as an internal reference voltage) is used to determine whether the current signal SRX is used to deliver a binary bit "1" or "0". For example, in the example embodiment of fig. 3, the voltage value of the signal VREF is (approximately) equal to an intermediate value (also referred to as a preset voltage value) between the voltage value of the supply voltage VDD and the voltage value of the ground reference voltage GND. For example, the predetermined voltage value is (approximately) equal to half of the sum of the voltage value of the supply voltage VDD and the voltage value of the ground reference voltage GND. If the voltage value of the current signal SRX is higher than the voltage value of the signal VREF, it indicates that the current signal SRX is used to transmit a binary bit "1". If the voltage value of the current signal SRX is lower than the voltage value of the signal VREF, it indicates that the current signal SRX is used to transmit a binary bit "0".
It is noted that in the alternative embodiment of fig. 3, if the voltage value of the current signal SRX is higher than the voltage value of the signal VREF, it can be considered that the current signal SRX is used to transfer a binary bit "0". If the voltage value of the current signal SRX is lower than the voltage value of the signal VREF, it can be considered that the current signal SRX is used to transmit a binary bit "1".
Specifically, the memory interface circuit 112 generates the signal SIN according to the voltage relationship between the signal SRX and the signal VREF. For example, the comparison circuit 23 may include an operational amplifier (OPA). The comparison circuit 23 receives the signal SRX and the signal VREF and compares the voltage values of the signal SRX and the signal VREF. By comparing the voltage values of the signal SRX and the signal VREF, a voltage relative relationship between the signal SRX and the signal VREF can be obtained. If the voltage-relative relationship between the signal SRX and the signal VREF is such that the voltage value of the signal SRX is higher than the voltage value of the signal VREF, a signal SIN corresponding to a certain binary bit data (e.g., binary bit "1") is output. If the voltage-to-voltage relationship between the signal SRX and the signal VREF is such that the voltage value of the signal SRX is lower than the voltage value of the signal VREF, a signal SIN corresponding to another binary bit data (e.g., binary bit "0") is output. In other words, according to the voltage relationship between the signal SRX and the signal VREF, the binary bit data transmitted by the signal SRX can be obtained.
In the exemplary embodiment, the memory interface circuit 112 also dynamically generates the signal VREF based on the impedance currently provided by the memory interface circuit 112 (i.e., the internal impedance) and the impedance provided by the volatile memory 12 (also referred to as the external impedance). For example, at least one impedance element is also disposed in the volatile memory 12 to provide this external impedance. In an exemplary embodiment, the impedance element in the volatile memory 12 for providing the external impedance is also referred to as an off-chip driver (OCD) impedance element. More specifically, in the exemplary embodiment of FIG. 3, the signal SRX from the volatile memory 12 is substantially affected by both the internal impedance of the memory interface circuit 112 and the external impedance of the volatile memory 12, such that the voltage level of the signal SRX is adjusted to the predetermined voltage range of FIG. 3.
In one exemplary embodiment, when the signal VREF is to be generated, the volatile memory 12 sends a signal (also referred to as a second signal) that meets a specified condition to the memory interface circuit 112. Memory interface circuitry 112 may receive the second signal on a receive path of signal SRX. In other words, the second signal is also affected by the internal impedance of the memory interface circuit 112 and the external impedance of the volatile memory 12. Then, the memory interface circuit 112 performs a voltage division operation on the second signal, thereby generating the signal VREF.
In an exemplary embodiment, the second signal refers to a signal for transmitting at least one specific binary bit. For example, in one exemplary embodiment, the specific bit is a "0" bit, so the voltage level of the second signal is the same as (or close to) the lower threshold voltage of the predetermined voltage range of FIG. 3. Then, a voltage division operation is performed on the second signal according to the supply voltage VDD detected in real time, and the signal VREF may be dynamically generated.
FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an exemplary embodiment of the invention. Referring to fig. 1 to 4, in an exemplary embodiment, the memory interface circuit 112 further includes a reference voltage generating circuit 40 connected to the connection interfaces 1311 and 1312. For example, an input terminal of the reference voltage generation circuit 40 is connected to the reception path of the signal SRX, and an output terminal of the reference voltage generation circuit 40 is connected to the comparison circuit 23. Thereby, the reference voltage generating circuit 40 can detect the internal impedance of the memory interface circuit 112 via the connection interface 1311 and the external impedance of the volatile memory 12 via the connection interface 1312 and then generate the signal VREF according to the detection result.
In the exemplary embodiment of fig. 4, the reference voltage generating circuit 40 includes a voltage detecting circuit 41, a voltage dividing circuit 42 and a voltage output circuit 43. When the memory interface circuit 112 is connected to the volatile memory 12, the voltage detection circuit 41 is connected between the resistance element R1 and the resistance element R2. Where the resistance element R1 represents an equivalent resistance that provides the internal resistance of the memory interface circuit 112 and the resistance element R2 represents an equivalent resistance that provides the external resistance of the volatile memory 12.
When the memory interface circuit 112 receives the second signal, the voltage detection circuit 41 detects the signal V1 (i.e., the second signal) between the impedance element R1 and the impedance element R2 and generates the signal V2 in response to the internal impedance provided by the impedance element R1 and the external impedance provided by the impedance element R2. In an exemplary embodiment, the signal V1 refers to a voltage (also referred to as a first voltage) at one end of the resistor R1, and the voltage value thereof is positively correlated to the voltage value of the supply voltage VDD connected to the other end of the resistor R1. Further, the signal V2 is also referred to as a second voltage. For example, the voltage level of the signal V2 may be locked to the voltage level of the signal V1. For example, the voltage level of the signal V2 may be the same as (or close to) the voltage level of the signal V1. Taking fig. 3 as an example, the voltage level of the signal V2 is equal to (or close to) the lower threshold voltage of the predetermined voltage range.
The voltage dividing circuit 42 is connected to the voltage detection circuit 41 and configured to perform a voltage dividing operation on the signal V2 at the output terminal of the voltage detection circuit 41. For example, the voltage divider circuit 42 includes impedance elements R3 and R4. A first terminal of the impedance element R3 is connected to the supply voltage VDD, a first terminal of the impedance element R4 is connected to the voltage detection circuit 41 to receive the signal V2, and a second terminal of the impedance element R3 is connected to a second terminal of the impedance element R4. In addition, the impedance elements R3 and R4 provide the same (or similar) impedance value. The voltage divider circuit 42 performs a voltage dividing operation according to the supply voltage VDD and the signal V2 to generate a signal V3 (also referred to as a third voltage). The voltage level of the signal V3 is (approximately) equal to half of the sum of the voltage level of the supply voltage VDD and the voltage level of the signal V2.
The voltage output circuit 43 is connected to the voltage divider circuit 42 and generates the signal VREF in response to a signal V3 at the output of the voltage divider circuit 42. For example, the voltage level of the signal VREF may be locked to the voltage level of the signal V3. For example, the voltage level of the signal VREF is the same (or close) to the voltage level of the signal V3. The signal VREF may then be provided to the comparison circuit 23 of fig. 2. In addition, in an exemplary embodiment, the voltage value or the generation parameter of the signal VREF may be recorded in a memory element such as a register (register). Thus, after stopping receiving the second signal, the voltage output circuit 43 (or the memory interface circuit 112) may continue to generate the signal VREF according to the recorded voltage value or the generation parameter. In addition, in an exemplary embodiment, after stopping receiving the second signal, at least one of the voltage detecting circuit 41 and the voltage dividing circuit 42 may be disabled (disabled) to save power.
In an exemplary embodiment, the operation of generating the signal VREF according to the second signal can also be regarded as an internal reference signal generating operation. For example, the internal reference signal generation operation is performed before the signal VREF is actually used to generate the signal SIN and is used to dynamically determine the voltage value of the signal VREF. That is, in an exemplary embodiment, before receiving the first signal, the memory interface circuit 112 receives the second signal and determines the voltage value of the internal reference signal for analyzing the first signal according to the second signal.
In an exemplary embodiment, the memory controller 111 sends at least one predetermined read command to the volatile memory 12 via the memory interface circuit 112. The predetermined read command is used to instruct the volatile memory 12 to read a predetermined data. This preset data includes at least one specific binary bit (e.g., binary bit "0"). According to the predetermined read command, the volatile memory 12 generates the second signal.
In an exemplary embodiment, according to the predetermined read command, the volatile memory 12 automatically stores the predetermined data and then performs an operation of reading the predetermined data to generate the second signal. Thereby, the memory controller 111 does not send an additional write command to instruct the storage of the predetermined data in the volatile memory 12 before sending the predetermined read command. In addition, in an exemplary embodiment, the volatile memory 12 generates the second signal without actually performing a data access operation according to the predetermined read command. Alternatively, in another exemplary embodiment, the preset data may be an additional write command sent by the memory controller 111 to indicate that the preset data is stored in the volatile memory 12 before the preset read command is sent, which is not limited in the invention.
In an exemplary embodiment, only one of the impedance elements 21 and 22 is activated. For example, if the signal ENA is present and the impedance element 21 is enabled, the signal ENB will not be present within a certain time frame. At this time, the activated impedance element 21 may provide an internal impedance to the receiving path of the signal SRX, while the deactivated impedance element 22 does not provide an internal impedance. Alternatively, if signal ENB is present and impedance element 22 is enabled, signal ENA will not be present for a certain time period. At this time, the activated impedance element 22 may provide an internal impedance to the receive path of the signal SRX, while the deactivated impedance element 21 does not provide an internal impedance. By activating only one of the impedance elements 21 and 22, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be reduced.
In an example embodiment, an enable time of the signal ENA or ENB may also be dynamically adjusted. For example, the enable time of signal ENA or ENB may be positively correlated to the total number of bits that are continuously transmitted via signal SRX. It should be noted that the enabling time refers to the existence time of the signal. For example, the enabling time of the signal ENA positively correlates to the time length of the impedance element 21 in the activated state, and the enabling time of the signal ENB positively correlates to the time length of the impedance element 22 in the activated state.
In an exemplary embodiment, it is assumed that the transmission specification of the signal SRX is to continuously transmit n binary bits of data. For example, n may be 4, 8, 16, or 32 or greater or less. If n is larger, the enabling time of the signal ENA or ENB is longer. Thus, it is ensured that (at least) one of the impedance elements 21 and 22 is continuously activated until the binary bit data from the volatile memory 12 is completely received. After receiving the binary bit data from the volatile memory 12 completely, the signal ENA or ENB may be stopped from being provided. Thus, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be further reduced.
In one exemplary embodiment, only one of the impedance devices 21 and 22 is disposed in the memory interface circuit 112. Thus, the power consumption of the memory interface circuit 112 when receiving the signal SRX can be reduced, and the layout area of the receiving side circuit in the memory interface circuit 112 can be further reduced.
FIG. 5 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. Fig. 6 is a diagram illustrating a first signal according to another exemplary embodiment of the present invention. Referring to fig. 5 and fig. 6, in the present exemplary embodiment, the memory interface circuit 112 is provided with the impedance element 21, but is not provided with the impedance element 22. The voltage value of the signal SRX is adjusted to a voltage range (also referred to as a first voltage range) in response to the internal impedance provided by the impedance element 21. The first voltage range has an upper threshold voltage VIH (also referred to as a first threshold voltage) and a lower threshold voltage VIL (also referred to as a second threshold voltage). The voltage value of the upper critical voltage VIH is higher than that of the lower critical voltage VIL. In other words, in the exemplary embodiments of fig. 5 and 6, the voltage value of the signal SRX fluctuates within the first voltage range due to the internal impedance provided by the impedance element 21, depending on the binary bit data to be transmitted. In addition, in the exemplary embodiment of fig. 5 and 6, the voltage value of the signal SRX does not exceed the first voltage range.
It is noted that, in the exemplary embodiments of fig. 5 and 6, the first voltage range is different from the predetermined voltage range of fig. 3, and an intermediate value of the first voltage range is different from a voltage value of the predetermined voltage VCEN. For example, the middle value of the first voltage range may be higher than the preset voltage VCEN. The middle value of the first voltage range is equal to half of the sum of the voltage values of the upper threshold voltage VIH and the lower threshold voltage VIL, and the voltage value of the preset voltage VCEN (i.e., the preset voltage value) is equal to half of the sum of the voltage value of the supply voltage VDD and the voltage value of the ground reference voltage GND. In addition, the upper threshold voltage VIH may have the same voltage value (or close to) the supply voltage VDD. It should be noted that although fig. 6 illustrates that the voltage value of the lower threshold voltage VIL is higher than the predetermined voltage VCEN, in another exemplary embodiment of fig. 6, the voltage value of the lower threshold voltage VIL may be lower than the predetermined voltage VCEN, depending on the configuration of the internal impedance and the external impedance.
In the exemplary embodiments of fig. 5 and 6, the signal VREF is also dynamically generated by the memory interface circuit 112. For example, according to the exemplary embodiment of FIG. 4, the voltage level of the signal V2 (or the signal V1) is the same as (or close to) the voltage level of the lower threshold voltage VIL of FIG. 6. After performing the voltage dividing operation according to the signal V2 and the supply voltage VDD, the signal VREF may be generated. For example, the voltage level of the signal VREF is the same (or close to) the middle of the first voltage range, as shown in fig. 6. For details of generating the signal VREF, reference may be made to the foregoing description, and further description is omitted here.
In addition, in another exemplary embodiment of fig. 5, the impedance element 21 may also be implemented by at least one electronic element such as a resistor, which can provide a resistance value or a reactance value. Thus, the impedance element 21 can continuously provide a receiving path for the internal impedance signal SRX without being controlled by the signal ENA.
FIG. 7 is a schematic diagram of a memory interface circuit according to another exemplary embodiment of the invention. Fig. 8 is a diagram illustrating a first signal according to another exemplary embodiment of the present invention. Referring to fig. 7 and 8, in the present exemplary embodiment, the memory interface circuit 112 is provided with the impedance element 22, but is not provided with the impedance element 21. The voltage value of the signal SRX is adjusted to another voltage range (also referred to as a second voltage range) in response to the internal impedance provided by the impedance element 22. The second voltage range also has an upper threshold voltage VIH and a lower threshold voltage VIL. The voltage value of the upper critical voltage VIH is higher than that of the lower critical voltage VIL. In other words, in the exemplary embodiments of fig. 7 and 8, the voltage value of the signal SRX fluctuates within the second voltage range due to the internal impedance provided by the impedance element 22, depending on the binary bit data being transmitted. In addition, in the exemplary embodiment of fig. 7 and 8, the voltage value of the signal SRX does not exceed the second voltage range.
It is noted that, in the exemplary embodiments of fig. 7 and 8, the second voltage range is different from the predetermined voltage range of fig. 3, and an intermediate value of the second voltage range is different from the voltage value of the predetermined voltage VCEN. The middle value of the second voltage range is equal to half of the sum of the voltage value of the upper threshold voltage VIH and the voltage value of the lower threshold voltage VIL. For example, the middle value of the second voltage range may be lower than the voltage value of the preset voltage VCEN. In addition, the voltage value of the lower threshold voltage VIL may be the same (or close) to the voltage value of the ground reference voltage GND. It should be noted that although fig. 8 illustrates that the voltage level of the upper threshold voltage VIH is lower than the predetermined voltage VCEN, in another exemplary embodiment of fig. 8, the voltage level of the upper threshold voltage VIH may be higher than the predetermined voltage VCEN depending on the configuration of the internal impedance and the external impedance.
In the exemplary embodiments of fig. 7 and 8, the signal VREF is also dynamically generated by the memory interface circuit 112. For example, according to the exemplary embodiment of FIG. 4, the voltage level of the signal V2 (or the signal V1) is the same as (or close to) the voltage level of the upper threshold voltage VIH in FIG. 8. If the supply voltage VDD connected to the voltage dividing circuit 42 is replaced with the ground reference voltage GND, the signal VREF may be generated after performing the voltage dividing operation according to the signal V2 and the ground reference voltage GND. For example, the voltage value of the signal VREF is the same (or close to) the middle value of the second voltage range, as shown in fig. 8.
In addition, in another exemplary embodiment of fig. 7, the impedance element 22 may also be implemented by at least one electronic element such as a resistor, which can provide a resistance value or a reactance value. Thus, the impedance element 22 can continuously provide a receiving path of the internal impedance signal SRX without being controlled by the signal ENB.
FIG. 9 is a schematic diagram of a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 9, the memory storage device 90 is, for example, a Solid State Drive (SSD) or the like, and includes a rewritable nonvolatile memory module 906 and a volatile memory 908. The memory storage device 90 may be used with a host system that may write data to the memory storage device 90 or read data from the memory storage device 90. The host system may be any system that can be substantially matched with the memory storage device 90 to store data, such as a desktop computer, a notebook computer, a digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like.
Specifically, the memory storage device 90 includes a connection interface unit 902, a memory control circuit unit 904, a rewritable nonvolatile memory module 906 and a volatile memory 908. The connection interface unit 902 is used to connect the memory storage device 90 to a host system. In the exemplary embodiment, connection interface unit 902 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 902 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard or other suitable standards. The connection interface unit 902 may be packaged with the memory control circuit unit 904 in one chip, or the connection interface unit 902 may be disposed outside a chip including the memory control circuit unit 904.
The memory control circuit unit 904 is used for performing data writing, reading, and erasing operations in the rewritable nonvolatile memory module 906 according to instructions of a host system. The rewritable nonvolatile memory module 906 is connected to the memory control circuit unit 904 and is used for storing data written by the host system. The rewritable nonvolatile memory module 906 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 binary bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 binary bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 binary bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
In the present exemplary embodiment, the memory control circuit unit 904 also has the same or similar functions and/or electronic circuit structures as the memory control circuit unit 11 mentioned in the exemplary embodiments of fig. 1 to 8, and the volatile memory 908 is the same or similar to the volatile memory 12 mentioned in the exemplary embodiment of fig. 1. Therefore, for the description of the memory control circuit unit 904 and the volatile memory 908, reference may be made to the exemplary embodiments of fig. 1 to 8, which are not repeated herein.
It should be noted that the electronic circuit structures shown in fig. 2, fig. 4, fig. 5 and fig. 7 are only schematic diagrams of a part of the memory interface circuit in the exemplary embodiment, and are not intended to limit the invention. In some applications not mentioned, more electronic components may be added to the memory interface circuit to provide additional functionality. In addition, in some applications not mentioned, the circuit layout and/or the connection relationship of the elements of the memory interface circuit may be changed as appropriate to meet the practical requirements.
Fig. 10 is a flowchart illustrating a signal receiving method according to an exemplary embodiment of the present invention. The signal receiving method can be applied to the memory storage device mentioned in the exemplary embodiment of fig. 1 or fig. 9. The following description will be made with reference to fig. 10 in addition to the memory storage device 10 of fig. 1.
Referring to fig. 1 and 10, in step S1001, the memory interface circuit 112 receives a first signal from the volatile memory 12. In step S1002, the voltage value of the first signal is adjusted to a voltage range by the memory interface circuit 112 in response to the internal impedance of the memory interface circuit 112. For example, this voltage range may be the first voltage range shown in fig. 6 or the second voltage range shown in fig. 8. In step S1003, an input signal is generated by the memory interface circuit 112 according to the voltage relative relationship between the first signal and the internal reference voltage.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, the present invention provides a specific receiving circuit in the memory interface circuit to adjust the voltage value of the first signal from the volatile memory to a specific voltage range and analyze the first signal using a suitable internal reference voltage. Therefore, the correctness of the generated input signal can be maintained, and the power consumption when the first signal is received can be reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (27)
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| CN112309444B (en) * | 2019-07-30 | 2023-10-13 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and setting state detection method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100202227A1 (en) * | 2007-07-19 | 2010-08-12 | Rambus Inc. | Reference voltage and impedance calibration in a multi-mode interface |
| CN103129151A (en) * | 2011-11-30 | 2013-06-05 | 珠海天威技术开发有限公司 | Storage chip, data communication method thereof, consumable container and imaging equipment thereof |
| US20140185374A1 (en) * | 2012-12-31 | 2014-07-03 | Sandisk Technologies Inc. | Nonvolatile memory and method with improved i/o interface |
| US20150205751A1 (en) * | 2012-07-20 | 2015-07-23 | Rambus Inc. | Reducing Unwanted Reflections in Source-Terminated Channels |
| CN107293320A (en) * | 2016-03-31 | 2017-10-24 | 三星电子株式会社 | Support the receiving interface circuit of a variety of communication standards and the storage system including it |
-
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- 2017-03-17 CN CN201710161613.7A patent/CN108628774B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100202227A1 (en) * | 2007-07-19 | 2010-08-12 | Rambus Inc. | Reference voltage and impedance calibration in a multi-mode interface |
| CN103129151A (en) * | 2011-11-30 | 2013-06-05 | 珠海天威技术开发有限公司 | Storage chip, data communication method thereof, consumable container and imaging equipment thereof |
| US20150205751A1 (en) * | 2012-07-20 | 2015-07-23 | Rambus Inc. | Reducing Unwanted Reflections in Source-Terminated Channels |
| US20140185374A1 (en) * | 2012-12-31 | 2014-07-03 | Sandisk Technologies Inc. | Nonvolatile memory and method with improved i/o interface |
| CN107293320A (en) * | 2016-03-31 | 2017-10-24 | 三星电子株式会社 | Support the receiving interface circuit of a variety of communication standards and the storage system including it |
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