CN108598155A - Thin film transistor (TFT), array substrate and display device - Google Patents

Abstract

The invention discloses a thin film transistor, comprising a gate, a source-drain metal layer and a semiconductor layer; the gate is arranged on a transparent substrate; a gate insulating layer is also provided on the transparent substrate to cover the gate; The semiconductor layer is disposed on the gate insulating layer and above the gate; the source-drain metal layer is disposed on the semiconductor layer, including a source and a drain, and the source and the drain are disposed on the semiconductor layer. The drains are separated from each other and are in contact with the semiconductor layer, the semiconductor layer is provided with a channel, the channel is arranged between the source and the drain, and the gate is connected to the source and drain The metal layer has an overlapping area in a direction perpendicular to the transparent substrate, and at least one of the gate and the source-drain metal layer is provided with a device for reducing the gap between the gate and the source-drain metal layer. The hollow structure of the facing area. The invention also relates to an array substrate and a display device.

Description

Thin film transistor, array substrate and display device

technical field

The present invention relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display device.

Background technique

Display devices, such as liquid crystal display (liquid crystal display, LCD) have the advantages of good image quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and dominate the field of flat panel display. status. A liquid crystal display device includes several parts such as an array substrate, a color filter substrate, and a backlight module. The array substrate includes: a transparent substrate and a plurality of scan lines (Scan Line) and a plurality of data lines (Data Line) formed on the transparent substrate, and a plurality of scan lines and a plurality of data lines intersect each other to form a plurality of pixel units, each Each pixel unit includes a thin film transistor (ThinFilm Transistor, TFT) and a pixel electrode, and the thin film transistor is used as a switching device to control the state of the pixel unit.

As shown in Figure 1, the equivalent circuit of each pixel unit in the array substrate is composed of a thin film transistor, a pixel liquid crystal layer capacitor Clc, and a pixel storage capacitor Cst, and the pixel unit is electrically connected through the scan line through the gate G of the thin film transistor. The gate driver IC (Gate Driver IC), and the source S of the thin film transistor is electrically connected to the source driver IC (Source Driver IC) through the data line, and the drain D of the thin film transistor is electrically connected to a pixel electrode, a pixel liquid crystal layer capacitor and pixel storage capacitor. When the gate drive chip drives the gate of the thin film transistor through the scan line, the data voltage signal input from the source drive chip can be transmitted from the source and drain of the thin film transistor to the pixel liquid crystal layer capacitor and pixel through the data line. storage capacitor, and the voltage signal received by the pixel liquid crystal layer capacitor and the pixel storage capacitor is stored.

There are also several parasitic capacitances in the pixel circuit of the array substrate. As shown in FIG. 2, the existing thin film transistor includes a gate 10, a source 21, a drain 22 and a semiconductor layer 30 arranged on a transparent substrate (not shown), and the semiconductor layer 30 is arranged above the gate 10, The source 21 and the drain 22 are arranged in the same layer and are separated from each other and are in contact with the semiconductor layer 30 , a part of the semiconductor layer 30 is exposed between the source 21 and the drain 22 to form a channel 31 . In the direction perpendicular to the transparent substrate, there are overlapping regions between the gate 10 and the source 21, and between the gate 10 and the drain 22, which will generate parasitic capacitance, such as between the gate and the drain. The overlap capacitance Cgd, the overlap capacitance Cgs between the gate and the source, etc. When the gate driving chip raises the voltage on the scanning line to the high voltage Vgh on the scanning line, the source driving chip also raises the voltage on the data line to start charging the pixel electrode. When the voltage of the pixel electrode rises to a predetermined voltage, the voltage on the scan line drops to the scan line low voltage Vgl. At this time, the voltage drop on the scan line causes a coupling effect to the pixel electrode, so that the voltage on the pixel electrode also produces a voltage drop ΔVp. The voltage drop ΔVp is also called feed through voltage (Feed Through Voltage). The mathematical relationship expressed with the scan line low voltage (Vgl) is as follows:

△Vp=(Vgh-Vgl)×{Cgd/(Cgd+Clc+Cst)}

The feed-through voltage will cause problems such as flickering of the display screen, afterimages and gray scale disorder, and reduce the display quality of the display device. In the process of forming the feed-through voltage, the overlap capacitance Cgd between the gate and the drain has the greatest influence on the feed-through voltage. Furthermore, the width and length of the channel 31 will also affect the feedthrough voltage. The selection of the width and length of the channel 31 also involves the on-state current, off-state current, aperture ratio, etc. of the thin film transistor, so it is necessary to select the The width and length of the channel 31 are optimized after taking all parties into consideration. On the premise that the width and length of the channel 31 are constant, how to further reduce the feed-through voltage to improve the display quality is one of the problems to be solved by those in the industry.

Contents of the invention

The object of the present invention is to provide a thin film transistor, an array substrate and a display device, which can reduce the feed-through voltage and improve the display quality of the display device.

An embodiment of the present invention provides a thin film transistor, including a gate, a source-drain metal layer, and a semiconductor layer; the gate is disposed on a transparent substrate; a gate insulating layer is also provided on the transparent substrate to cover the gate ; the semiconductor layer is disposed on the gate insulating layer and located above the gate; the source-drain metal layer is disposed on the semiconductor layer, including a source and a drain, the source and The drains are separated from each other and are in contact with the semiconductor layer, the semiconductor layer is provided with a channel, the channel is arranged between the source and the drain, the gate is connected to the source and drain The electrode metal layer has an overlapping area in the direction perpendicular to the transparent substrate, and at least one of the gate and the source-drain metal layer is provided with a The hollow structure of the facing area.

Further, the hollow structure is a first hollow structure provided on the gate.

Further, the gate and the source have a first overlapping area in a direction perpendicular to the transparent substrate, and the gate and the drain have a second overlapping area in a direction perpendicular to the transparent substrate ; The first hollow structure includes a first hollow pattern arranged in the first overlapping region and a second hollow pattern arranged in the second overlapping region.

Further, the hollow structure is a second hollow structure disposed on the source and the drain.

Further, the source and the gate have a first overlapping area in a direction perpendicular to the transparent substrate, and the drain and the gate have a second overlapping area in a direction perpendicular to the transparent substrate; The second hollow structure includes a third hollow pattern arranged in the first overlapping region and a fourth hollow pattern arranged in the second overlapping region.

Further, the hollow structure is a first hollow structure disposed on the gate and a second hollow structure disposed on the source and the drain.

Further, the gate and the source have a first overlapping area in a direction perpendicular to the transparent substrate, and the gate and the drain have a second overlapping area in a direction perpendicular to the transparent substrate; The first hollow structure includes a first hollow pattern arranged in the first overlapping region and a second hollow pattern arranged in the second overlapping region; the second hollow structure includes a first hollow pattern arranged in the first overlapping region. A third hollow pattern in an overlapping area and a fourth hollow pattern arranged in the second overlapping area.

Further, the overlapping area of the first hollow structure and the second hollow structure in a direction perpendicular to the transparent substrate is greater than 80% of the total area of the first overlapping area and the second overlapping area above.

An embodiment of the present invention provides an array substrate, the array substrate includes a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines intersect to define a plurality of pixel units, each pixel The unit includes a pixel electrode, and each pixel unit further includes the above-mentioned thin film transistor, the gate of the thin film transistor is connected to the corresponding scanning line, and the drain of the thin film transistor is connected to the pixel electrode.

An embodiment of the present invention provides a display device, including the above-mentioned array substrate.

In the thin film transistor provided by the embodiment of the present invention, the gate and the source-drain metal layer have an overlapping area in the direction perpendicular to the transparent substrate, and at least one of the gate and the source-drain metal layer is provided with a The hollow structure of the facing area between the drain metal layers, by reducing the facing area between the gate and the source, the gate and the drain, thereby reducing the gate and the source, the gate and the drain The overlapping capacitance (parasitic capacitance) between the thin film transistors effectively reduces the feed-through voltage coupled to the pixel electrodes during the process of turning on the thin film transistors to charge the pixel electrodes, thereby improving the display quality of the display device.

Description of drawings

FIG. 1 is an equivalent circuit diagram of a pixel unit in an existing array substrate.

FIG. 2 is a schematic diagram of a partial structure of the thin film transistor shown in FIG. 1 .

FIG. 3 is a schematic diagram of a partial structure of a thin film transistor according to a first embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a gate of a thin film transistor according to a first embodiment of the present invention.

FIG. 5 is a schematic structural diagram of the source and drain of the thin film transistor according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view along line A-A in FIG. 3 .

FIG. 7 is a schematic diagram of a partial structure of a thin film transistor according to a second embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a gate of a thin film transistor according to a second embodiment of the present invention.

FIG. 9 is a schematic structural diagram of the source and drain of the thin film transistor according to the second embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view along line B-B in Fig. 7 .

FIG. 11 is a schematic diagram of a partial structure of a thin film transistor according to a third embodiment of the present invention.

FIG. 12 is a schematic structural diagram of a gate of a thin film transistor according to a third embodiment of the present invention.

FIG. 13 is a schematic structural diagram of the source and drain of the thin film transistor according to the third embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view along line C-C in FIG. 11 .

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, features and effects of the present invention will be described in detail below in conjunction with the accompanying drawings and examples.

[first embodiment]

Referring to FIGS. 3 to 6 , the thin film transistor provided by the first embodiment of the present invention includes a gate 110 , a source-drain metal layer 120 and a semiconductor layer 300 disposed on a transparent substrate 100 . Wherein, the gate 110 is arranged on the transparent substrate 100; the gate insulating layer 101 is also provided on the transparent substrate 100 to cover the gate 110; the semiconductor layer 300 is arranged on the gate insulating layer 101 and is located above the gate 110; The drain metal layer 120 is disposed on the semiconductor layer 300, including a source electrode 121 and a drain electrode 122. The source electrode 121 and the drain electrode 122 are separated from each other and are in contact with the semiconductor layer 300. The semiconductor layer 300 is provided with a channel 301, and the channel 301 is provided with between the source 121 and the drain 122 .

The source 121 is a "U"-shaped or "C"-shaped structure, but not limited thereto. The opening of the “U”-shaped or “C”-shaped structure of the source 121 faces the drain 122 .

One end of the drain 122 close to the source 121 is elongated and partially extends into the opening of the “U” or “C” structure of the source 121 . The other end of the drain 122 is used to connect to the pixel electrode.

The gate 110 and the source-drain metal layer 120 have overlapping areas in a direction perpendicular to the transparent substrate 100, and at least one of the gate 110 and the source-drain metal layer 120 is provided with a layer for reducing the size of the gate 110 and the source-drain metal layer. The hollow structure of the facing area between 120. In this embodiment, the gate 110 is provided with a first hollow structure 130 for reducing the facing area between the gate 110 and the source-drain metal layer 120 .

Specifically, the gate 110 and the source 121 have a first overlapping region S1 in a direction perpendicular to the transparent substrate 100 , and the gate 110 and the drain 122 have a second overlapping region S2 in a direction perpendicular to the transparent substrate 100 . The first hollow structure 130 is disposed in the first overlapping region S1 and the second overlapping region S2.

In this embodiment, the first hollow structure 130 includes a first hollow pattern 131 disposed in the first overlapping region S1 and a second hollow pattern 132 disposed in the second overlapping region S2. But it is not limited thereto, and in other embodiments, the hollow pattern can also be provided only in one of the overlapping regions.

In this embodiment, the total area of the first hollow structure 130 is more than 50% of the total area of the first overlapping region S1 and the second overlapping region S2.

As shown in FIG. 4, in this embodiment, the first hollow pattern 131 is two arc-shaped structures 1311 and 1312 concentrically arranged with the source 121, and the second hollow pattern 132 is a "U"-shaped structure, but not This is the limit.

The first hollow structure 130 is arranged on the gate 110, which reduces the facing area between the gate 110 and the source 121, and between the gate 110 and the drain 122, thereby reducing the area between the gate 110 and the source 121, the gate The overlap capacitance (parasitic capacitance) between the electrode 110 and the drain electrode 122 effectively reduces the feed-through voltage coupled to the pixel electrode when the thin film transistor is turned on to charge the pixel electrode.

The following table compares the characteristics of the thin film transistor of this embodiment and the thin film transistor of the prior art under the premise that the width and length of the channel are constant values. It can be seen from the table that the gate 110 of the thin film transistor of this embodiment Compared with the overlap capacitance between the drains 122 in the prior art, it is reduced (by 35%), and the minimum value and the maximum value of the feedthrough voltage of the thin film transistor of the present embodiment are lower than those in the prior art. Significant reductions (36% and 34% drops).

[Second embodiment]

Referring to FIG. 7 to FIG. 10 , the thin film transistor provided by the second embodiment of the present invention includes a gate 110 , a source-drain metal layer 120 and a semiconductor layer 300 disposed on a transparent substrate 100 . Wherein, the gate 110 is arranged on the transparent substrate 100; the gate insulating layer 101 is also provided on the transparent substrate 100 to cover the gate 110; the semiconductor layer 300 is arranged on the gate insulating layer 101 and is located above the gate 110; The drain metal layer 120 is disposed on the semiconductor layer 300, including a source electrode 121 and a drain electrode 122. The source electrode 121 and the drain electrode 122 are separated from each other and are in contact with the semiconductor layer 300. The semiconductor layer 300 is provided with a channel 301, and the channel 301 is provided with between the source 121 and the drain 122 .

The source 121 is a "U"-shaped or "C"-shaped structure, but not limited thereto. The opening of the “U”-shaped or “C”-shaped structure of the source 121 faces the drain 122 .

One end of the drain 122 close to the source 121 is elongated and partially extends into the opening of the “U” or “C” structure of the source 121 . The other end of the drain 122 is used to connect to the pixel electrode.

The gate 110 and the source-drain metal layer 120 have overlapping areas in a direction perpendicular to the transparent substrate 100, and at least one of the gate 110 and the source-drain metal layer 120 is provided with a layer for reducing the size of the gate 110 and the source-drain metal layer. The hollow structure of the facing area between 120. In this embodiment, the second hollow structure 140 for reducing the facing area between the gate 110 and the source-drain metal layer 120 is disposed on the source-drain metal layer 120 .

Specifically, the source 121 and the gate 110 have a first overlapping region S1 in a direction perpendicular to the transparent substrate 100 , and the drain 122 and the gate 110 have a second overlapping region S2 in a direction perpendicular to the transparent substrate 100 . The second hollow structure 140 is disposed on the first overlapping area S1 and the second overlapping area S2.

In this embodiment, the second hollow structure 140 includes a third hollow pattern 141 disposed in the first overlapping region S1 and a fourth hollow pattern 142 disposed in the second overlapping region S2. But it is not limited thereto, and in other embodiments, the hollow pattern can also be provided only in one of the overlapping regions.

In this embodiment, the total area of the second hollow structure 140 is greater than 30% of the total area of the first overlapping region S1 and the second overlapping region S2.

As shown in FIG. 7 , in this embodiment, the third hollow pattern 141 is an arc-shaped structure arranged concentrically with the source electrode 121 , and the fourth hollow pattern 142 is an arc structure that is in the same direction as the length of the end of the drain electrode 122 near the drain electrode 122 . The elongated structure, but not limited to this.

The second hollow structure 140 is provided on the source-drain metal layer 120, which reduces the facing area between the gate 110 and the source 121, and between the gate 110 and the drain 122, thereby reducing the distance between the gate 110 and the source. 121. The overlapping capacitance (parasitic capacitance) between the gate 110 and the drain 122 effectively reduces the feed-through voltage coupled to the pixel electrode when the thin film transistor is turned on to charge the pixel electrode.

The following table compares the characteristics of the thin film transistor of this embodiment and the thin film transistor of the prior art under the premise that the width and length of the channel are constant values. It can be seen from the table that the gate 110 of the thin film transistor of this embodiment Compared with the overlapping capacitance between the drains 122 in the prior art, it is reduced (by 3.2%), and the minimum value and the maximum value of the feedthrough voltage of the thin film transistor of the present embodiment are also reduced compared with the prior art. decrease (both down 4%).

[Third embodiment]

Referring to FIG. 11 to FIG. 14 , the thin film transistor provided by the third embodiment of the present invention includes a gate 110 , a source-drain metal layer 120 and a semiconductor layer 300 disposed on a transparent substrate 100 . Wherein, the gate 110 is arranged on the transparent substrate 100; the gate insulating layer 101 is also provided on the transparent substrate 100 to cover the gate 110; the semiconductor layer 300 is arranged on the gate insulating layer 101 and is located above the gate 110; The drain metal layer 120 is disposed on the semiconductor layer 300, including a source electrode 121 and a drain electrode 122. The source electrode 121 and the drain electrode 122 are separated from each other and are in contact with the semiconductor layer 300. The semiconductor layer 300 is provided with a channel 301, and the channel 301 is provided with between the source 121 and the drain 122 .

The source 121 is a "U"-shaped or "C"-shaped structure, but not limited thereto. The opening of the “U”-shaped or “C”-shaped structure of the source 121 faces the drain 122 .

One end of the drain 122 close to the source 121 is elongated and partially extends into the opening of the “U” or “C” structure of the source 121 . The other end of the drain 122 is used to connect to the pixel electrode.

The gate 110 and the source-drain metal layer 120 have overlapping areas in a direction perpendicular to the transparent substrate 100, and at least one of the gate 110 and the source-drain metal layer 120 is provided with a layer for reducing the size of the gate 110 and the source-drain metal layer. The hollow structure of the facing area between 120. In this embodiment, a first hollow structure 130 for reducing the facing area between the gate 110 and the source-drain metal layer 120 is provided on the gate 110; The second hollow structure 140 in the facing area between the electrode 110 and the source-drain metal layer 120 .

Specifically, the gate 110 and the source 121 have a first overlapping region S1 in a direction perpendicular to the transparent substrate 100 , and the gate 110 and the drain 122 have a second overlapping region S2 in a direction perpendicular to the transparent substrate 100 . Both the first hollow structure 130 and the second hollow structure 140 are disposed in the first overlapping region S1 and the second overlapping region S2.

In this embodiment, the first hollow structure 130 includes a first hollow pattern 131 disposed in the first overlapping region S1 and a second hollow pattern 132 disposed in the second overlapping region S2. But it is not limited thereto, and in other embodiments, the hollow pattern can also be provided only in one of the overlapping regions.

In this embodiment, the second hollow structure 140 includes a third hollow pattern 141 disposed in the first overlapping region S1 and a fourth hollow pattern 142 disposed in the second overlapping region S2. But it is not limited thereto, and in other embodiments, the hollow pattern can also be provided only in one of the overlapping regions.

In this embodiment, the total overlapping area of the first hollow structure 130 and the second hollow structure 140 in the direction perpendicular to the transparent substrate 100 is more than 80% of the total area of the first overlapping region S1 and the second overlapping region S2.

In this embodiment, as shown in FIG. 12, the first hollow pattern 131 is two arc-shaped structures 1311 and 1312 arranged concentrically with the source electrode 121, and the second hollow pattern 132 is a "U"-shaped structure; as shown in FIG. 13 As shown, the third hollow pattern 141 is an arc-shaped structure arranged concentrically with the source 121 , and the fourth hollow pattern 142 is an elongated structure extending in the same direction as the length of the end of the drain 122 near the drain 122 . As shown in FIG. 10 , the first hollow pattern 131 and the third hollow pattern 141 will occupy most of the first overlapping area S1 after overlapping in a direction perpendicular to the transparent substrate 100 . The overlapping of the second hollow pattern 132 and the fourth hollow pattern 142 will occupy most of the second overlapping area S2.

At the same time, the first hollow structure 130 is set on the gate 110 and the second hollow structure 140 is set on the source-drain metal layer 120, which greatly reduces the distance between the gate 110 and the source 121, and between the gate 110 and the drain 122. The facing area further reduces the overlapping capacitance (parasitic capacitance) between the gate 110 and the source 121, and between the gate 110 and the drain 122. When the thin film transistor is turned on to charge the pixel electrode, it effectively reduces the coupling to enables the feedthrough voltage on the pixel electrode.

The following table compares the characteristics of the thin film transistor of this embodiment and the thin film transistor of the prior art under the premise that the width and length of the channel are constant values. It can be seen from the table that the gate 110 of the thin film transistor of this embodiment Compared with the overlapping capacitance between the drains 122, the existing technology has a relatively large reduction (49.8%), and the minimum value and the maximum value of the feedthrough voltage of the thin film transistor of the present embodiment are compared with the prior art. Both have a relatively large decrease (51% and 50% decrease).

The present invention also relates to an array substrate, the array substrate includes a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines are intersected to define a plurality of pixel units, and each pixel unit includes a pixel electrode Each pixel unit further includes the above thin film transistor, the gate 110 of the thin film transistor is connected to the corresponding scanning line, and the drain 122 of the thin film transistor is connected to the pixel electrode in the pixel unit.

The present invention also relates to a display device, which includes the above-mentioned array substrate. The display device is, for example, a liquid crystal display device, including a color filter substrate opposite to the array substrate and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. Other structures of the display device are known to those skilled in the art. It is well known and will not be repeated here.

The above descriptions are only preferred embodiments of the thin film transistor, array substrate and display device of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to To limit the present invention, any skilled person familiar with the profession, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or be modified into equivalent embodiments with equivalent changes, provided that they do not depart from the present invention The content of the technical solution of the invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still belong to the scope of the technical solution of the present invention.

Claims (10)

1. A thin film transistor, comprising a gate (110), a source-drain metal layer (120) and a semiconductor layer (300); the gate (110) is arranged on a transparent substrate (100); the transparent substrate ( 100) is also provided with a gate insulating layer (101) covering the gate (110); the semiconductor layer (300) is arranged on the gate insulating layer (101) and is located on the gate (110) above; the source-drain metal layer (120) is disposed on the semiconductor layer (300), including a source (121) and a drain (122), and the source (121) and the drain ( 122) are separated from each other and are in contact with the semiconductor layer (300), the semiconductor layer (300) is provided with a channel (301), and the channel (301) is arranged on the source (121) and the drain Between electrodes (122), it is characterized in that the gate (110) and the source-drain metal layer (120) have overlapping regions in a direction perpendicular to the transparent substrate (100), and the gate At least one of (110) and the source-drain metal layer (120) is provided with a hollow structure for reducing the facing area between the gate (110) and the source-drain metal layer (120). 2. The thin film transistor according to Claim 1, characterized in that, the hollow structure is a first hollow structure (130) provided on the gate (110). 3. The thin film transistor according to claim 2, characterized in that, the gate (110) and the source (121) have a first overlapping region ( S1), the gate (110) and the drain (122) have a second overlapping region (S2) in a direction perpendicular to the transparent substrate (100); the first hollow structure (130) includes a The first hollow pattern (131) in the first overlapping area (S1) and the second hollow pattern (132) arranged in the second overlapping area (S2). 4. The thin film transistor according to claim 1, characterized in that, the hollow structure is a second hollow structure (140) disposed on the source (121) and the drain (122). 5. The thin film transistor according to claim 4, characterized in that the source (121) and the gate (110) have a first overlapping region (S1) in a direction perpendicular to the transparent substrate (100) , the drain (122) and the gate (110) have a second overlapping region (S2) in a direction perpendicular to the transparent substrate (100); the second hollow structure (140) includes The third hollow pattern (141) in the first overlapping area (S1) and the fourth hollow pattern (142) arranged in the second overlapping area (S2). 6. The thin film transistor according to claim 1, characterized in that, the hollow structure is a first hollow structure (130) arranged on the gate (110) and a first hollow structure (130) arranged on the source (121), A second hollow structure (140) on the drain (122). 7. The thin film transistor according to claim 6, characterized in that, the gate (110) and the source (121) have a first overlapping region (S1) in a direction perpendicular to the transparent substrate (100) , the gate (110) and drain (122) have a second overlapping region (S2) in a direction perpendicular to the transparent substrate (100); the first hollow structure (130) includes The first hollow pattern (131) in the first overlapping area (S1) and the second hollow pattern (132) arranged in the second overlapping area (S2); the second hollow structure (140) includes The third hollow pattern (141) arranged in the first overlapping region (S1) and the fourth hollow pattern (142) arranged in the second overlapping region (S2). 8. The thin film transistor according to claim 7, characterized in that, the overlapping area of the first hollow structure (130) and the second hollow structure (140) in a direction perpendicular to the transparent substrate (100) is greater than 80% of the total area of the first overlapping region (S1) and the second overlapping region (S2). 9. An array substrate, the array substrate includes a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines intersect each other to define a plurality of pixel units, each pixel unit includes a pixel electrode, characterized in that each pixel unit further includes the thin film transistor according to any one of claims 1 to 8, the gate (110) of the thin film transistor is connected to the corresponding scanning line, and the thin film transistor The drain (122) of is connected to the pixel electrode. 10. A display device, comprising the array substrate according to claim 9.