CN108597558B - System and method for optimizing phase change memory write operation current - Google Patents

Abstract

The present invention provides a system and method for optimizing the write operation current of a phase change memory. The method includes: adjusting the write operation current based on the change step size of the write operation current, so that the write operation current is sequentially increased from the minimum write operation current to the maximum write operation current ; After each acquisition of the write operation current, perform a write operation on the unit to be operated and conduct an electrical test on it, and obtain the resistance data and V-I characteristic curve corresponding to the write operation current; before each write operation, it is also based on the same preset erasing parameters. Erase the unit to be operated; carry out statistical analysis on the resistance data corresponding to different write operation currents, and screen out the true write operation current that enables the unit to be operated to successfully perform the write operation; Fitting to obtain a number of sub-threshold slopes; and performing statistical analysis on the obtained sub-threshold slopes to obtain an optimal write operation current. The present invention solves the problem that the existing method cannot screen out the optimal write operation current.

Description

System and method for optimizing phase change memory write operation current

technical field

The present invention relates to the field of integrated circuit testing, in particular to a system and method for optimizing the write operation current of a phase change memory.

Background technique

Phase change memory is a new type of non-volatile memory, which has the characteristics of fast read and write speed, compatible with CMOS technology and high density. The core of the phase change memory is a phase change material based on chalcogenide compounds. The phase change material exhibits different resistance values in the amorphous state and the crystalline state, and there is a large resistance difference. The resistance value difference of the unit device can be to the order of 2-3. The basic working principle of the phase change memory is to apply different pulses at both ends of the phase change device unit, so that the phase change material is converted between the amorphous state and the crystalline state to realize the write and erase operations, and at the same time, the resistance value is measured by the principle of Ohm's law. Implement read operations.

The phase change memory is a current-operated device. For the phase change memory: the switching of the unit data '0' and '1' and the readout of the unit data depend on the corresponding operating current. The write operation (RESET) of the phase change memory, that is, the write '0' operation, is to operate the phase change unit to a high resistance state (RESET state). The write operation is to apply a write current to the phase change material, convert the electrical energy into heat energy by heating the electrode, and raise the temperature of the phase change material to above the melting temperature. The order is destroyed, and the phase change material is transformed from a crystalline state to an amorphous state. The write operation makes the phase change unit finally in the high resistance region, realizing the storage of '0'. The erase operation (SET), that is, the write '1' operation, is to operate the phase change unit to a low resistance state (SET state). The wiping operation is to apply an electric pulse with a suitable amplitude and a long duration to the phase change material, so that the temperature of the phase change material is increased to between the crystallization temperature and the melting temperature and the electric pulse width is maintained longer than the crystallization induction time to ensure the phase change. The material crystallizes sufficiently in sufficient time. It can be seen that the operating current is an important parameter of the phase change memory, which has a very important influence on the overall performance of the chip. The write operation current is a relatively large current. Selecting an appropriate value of the write operation current can not only realize the write operation of the chip, ensure the yield rate of the chip, but also avoid unnecessary current consumption and reduce the power consumption of the chip.

The traditional method for determining the write operation current is from a macroscopic point of view, and is determined according to the resistance value of the cell after the write operation. The specific method is: first select a RESET current, after the write operation, test the resistance distribution of the chip, and finally determine the value of the write operation current; when the resistance distribution is consistent, the phase change resistance is in the high resistance area, and the resistance distribution does not appear tail area, it can be considered that the current can perform a write operation. It can be seen that the traditional method can only be distinguished from the resistance distribution, but the accuracy of the resistance distribution is low; and for the situation where the resistance distribution is the same and the RESET current is different, the traditional method is difficult to apply, and the optimal write operation current cannot be obtained, which leads to the traditional method. The screened write operation current will over-operate the phase change unit, which reduces the fatigue reliability and data retention of the phase change memory, so that in some environments that require accurate control of power consumption and chip operating parameters, traditional methods cannot be used. Meet the requirements.

In view of this, it is necessary to design a new system and method for optimizing the write operation current of a phase change memory to solve the above technical problems.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a system and method for optimizing the write operation current of a phase change memory, so as to solve the problem that the existing method has insufficient precision and cannot screen out the optimal write operation current, thereby As a result, the phase change memory has problems such as over-operation and high power consumption.

In order to achieve the above object and other related objects, the present invention provides a method for optimizing the write operation current of a phase change memory, the method comprising:

Setting the minimum write operation current, the maximum write operation current and the change step size of the write operation current of the phase change memory, and selecting a number of units to be operated from the phase change memory;

The write operation current is adjusted based on the change step size of the write operation current, so that the write operation current is sequentially increased from the minimum write operation current to the maximum write operation current; after each acquisition of the write operation current , perform a write operation on the to-be-operated unit based on the write operation current, and after the write operation ends, perform an electrical test on the to-be-operated unit to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; Wherein, each time before the write operation is performed on the unit to be operated, the method further includes performing an erase operation on the unit to be operated based on the same preset erase parameter;

Statistical analysis is performed on the resistance data corresponding to different write operation currents, and the real write operation current that enables the to-be-operated unit to successfully perform the write operation is screened out; and the V-I characteristic curve corresponding to the real write operation current is fitted, obtaining the sub-threshold slope corresponding to the true write operation current; and

Statistical analysis is performed on the acquired sub-threshold slope to acquire the optimal write operation current of the phase change memory.

Optionally, the minimum write operation current and the maximum write operation current are set according to the minimum initial write operation current and the maximum initial write operation current of the phase change memory, wherein the minimum write operation current is smaller than the minimum initial write operation current. current, the maximum write operation current is greater than the maximum initial write operation current.

Optionally, the method for acquiring a V-I characteristic curve includes: setting a scan voltage, and performing a V-I scan test on the to-be-operated unit based on the scan voltage to acquire a V-I characteristic curve; wherein the scan voltage is less than the phase The threshold voltage at which the phase transition of the memory is changed.

Optionally, the method for screening the real write operation current includes: performing statistics on resistance data corresponding to different write operation currents, and screening each resistance data based on a reference resistance, so as to classify resistance data larger than the reference resistance. The corresponding write operation current is used as the true write operation current.

Optionally, the method for obtaining the sub-threshold slope includes: performing a log operation on the current value in the V-I characteristic curve to obtain the sub-threshold slope corresponding to the true write operation current.

Optionally, the method for obtaining the optimal write operation current of the phase change memory includes: performing a statistical analysis on the sub-threshold slope, and filtering out the corresponding true write operation current when the change of the sub-threshold slope tends to be saturated, as The optimal write operation current of the phase change memory.

The present invention also provides a system for optimizing the write operation current of the phase change memory, the system includes: a main control module, a parameter setting module, a switching module, a signal acquisition module, a parameter measurement module and a data processing module, the main control module It is connected with the parameter setting module, the switching module and the data processing module, the parameter setting module is connected with the switching module, and the switching module is connected with the signal acquisition module and the parameter measurement module, so the The parameter measurement module is connected with the main control module; wherein,

The main control module is used to control the switching module, so as to realize the connection between the signal acquisition module and the parameter setting module or the connection between the signal acquisition module and the parameter measurement module; When the parameter setting module is connected, it is used to control the parameter setting module to generate an address signal, an erase operation current and a write operation current in sequence, wherein the write operation current generated each time takes the change step size of the write operation current as the change amount The minimum write operation current is sequentially increased to the maximum write operation current; when the signal acquisition module is connected to the parameter measurement module, it is used to transmit the resistance data and the V-I characteristic curve obtained by the parameter measurement module to the data processing module;

The parameter setting module is used to sequentially generate an address signal, an erase operation current and a write operation current under the control of the main control module and transmit them to the signal acquisition module, wherein the write operation current output each time is equal to The change step size of the write operation current is that the change amount is sequentially increased from the minimum write operation current to the maximum write operation current;

The switching module is used to realize the connection between the signal acquisition module and the parameter setting module or the connection between the signal acquisition module and the parameter measurement module under the control of the main control module;

The signal acquisition module is used to select a number of units to be operated from the phase change memory according to the address signal, the erase operation current and the write operation current sequentially output by the parameter setting module, and to perform the erase operation on the units to be operated in turn. and write operations;

The parameter measurement module performs an electrical test on the phase change memory through the signal acquisition module, obtains resistance data and V-I characteristic curves corresponding to each of the write operation currents, and passes the resistance data and V-I characteristic curves through the main control module. to the data processing module; and

The data processing module is used to perform statistical analysis on the resistance data corresponding to each of the write operation currents, and to screen out the real write operation current that enables the to-be-operated unit to successfully perform the write operation; The V-I characteristic curve is fitted to obtain the sub-threshold slope corresponding to each of the true write operation currents; and statistical analysis is performed on the obtained sub-threshold slope to obtain the optimal write operation current of the phase change memory.

Optionally, the parameter setting module includes an address selection unit and a pulse signal generation unit respectively connected between the main control module and the switching module; wherein,

The address selection unit is configured to output an address signal to the signal acquisition module under the control of the main control module; and

The pulse signal generating unit is used for sequentially outputting the erase operation current and the write operation current to the signal acquisition module under the control of the main control module, wherein the write operation current output each time is the same as the write operation current. The current change step size is the change amount, which is sequentially increased from the minimum write operation current to the maximum write operation current.

As described above, the system and method of the present invention for the preferred phase change memory write operation current have the following beneficial effects:

The system and method of the present invention can realize the optimization of the write operation current of the phase change memory, greatly increase the accuracy of the write operation current screening; reduce the unnecessary power consumption of the RESET operation, and at the same time ensure the effect of the write operation; The influence of over-operation on the fatigue reliability of the phase change memory can be avoided, the high temperature durability and read durability of the phase change memory are ensured, and the service life of the phase change memory is prolonged.

From a microscopic point of view, the method of the invention has the advantages of simple operation, high screening accuracy, low test cost, no damage to the chip, etc., and can be used to accurately determine the most suitable write operation current parameters for mass-produced chips and improve the performance of the chip.

Description of drawings

Figure 1 shows a schematic flow chart of the method of the present invention.

FIG. 2 is a block diagram showing the structure of the system according to the present invention.

FIG. 3 is a graph showing the sub-threshold slope distribution corresponding to different real write operation currents when the phase change memory is optimized by the method of the present invention.

FIG. 4 is a diagram showing the distribution of resistance data corresponding to different real write operation currents when the phase change memory is optimized for the write operation current by the method of the present invention.

Component label description

100 main control module

200 Parameter setting module

201 Address selection unit

202 Pulse signal generation unit

300 Switching Modules

400 signal acquisition module

500 Parameter Measurement Module

600 Data Processing Module

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 4. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

As shown in FIG. 1 , this embodiment provides a method for optimizing the write operation current of a phase change memory, and the method includes:

Step 1: Set the minimum write operation current, the maximum write operation current and the change step size of the write operation current of the phase change memory, and select a number of units to be operated from the phase change memory;

Step 2: Adjust the write operation current based on the change step size of the write operation current, so that the write operation current is sequentially increased from the minimum write operation current to the maximum write operation current; After operating the current, perform a write operation on the to-be-operated unit based on the write operation current, and after the write operation ends, perform an electrical test on the to-be-operated unit to obtain resistance data and V-I corresponding to the write operation current Characteristic curve; wherein, before each write operation is performed on the unit to be operated, it also includes performing an erase operation on the unit to be operated based on the same preset erase parameter;

Step 3: Statistical analysis is performed on the resistance data corresponding to different write operation currents, and the real write operation current that enables the to-be-operated unit to successfully perform the write operation is screened out; and the V-I characteristic curve corresponding to the real write operation current is carried out. Fitting to obtain the sub-threshold slope corresponding to the true write operation current; and

Step 4: Statistical analysis is performed on the acquired sub-threshold slope to acquire the optimal write operation current of the phase change memory.

As an example, in step 1, the minimum writing current I _min and the maximum writing current I _max are set according to the minimum initial writing current I _inimin and the maximum initial writing current I _inimax of the phase change memory, wherein the The minimum writing current I _min is smaller than the minimum initial writing current I _inimin , and the maximum writing current I _max is greater than the maximum initial writing current I _inimax . It should be noted that the minimum initial write operation current I _inimin and the maximum initial write operation current I _{inimax mentioned here} refer to the minimum factory write operation current and the maximum factory write operation current specified when the phase change memory leaves the factory; the minimum write operation current The settings of the current I _min and the maximum write operation current I _max must ensure that the phase change memory can work normally within a given current range.

As an example, in step 1, the write operation current change step size I _setp is related to the optimization accuracy of the write operation current, wherein, the smaller the write operation current change step size I _{setp is} , the smaller the write operation current change step size I setp is. The higher the optimization precision is, the larger the write operation current change step size _Isetp is, and the lower the optimization precision of the write operation current is; therefore, in this embodiment, in order to ensure the optimization precision of the write operation current, the write operation current is The setting of the operating current change step size I _setp should be as small as possible.

As an example, in step 2, the method for acquiring the V-I characteristic curve includes: setting a scan voltage, and performing a V-I scan test on the to-be-operated unit based on the scan voltage to acquire the V-I characteristic curve; wherein the scan voltage is less than the threshold voltage at which the phase change memory undergoes a phase change.

As an example, in step 2, before each write operation to the to-be-operated unit, the method further includes performing an erase operation on the to-be-operated unit based on the same preset erasing parameters, so that the to-be-operated unit is written to each time The state of the phase change material is the same before operation to ensure the accuracy of subsequent measurements. It should be noted that the preset erasing parameters include the width of the erasing operation current pulse and the height of the erasing operation current pulse, that is, the erasing operation current can be determined by determining the preset erasing parameters.

As an example, in step 3, the method for screening the true write operation current includes: performing statistics on resistance data corresponding to different write operation currents, and screening each resistance data based on the reference resistance, so that the resistance data is larger than the reference resistance. The write operation current corresponding to the resistance data of the resistor is used as the real write operation current. It should be noted that the reference resistance is the resistance when the phase change memory is in a high resistance state, usually 10 ⁶ or more.

As an example, in step 3, the method for obtaining the sub-threshold slope includes: performing a log operation on the current value in the V-I characteristic curve, and using the obtained V-log(I) characteristic curve as the true write operation The current corresponding to the subthreshold slope.

As an example, in step 4, the method for obtaining the optimal write operation current of the phase change memory includes: performing statistical analysis on the sub-threshold slope, and filtering out the real write operation corresponding to the sub-threshold slope change that tends to be saturated current as the optimal write operation current of the phase change memory.

It should be noted that, from the perspective of the microstructure of the phase change memory cell, the method described in this embodiment utilizes the relationship between the carrier transport mechanism and the macroscopic electrical properties to characterize the microscopic phenomenon of the phase change material under the writing operation, thereby The optimal write operation current of the phase change memory is screened out. The specific principle is: under the action of different amplitudes of write operation currents, the internal defect densities of the amorphous materials of the phase-change memory cells are different, so the currents generated by the electron transitions under the action of a certain electric field are also different, resulting in macroscopic voltage currents ( V-I) characteristics are different; and by measuring the V-I characteristic curve of the phase change memory cell in the amorphous state after the write operation, fitting the V-I characteristic curve, and performing statistical analysis on the obtained subthreshold slope STS, the phase change can be obtained. Optimal write current for the memory.

As shown in FIG. 2 , this embodiment also provides a system for optimizing the write operation current of a phase change memory, the system includes: a main control module 100 , a parameter setting module 200 , a switching module 300 , a signal acquisition module 400 , and a parameter measurement module Module 500 and data processing module 600, the main control module 100 is connected with the parameter setting module 200, the switching module 300 and the data processing module 600, the parameter setting module 200 is connected with the switching module 300, The switching module 300 is connected to the signal acquisition module 400 and the parameter measurement module 500, and the parameter measurement module 500 is connected to the main control module 100; wherein,

The main control module 100 is used to control the switching module 300, so as to realize the connection between the signal acquisition module 400 and the parameter setting module 200 or the connection between the signal acquisition module 400 and the parameter measurement module 500; When the signal acquisition module 400 is connected to the parameter setting module 200, it is used to control the parameter setting module 200 to sequentially generate an address signal, an erase operation current and a write operation current, wherein the write operation current generated each time is equal to the The change step size of the write operation current is that the change amount is sequentially increased from the minimum write operation current to the maximum write operation current; when the signal acquisition module 400 is connected to the parameter measurement module 500, it is used to measure the parameter The resistance data and V-I characteristic curve acquired by the measurement module 500 are transmitted to the data processing module 600;

The parameter setting module 200 is used to sequentially generate an address signal, an erase operation current and a write operation current under the control of the main control module 100 and transmit them to the signal acquisition module 400. The operation current is sequentially increased from the minimum write operation current to the maximum write operation current by taking the change step of the write operation current as the change amount;

The switching module 300 is configured to realize the connection between the signal acquisition module 400 and the parameter setting module 200 or the connection between the signal acquisition module 400 and the parameter measurement module 500 under the control of the main control module 100;

The signal acquisition module 400 is used to select a number of units to be operated from the phase change memory according to the address signal, the erase operation current and the write operation current sequentially output by the parameter setting module 200, and perform the operation on the units to be operated in sequence. Erase and write operations;

The parameter measurement module 500 conducts an electrical test on the phase change memory through the signal acquisition module 400, obtains resistance data and V-I characteristic curves corresponding to each of the write operation currents, and passes the resistance data and V-I characteristic curves through the main The control module 100 is transmitted to the data processing module 600; and

The data processing module 600 is configured to perform statistical analysis on the resistance data corresponding to each of the write operation currents, and to screen out the real write operation current that enables the unit to be operated to successfully perform the write operation; The corresponding V-I characteristic curve is fitted to obtain the sub-threshold slope corresponding to each of the true write operation currents; and the obtained sub-threshold slope is statistically analyzed to obtain the optimal write operation current of the phase change memory.

As an example, the main control module 100 includes a computer; the signal acquisition module 400 includes a high-precision micro-control probe station, which enables the phase change memory placed on the probe station to communicate with the entire test system through the probe .

As an example, as shown in FIG. 2 , the parameter setting module 200 includes an address selection unit 201 and a pulse signal generating unit 202 respectively connected between the main control module 100 and the switching module 300; wherein,

The address selection unit 201 is configured to output an address signal to the signal acquisition module 400 under the control of the main control module 100; and

The pulse signal generating unit 202 is used for sequentially outputting the erase operation current and the write operation current to the signal acquisition module 400 under the control of the main control module 100, wherein the write operation current outputted each time is in the order of the specified value. The change step size of the write operation current is that the change amount increases sequentially from the minimum write operation current to the maximum write operation current.

Referring to FIG. 1 to FIG. 4 below, the method for optimizing the writing operation current of the phase change memory according to the present embodiment will be described in detail in conjunction with the system for optimizing the writing operation current of the phase change memory according to the present embodiment.

Before the test, the phase change memory to be tested (4M phase change memory) needs to be placed on the probe station, and the phase change memory to be tested is realized by electrically connecting the probe with the corresponding PAD of the phase change memory to be tested. For the communication with the entire test system, the corresponding test is performed after the hardware connection is completed, as follows:

1) According to the factory parameters of the phase change memory to be tested, set the minimum write operation current I _min , the maximum write operation current I _max and the write operation current change step size I _step of the phase change memory to be tested.

2) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter setting module 200, and the address selection unit 201 is controlled by the main control module 100 to generate an address The signal is output to the signal acquisition module 400 to select a number of units to be operated from the phase change memory to be measured.

3) The pulse signal generating unit 202 is controlled by the main control module 100 to generate a wiping operation current, so as to perform wiping operation on the to-be-operated unit, so that the to-be-operated unit becomes a crystalline state (low resistance state).

4) The main control module 100 controls the pulse signal generating unit 202 to generate a write operation current to perform a write operation on the to-be-operated unit; at this time, the write operation current is the minimum write operation current I _min .

5) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter measurement module 500, and the to-be-operated unit is electrically tested by the parameter measurement module 500 to sequentially Obtain the resistance data and VI characteristic curve corresponding to the minimum write operation current _Imin ; and transmit the resistance data and VI characteristic curve corresponding to the minimum write operation current _Imin to the data processing module 600 through the main control module 100 .

6) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter setting module 200, and the pulse signal generating unit 202 is controlled by the main control module 100 to generate a The erasing operation current is used to perform the erasing operation on the to-be-operated unit, so that the to-be-operated unit becomes a crystalline state (low resistance state).

7) Controlling the pulse signal generating unit 202 by the main control module 100 to generate a write operation current to perform a write operation on the to-be-operated unit, wherein the write operation current is an increase of a write operation on the original basis Current change step size I _step ;

8) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter measurement module 500, and the to-be-operated unit is electrically tested by the parameter measurement module 500 to sequentially Obtain the resistance data and V-I characteristic curve corresponding to the write operation current; and transmit the resistance data and V-I characteristic curve corresponding to the write operation current to the data processing module 600 through the main control module 100;

9) Repeat 6) to 8) until the resistance data and VI characteristic curve corresponding to the maximum write operation current _Imax are transmitted to the data processing module 600;

10) The data processing module 600 performs statistical analysis on the resistance data corresponding to each of the write operation currents, and selects the true write operation current that enables the unit to be operated to successfully perform the write operation from each write operation current; Fitting the V-I characteristic curve corresponding to the real write operation current to obtain the sub-threshold slope corresponding to each of the real write operation currents; and then performing statistical analysis on the obtained sub-threshold slope to obtain the optimal value of the phase change memory. write operation current.

It can be seen that the sub-threshold slope obtained by the above method is shown in Figure 3. It can be seen from Figure 3 that as the real write operation current increases, the sub-threshold slope STS becomes larger and larger, and the distribution tends to be more saturated; When the sub-threshold slope STS tends to be saturated, the corresponding real write operation current is about 0.81mA. Therefore, the real write operation current of 0.81mA is used as the optimal write operation current of the phase change memory to be tested, which not only guarantees The write operation effect of the phase change memory to be tested reduces unnecessary power consumption. Figure 4 shows the resistance data distribution corresponding to the real writing operation current. It can be seen from Figure 4 that in the process of changing the real writing operation current from 0.58mA to 0.77mA, the resistance distribution of the to-be-operated unit is completely indistinguishable. On the other hand, the sub-threshold slope STS shown in FIG. 3 can be completely distinguished, and there is a law that increases with the increase of the real write operation current. Therefore, as can be seen from FIG. 3 and FIG. 4 , in the case where the traditional method is not applicable, the method described in this embodiment can still realize the screening of the write operation current.

To sum up, the system and method for optimizing the write operation current of the phase change memory of the present invention have the following beneficial effects:

The system and method of the present invention can realize the optimization of the write operation current of the phase change memory, greatly increase the accuracy of the write operation current screening; reduce the unnecessary power consumption of the RESET operation, and at the same time ensure the effect of the write operation; The influence of over-operation on the fatigue reliability of the phase change memory can be avoided, the high temperature durability and read durability of the phase change memory are ensured, and the service life of the phase change memory is prolonged.

From a microscopic point of view, the method of the invention has the advantages of simple operation, high screening accuracy, low test cost, no damage to the chip, etc., and can be used to accurately determine the most suitable write operation current parameters for mass-produced chips and improve the performance of the chip.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (8)

1. A method for obtaining an optimal write operation current of a phase change memory, the method comprising:

setting the minimum write operation current, the maximum write operation current and the write operation current change step length of the phase change memory, and selecting a plurality of units to be operated from the phase change memory;

adjusting the write operation current based on the write operation current change step length to enable the write operation current to be sequentially increased from the minimum write operation current to the maximum write operation current; after the write operation current is obtained each time, performing write operation on the unit to be operated based on the write operation current, and after the write operation is finished, performing electrical test on the unit to be operated to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; before writing operation is carried out on the unit to be operated each time, erasing operation is carried out on the unit to be operated based on the same preset erasing parameters;

carrying out statistical analysis on resistance data corresponding to different write operation currents, and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to the true write operation current to obtain a sub-threshold slope corresponding to the true write operation current; and

and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.

2. The method of claim 1, wherein the minimum write current and the maximum write current are set according to a minimum initial write current and a maximum initial write current of the phase change memory, wherein the minimum write current is smaller than the minimum initial write current, and the maximum write current is larger than the maximum initial write current.

3. The method for obtaining the optimal write operation current of the phase change memory as claimed in claim 1, wherein the method for obtaining the V-I characteristic curve comprises: setting a scanning voltage, and carrying out V-I scanning test on the unit to be operated based on the scanning voltage to obtain a V-I characteristic curve; wherein the scan voltage is less than a threshold voltage of the phase change memory for phase change.

4. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for screening the true write operation current comprises: and counting resistance data corresponding to different write operation currents, and screening each resistance data based on a reference resistance to take the write operation current corresponding to the resistance data larger than the reference resistance as the true write operation current.

5. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for obtaining the subthreshold slope comprises: and carrying out log taking on the current value in the V-I characteristic curve so as to obtain a subthreshold slope corresponding to the true write operation current.

6. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for obtaining the optimal write operation current of the phase change memory comprises: and carrying out statistical analysis on the sub-threshold slope, and screening out the true write operation current corresponding to the sub-threshold slope when the change of the sub-threshold slope is close to saturation so as to be used as the optimal write operation current of the phase change memory.

7. A system for obtaining an optimal write operation current for a phase change memory, the system comprising: the device comprises a main control module, a parameter setting module, a switching module, a signal acquisition module, a parameter measurement module and a data processing module, wherein the main control module is connected with the parameter setting module, the switching module and the data processing module; wherein,

the main control module is used for controlling the switching module so as to realize that the signal acquisition module is connected with the parameter setting module or the signal acquisition module is connected with the parameter measurement module; when the signal acquisition module is connected with the parameter setting module, the signal acquisition module is used for controlling the parameter setting module to sequentially generate an address signal, an erasing operation current and a writing operation current, wherein the writing operation current generated each time is sequentially increased from a minimum writing operation current to a maximum writing operation current by taking a writing operation current change step as a variable quantity; when the signal acquisition module is connected with the parameter measurement module, the signal acquisition module is used for transmitting the resistance data and the V-I characteristic curve acquired by the parameter measurement module to the data processing module;

the parameter setting module is used for sequentially generating an address signal, an erasing operation current and a writing operation current under the control of the main control module and transmitting the address signal, the erasing operation current and the writing operation current to the signal acquisition module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity;

the switching module is used for realizing the connection between the signal acquisition module and the parameter setting module or between the signal acquisition module and the parameter measurement module under the control of the main control module;

the signal acquisition module is used for selecting a plurality of units to be operated from the phase change memory according to the address signal, the erasing operation current and the writing operation current which are sequentially output by the parameter setting module, and sequentially performing erasing operation and writing operation on the units to be operated;

the parameter measuring module performs electrical test on the phase change memory through the signal acquisition module, acquires resistance data and a V-I characteristic curve corresponding to each write operation current, and transmits the resistance data and the V-I characteristic curve to the data processing module through the main control module; and

the data processing module is used for carrying out statistical analysis on resistance data corresponding to each write operation current and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to each true write operation current to obtain a sub-threshold slope corresponding to each true write operation current; and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.

8. The system for obtaining the optimal write operation current of the phase change memory according to claim 7, wherein the parameter setting module comprises an address selection unit and a pulse signal generation unit respectively connected between the main control module and the switching module; wherein,

the address selection unit is used for outputting an address signal to the signal acquisition module under the control of the main control module; and

the pulse signal generating unit is used for sequentially outputting erasing operation current and writing operation current to the signal acquisition module under the control of the main control module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity.

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