CN108595748B - Three-dimensional topological structure of antifuse Field Programmable Gate Array (FPGA) - Google Patents

Abstract

The invention designs a novel three-dimensional topology structure which can be applied to the anti-fuse FPGA programmable logic array. Compared with the programmable logic array of the conventional two-dimensional anti-fuse FPGA, the structure has the advantages of large capacity and high performance. The invention first uses two programmable logic modules to complete the construction from programmable logic row to programmable logic layer, and then to programmable logic array, and constructs a three-dimensional programmable logic module arrangement structure. A variety of wiring channels are designed for this structure, and different wiring methods are set for the wiring channels. At the same time, different interconnection strategies are used between adjacent and distant programmable logic modules, thus completing the interconnection of programmable logic arrays. . The finally obtained three-dimensional topology structure has the characteristics of spatial three-dimensionality, abundant wiring resources, flexible wiring methods, convenient interconnection between programmable logic modules, and the overall structure can be expanded in all directions. Antifuse FPGA.

Description

A Three-Dimensional Topology of Antifuse FPGA Programmable Logic Array

technical field

The invention belongs to the field of integrated circuits, and designs a novel three-dimensional topology structure which can be applied to an anti-fuse FPGA programmable logic array.

Background technique

As a typical programmable logic device, FPGA is mainly divided into anti-fuse type FPGA, SRAM type FPGA, EEPROM/FLASH type FPGA and so on. Among them, anti-fuse FPGA is a programmable FPGA using anti-fuse technology, which has the advantages of non-volatility, one-time programmability, radiation resistance and high reliability. The programmable logic modules of a typical anti-fuse FPGA are usually divided into programmable combinational logic modules (hereinafter referred to as PCM) and programmable sequential logic modules (hereinafter referred to as PSM).

The programmable logic array of traditional FPGA is distributed in a two-dimensional plane structure. As the scale of FPGA becomes larger and larger, the area of FPGA chip with standard two-dimensional structure is also increasing. Too large area often leads to low chip yield and performance degradation. , even beyond the size of the package package to achieve packaging. The contradiction between the capacity, performance and chip area of FPGA is becoming more and more obvious. For antifuse FPGAs, this contradiction is even more pronounced. The extension of the programmable logic array of the large-capacity FPGA with two-dimensional structure on the plane leads to longer and longer wiring paths. Because the anti-fuse unit itself has obvious parasitic resistance and parasitic capacitance, the performance of the anti-fuse FPGA is negatively affected. The degree of impact is more pronounced than the degree to which the performance of other types of FPGAs without significant parasitics is negatively affected. In addition, the anti-fuse requires high-voltage programming. The high-voltage resistance determines that the size of the anti-fuse unit itself and the high-voltage devices in the programming circuit should not be too small, and the degree of scaling down with process improvement is limited. In a two-dimensional plane with a limited area, anti-fuse FPGAs are more limited in capacity expansion than other types of FPGAs represented by SRAM structures. Therefore, in order to realize large-capacity, high-performance anti-fuse FPGA, it is particularly important to innovate in architecture.

With the rapid development of electronic information technology, the complexity of the system is getting higher and higher, the scale of the circuit is getting bigger and bigger, and the performance requirements of the system are getting higher and higher. The three-dimensional packaging technology represented by multi-chip packaging and integration is becoming more widespread and mature, and the on-chip high-density three-dimensional circuit integration technology using a single chip as a carrier has also attracted much attention and achieved good development.

Based on the three-dimensional integration technology, the architectural innovation of anti-fuse FPGA and the construction of three-dimensional anti-fuse FPGA is an effective solution to solve the bottleneck problem of large-capacity and high-performance anti-fuse FPGA design. First, by extending the anti-fuse FPGA from two-dimensional to three-dimensional, it can develop vertically within a limited area, thereby breaking the capacity limitation and increasing the scale of the anti-fuse FPGA design; secondly, the programmable logic of the three-dimensional anti-fuse FPGA The modules are more compact, the wiring resources in the three-dimensional space are more abundant, the interconnection between logic modules is more convenient and flexible, and the wiring length of the interconnection lines in practical applications is shortened in disguise due to the three-dimensional distribution. Therefore, compared with the traditional two-dimensional structure FPGA, its speed performance is improved. can be significantly improved.

The existing three-dimensional integration technologies of integrated circuits are mainly divided into two types: multi-chip inter-chip three-dimensional packaging integration and single-chip intra-chip three-dimensional circuit integration. If the 3D anti-fuse FPGA adopts multi-chip 3D package integration, the chips are connected based on chip pins, and the programmable logic modules located in different chips need to be connected through I/O circuits and chip pin bridges. , and the bridging interconnection will bring additional parasitic effects, so although this technology can effectively increase the size of the FPGA, it cannot significantly improve the performance of the FPGA. If the 3D anti-fuse FPGA is integrated with three-dimensional circuits on a single chip, the programmable logic modules can be directly interconnected on-chip without inter-chip bridges, thus increasing the scale of the FPGA and effectively ensuring the full improvement of the FPGA performance. The three-dimensional package integration between multi-chips only focuses on simple capacity expansion, while the three-dimensional circuit integration within a single chip involves essential architectural innovation, taking into account capacity expansion and performance improvement.

In the context of the above analysis, the present invention proposes a novel three-dimensional topology structure that can be applied to an anti-fuse FPGA programmable logic array. The structure has abundant wiring resources and flexible wiring methods. In addition, because this structure adopts three-dimensional integration at the circuit level, rather than three-dimensional integration at the packaging level, it has a more significant effect on the scale and performance of anti-fuse FPGAs. The present invention can be applied to design a large-capacity, high-performance anti-fuse FPGA.

SUMMARY OF THE INVENTION

The invention designs a novel three-dimensional topology structure applied to the anti-fuse FPGA programmable logic array. Compared with the conventional two-dimensional FPGA, the three-dimensional anti-fuse FPGA has the advantages of large capacity and high performance.

The technical scheme of the present invention is to use a plurality of PCMs and PSMs to construct a three-dimensional arrangement structure, design a variety of wiring channels for the structure, and use different interconnection schemes between adjacent programmable logic modules and programmable logic modules with a long distance. The modules are interconnected to obtain the final topology. The structure proposed by the invention ensures abundant wiring resources and various wiring modes among programmable logic modules, greatly improves the speed of the anti-fuse FPGA, and expands the scale of the anti-fuse FPGA.

The above-mentioned topology structure includes at least a three-dimensional arrangement structure of programmable logic modules, and wiring channels and wiring schemes between programmable logic modules. It is characterized by the following steps:

1) Using the three-dimensional arrangement of programmable combinational logic modules and programmable sequential logic modules in space to form a multi-layer three-dimensional arrangement structure of programmable logic modules;

2) For the multi-layer three-dimensional arrangement structure of programmable logic modules, various wiring channels are set between adjacent programmable logic modules within and between layers;

3) The interconnection between adjacent programmable logic modules is realized through different wiring methods, and for the programmable logic modules with a long distance, the interconnection is realized through a half-length line and a long line.

For the multi-layer three-dimensional arrangement structure of programmable logic modules, it can be expanded in all directions of x, y, and z. The simplest application of this structure is a structure with only two layers in the z-direction, and a structure with three or more layers in the z-direction can be used for designs that require a larger chip scale.

Between a programmable logic module and all other adjacent programmable logic modules, it is possible to choose whether to set a routing channel according to actual needs; there are four types of routing channels: axial routing channel, intra-layer diagonal routing channel, layer routing channel Inter-plane diagonal wiring channels and inter-layer space diagonal wiring channels; wiring channels between adjacent programmable logic modules have two types of saturated short-line wiring and simple short-line wiring, and each wiring channel can use any one. The wiring method is used to ensure the abundance of wiring resources and the flexibility of wiring methods.

In actual manufacturing, the structure should be manufactured by means of three-dimensional circuit integration within a single chip, rather than by means of three-dimensional packaging and integration between multiple chips.

The structure is not limited to the three-dimensional design of the anti-fuse FPGA, but can also be applied to the three-dimensional design of the SRAM type FPGA and the EEPROM/FLASH type FPGA.

Description of drawings

FIG. 1 is a multi-layer three-dimensional arrangement structure of programmable logic modules in the present invention.

FIG. 2 is a schematic diagram of the three-dimensional distribution of the complete wiring channels of the present invention.

3 is a schematic diagram of three-dimensional distribution of wiring channels between a programmable logic module and its adjacent programmable logic modules in the present invention.

FIG. 4 is a schematic diagram of the distribution of routing channels of a typical two-dimensional FPGA.

FIG. 5 is a schematic diagram of the three-dimensional distribution of the axial wiring channels of the present invention.

FIG. 6 is a schematic diagram of the distribution of the diagonal complete wiring channel in the layer of the present invention.

FIG. 7 is an intra-layer diagonal routing channel type 1 of the present invention.

FIG. 8 is an intra-layer diagonal routing channel type 2 of the present invention.

FIG. 9 is a schematic diagram of the three-dimensional distribution of the complete wiring channels on the diagonal of the interlayer plane in the xz plane of the present invention.

FIG. 10 is an interlayer plane diagonal routing channel type 1 of the xz plane of the present invention.

FIG. 11 is an interlayer plane diagonal routing channel type 2 of the xz plane of the present invention.

12 is a schematic diagram of a diagonal wiring channel between a programmable logic module and an adjacent programmable logic module in the present invention.

FIG. 13 is a schematic diagram of a saturated stub routing resource for routing channels.

Figure 14 is a schematic diagram of a simple short-line routing resource for routing channels.

Figure 15 is a schematic diagram of mixed routing resources across multiple programmable logic modules.

FIG. 16 is a comparison diagram of an example of the wiring effect of the present invention and an existing typical two-dimensional structure.

FIG. 17 is a diagram showing an example of the effect of three-dimensional wiring in a preferred typical application of the present invention.

Detailed ways

In order to make the technical solutions, structures and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

FIG. 1 is a multi-layer three-dimensional arrangement structure of programmable logic modules in the present invention. First, in the x direction, arrange the two programmable logic modules in the order of PCM-PSM-PCM... and PSM-PCM-PSM... (or in the reverse order) to form programmable logic lines L1 and L2, and then put L1 and L2 are arranged in the order of L1L2L1L2... and L2L1L2L1... respectively in the y direction to form two programmable logic layers F1 and F2, which are located in the xy plane, similar to the programmable logic array of a conventional two-dimensional FPGA. Finally, the two programmable logic layers are arranged in the order of F1F2F1F2... or F2F1F2F1... to form a multi-layer three-dimensional arrangement structure. For the sake of simplicity in the figure, only the distances of three programmable logic modules are drawn in the three directions of x, y, and z for illustration. In actual manufacturing, all directions can be expanded. For the three-dimensional structure with only three programmable logic module distances in the x, y, and z directions shown in Figure 1, we call it a programmable logic unit cell.

A 3D FPGA should be fabricated by fabricating one layer first, then fabricating the second layer on top of the first layer, and so on. For the convenience of discussion, we assume that the present invention always manufactures programmable logic layers in the xy plane first, and then stacks them in the z direction in practical applications, and calls each group of programmable logic modules with the same z coordinate as a programmable logic layer (hereinafter referred to as layer). For a programmable logic unit cell, it has three layers in the z direction.

FIG. 2 is a schematic diagram of the three-dimensional distribution of the complete wiring channels of the present invention. The biggest feature of the present invention is that wiring channels can be designed between any programmable logic module and all adjacent programmable logic modules. The so-called adjacent programmable logic modules refer to all other programmable logic modules except the logic module in the three-dimensional middle of the programmable logic unit cell size centered on one programmable logic module.

3 is a schematic diagram of three-dimensional distribution of wiring channels between a programmable logic module and its adjacent programmable logic modules in the present invention. We divide these routing channels into four broad categories, which are detailed below.

FIG. 4 is a schematic diagram of the distribution of routing channels of a typical two-dimensional FPGA. It is characterized in that the routing channels between the programmable logic modules are located in the x-direction and the y-direction, and there are no routing channels in other directions.

FIG. 5 is a schematic diagram of the three-dimensional distribution of the axial wiring channels of the present invention. The axial routing channel is the first type of routing channel in the present invention, which is similar to the routing channel of the conventional two-dimensional FPGA, and the difference is that it also adds routing channels in the z direction on the basis of the two-dimensional routing channel. Since these routing channels are parallel to the coordinate axis, we refer to this type of routing channels as axial routing channels.

FIG. 6 is a schematic diagram of the distribution of the diagonal complete wiring channel in the layer of the present invention. Intra-layer diagonal routing channels are the second type of routing channels in the present invention. Taking a programmable logic unit cell as an example, the intra-layer diagonal routing channels are located on the diagonals of four small rectangles defined by the programmable logic modules in each layer. Since this type of routing channel does not appear across layers and is distributed diagonally, we call this routing channel an intra-layer diagonal routing channel. This routing channel can have two orientations, so there are two types.

FIG. 7 is an intra-layer diagonal routing channel type 1 of the present invention.

FIG. 8 is an intra-layer diagonal routing channel type 2 of the present invention.

FIG. 9 is a schematic diagram of the three-dimensional distribution of the complete wiring channels on the diagonal of the interlayer plane in the xz plane of the present invention. The interlayer planar diagonal wiring channel is the third type of wiring channel in the present invention, which is located between layers. Taking a programmable logic unit cell as an example, the interlayer planar diagonal wiring channel is the same as the inner diagonal wiring channel. The line routing channel is somewhat similar, it is located on the diagonal of four small rectangles determined by the programmable logic module on the xz plane and the yz plane. Similarly, there are two interlayer plane diagonal routing channels on each plane. type.

FIG. 10 is an interlayer plane diagonal routing channel type 1 of the xz plane of the present invention.

FIG. 11 is an interlayer plane diagonal routing channel type 2 of the xz plane of the present invention.

The situation of the yz plane is similar to this, and details are not described here.

FIG. 12 is a schematic diagram of a diagonal wiring channel between a programmable logic module and an adjacent programmable logic module in the present invention. The interlayer space diagonal wiring channel is the fourth type of wiring channel in the present invention, and other wiring channels other than the above three types of wiring channels are called interlayer space diagonal wiring channels. As can be seen from the figure, the wiring channel between the programmable logic module at the center of the unit cell and the eight vertices of the unit cell is the diagonal wiring channel in the interlayer space.

In the three-dimensional structure proposed by the present invention, whether or not to design a wiring channel can be selected according to actual requirements between any two adjacent programmable logic modules.

For the distribution of wiring in the wiring channel between adjacent programmable logic modules, we have designed two wiring methods, namely saturated short-circuit wiring method and simple short-circuit wiring method. The following takes a wiring channel between a PCM and a PSM as an example, and the accompanying drawings illustrate.

Figure 13 is a schematic diagram of the saturated short-wire routing resource of the routing channel. The specific number of short lines can be determined according to the architecture of the anti-fuse FPGA, the design of PCM and PSM, and the number of input and output, in order to fully ensure the interconnectivity between programmable logic modules.

Figure 14 is a schematic diagram of a simple short-line routing resource for routing channels. This wiring method uses a small number of wiring lines, and only at least one, typically 3-5, and preferably no more than 10 short lines are arranged in the wiring channel.

In the above two wiring methods, each short line can be connected to the input and output of the programmable logic module through the anti-fuse structure, programming a specific anti-fuse, and the short line is connected to the specific input and output of the programmable logic module. An embodiment of the programmability of an antifuse FPGA.

For the three-dimensional arrangement structure of the programmable logic module, according to the specific architecture and design complexity of the FPGA, only the axial routing channel can be designed for it, or one or one of the other three types of routing channels can be added to the axial routing channel. variety. Each routing channel can apply any of the two routing methods described above. In order to ensure the abundance of wiring resources and the flexibility of wiring methods to the greatest extent. In the actual manufacturing process, since each layer is similar to the programmable logic array of a conventional two-dimensional FPGA, a better solution is to use a saturated short-circuit wiring method in each layer to fully ensure interconnectivity. For the axial routing channels between layers, we can apply saturated short-wire routing to them. For the interlayer plane diagonal wiring channel and the interlayer space diagonal wiring channel, both the saturated short-line wiring method and the simple short-line wiring method can be applied. The advantage of applying the saturated short-line wiring method is that various complex designs can be realized by using the abundant wiring resources between adjacent programmable logic modules; while the advantage of applying the simple short-line wiring method is that the process of this structure is more complex in the actual manufacturing process. Simple, three-dimensional synthesis between layers is also more convenient. At the same time, the simple short-circuit wiring can also reduce the requirements for the wiring algorithm.

The above discussion is only about the interconnection between adjacent programmable logic modules, and for the interconnection between programmable logic modules spanning several modules or a longer distance, half-length wires and long wires can be used for interconnection.

Figure 15 is a schematic diagram of mixed wiring resources across multiple programmable logic modules. Adjacent programmable logic modules can be interconnected through short wires and antifuses, and programmable logic modules spanning several modules can be connected through half-length wires and antifuses. Interconnects are implemented, and for longer distances, long wires and antifuses are used. By applying the semi-long line and long line technology to the three-dimensional space, the interconnection between the far-distance programmable logic modules in this structure can be realized.

For the structure proposed by the present invention, the routing algorithm can be implemented after improving the routing algorithm of the conventional two-dimensional FPGA.

The advantages of the novel topology proposed by the present invention are shown below through two specific examples.

FIG. 16 is a comparison diagram of an example of the wiring effect of the present invention and an existing typical two-dimensional structure. It can be found that, using the structure proposed by the present invention, a 3×3×3 structure, that is, in a three-dimensional structure of 27 programmable logic modules, the two programmable logic modules that are farthest apart are located at the two diagonal vertices of this structure , after the wiring channel is designed in the diagonal direction, the two programmable logic modules only need to cross one programmable logic module to achieve interconnection. For a conventional two-dimensional programmable logic array, in a 5×5 structure, even if the number of programmable logic modules is small, the interconnection of the two farthest programmable logic modules needs to span 7 other programmable logic modules. Programmable logic modules can complete the interconnection. It can be seen that the application of the structure proposed by the present invention can greatly reduce the distance between programmable logic modules and the length of interconnecting lines between programmable logic modules due to its three-dimensional characteristics, so as to achieve easier interconnection, and at the same time interconnecting lines The reduction in length can also reduce various parasitic effects and improve the operating speed of the chip. For a large-scale anti-fuse FPGA, by applying the structure proposed by the present invention, the package size can be greatly reduced, and a large-scale FPGA chip can be packaged with a small package.

FIG. 17 is a diagram showing an example of the effect of three-dimensional wiring in a preferred typical application of the present invention. As can be seen from the figure, when a design requires a large number of programmable logic modules of a certain type to realize interconnection, it may be assumed that this programmable logic module is PCM, using the structure proposed by the present invention, using the inter-layer The flat diagonal routing channel can realize the interconnection of multiple PCMs with only a few routing resources, and does not need to cross any PSM at all. It can be seen that due to the abundant wiring channels and flexible wiring methods proposed by the present invention, the fast direct connection between programmable logic modules can be realized by using less wiring resources, and the interconnection between programmable logic modules of the same type will not Excessive influence from different types of programmable logic modules.

To sum up, the new three-dimensional topology structure proposed in this invention, which can be applied to the anti-fuse FPGA programmable logic array, has three-dimensional space, rich and diverse wiring resources, flexible wiring methods, and programmable logic modules. The advantages of convenient interconnection and scalability of the overall structure in all directions. With the present invention, a large-scale, high-speed and small-package FPGA can be easily realized. The simplest application of the structure proposed by the present invention is the structure with only two layers in the z direction, and the design with higher requirements on the chip scale can be realized by a structure with three or more layers. In actual manufacturing, the structure should be manufactured by means of three-dimensional circuit integration within a single chip, rather than by means of three-dimensional packaging and integration between multiple chips.

The invention takes the anti-fuse FPGA as a typical application, and proposes a three-dimensional topology structure with universality, which can also be applied to the three-dimensional design of SRAM type FPGA and EEPROM/FLASH type FPGA. When there are two programmable logic modules in the FPGA, the three-dimensional structure design of the PCM plus PSM of the present invention can be directly adopted; when there is only one programmable logic module in the FPGA, the PCM and the PSM in the present invention are regarded as the same The three-dimensional structure of the present invention is directly adopted after a programmable logic module.

Claims (5)

1. A novel three-dimensional topology that can be applied to an antifuse FPGA programmable logic array, wherein the topology includes at least a three-dimensional arrangement of programmable logic modules, and wiring channels and wiring methods between programmable logic modules. ; It is characterized in that there are the following steps: 1) Utilizing the three-dimensional arrangement of programmable combinational logic modules and programmable sequential logic modules in space to form a multi-layer three-dimensional arrangement structure of programmable logic modules; the multi-layer three-dimensional arrangement structure is: first, in the x direction, the two The programmable logic modules are arranged in the order of PCM-PSM-PCM... and PSM-PCM-PSM... or in reverse order, respectively, to form programmable logic lines L1 and L2, and then L1 and L2 in the y direction are respectively L1L2L1L2 The order of ... and L2L1L2L1... constitutes two programmable logic layers F1 and F2. These two programmable logic layers are located in the xy plane. Finally, the two programmable logic layers are arranged in the order of F1F2F1F2... or F2F1F2F1... to form A multilayer three-dimensional arrangement structure; 2) For the multi-layer three-dimensional arrangement structure of programmable logic modules, multiple wiring channels are set between adjacent programmable logic modules within and between layers; the wiring channels have four types: axial wiring channels, intra-layer wiring channels, and intra-layer wiring channels. Diagonal routing channels, inter-layer plane diagonal routing channels and inter-layer space diagonal routing channels; the axial routing channels include routing channels in the x-direction, y-direction and z-direction, and the routing channels are all connected with The coordinate axes are parallel; in a programmable logic unit cell, the intra-layer diagonal routing channels are located on the diagonals of the four rectangles determined by the programmable logic module in each layer, and the intra-layer diagonal routing channels Channels do not appear across layers and are distributed diagonally; in a programmable logic unit cell, the interlayer planar diagonal routing channels are located in four rectangular areas defined by programmable logic modules on the xz and yz planes. On the diagonal; the diagonal wiring channel of the interlayer space is located between the programmable logic module at the center of the programmable logic unit cell and the eight vertices of the programmable logic unit cell; 3) The interconnection between adjacent programmable logic modules is realized through different wiring methods, and for the programmable logic modules with a long distance, the interconnection is realized through a half-length line and a long line. 2. the novel three-dimensional topology that can be applied to antifuse FPGA programmable logic array according to claim 1, it is characterized in that, for the multilayer three-dimensional arrangement structure of programmable logic module, it is in each direction of x, y, z Both can be expanded; the simplest application of this structure is a structure with only two layers in the z direction, and a structure with three or more layers in the z direction can be used for designs with larger chip scale requirements. 3. the novel three-dimensional topology that can be applied to antifuse FPGA programmable logic array according to claim 1, it is characterized in that, between a programmable logic module and all other programmable logic modules adjacent to it can be based on Choose whether to set up routing channels according to actual needs; there are four types of routing channels: axial routing channels, intra-layer diagonal routing channels, inter-layer planar diagonal routing channels, and inter-layer space diagonal routing channels; adjacent programmable routing channels There are two types of wiring channels between logic modules: saturated short-circuit wiring and simple short-circuit wiring. Each wiring channel can use any wiring method to ensure abundant wiring resources and flexible wiring methods. 4. the novel three-dimensional topology structure that can be applied to anti-fuse FPGA programmable logic array according to claim 1, it is characterized in that, this structure should adopt the mode of single-chip three-dimensional circuit integration to manufacture in actual manufacture, Instead of adopting multi-chip inter-chip three-dimensional packaging integration. 5. the novel three-dimensional topology structure that can be applied to anti-fuse FPGA programmable logic array according to claim 1, is characterized in that, this structure is not limited to the three-dimensional design that is applied to anti-fuse FPGA, can also be applied to SRAM 3D design of FPGA and EEPROM/FLASH FPGA.

Images