CN108594555A - Active element array substrate - Google Patents

Abstract

The invention discloses an active element array substrate, which includes a substrate, a first circuit layer, a first insulating layer, a plurality of semiconductor layers, a second circuit layer, a second insulating layer, a transparent conductive pattern layer and a plurality of pad layers. The first insulation layer covers the first circuit layer and the substrate. The semiconductor layer is located on the first insulating layer. The second circuit layer is located on the first insulation layer. The second insulation layer covers the second circuit layer and the semiconductor layer. The transparent conductive pattern layer is located on the second insulating layer and has a plurality of gap areas. Each gap area is formed between two adjacent edges of the transparent conductive pattern layer, and overlaps with the first circuit layer, but does not overlap with the second circuit layer and the semiconductor layer. The cushion layer is sandwiched between the first insulating layer and the second insulating layer and located in the gap area. Each pad layer overlaps part of the first circuit layer and protrudes from the edge of the first circuit layer.

Description

Active element array substrate

technical field

The invention relates to a display device, and in particular to an active element (active element) array substrate in the display device.

Background technique

At present, most liquid crystal display panels use a transparent conductive film (transparent conductive film) as a pixel electrode (pixel electrode) for driving liquid crystal molecules. The transparent conductive film is usually made of transparent conductive oxide (TCO). For example, Indium Tin Oxide (ITO). In addition, the ITO will crystallize after absorbing enough heat energy to produce crystallized ITO.

In detail, in the active (active) element array substrate of the existing liquid crystal display, the pixel electrode made of indium tin oxide (ITO) will generate more heat due to the process (such as baking and annealing) to produce crystals. The crystals tend to appear in the gap between two adjacent pixel electrodes, and extend to the gap between two adjacent pixel electrodes, so as to electrically connect the two adjacent pixel electrodes. This will cause the two pixel electrodes to be short-circuited to each other and be at the same potential, so that an appropriate electric field cannot be generated to rotate the liquid crystal molecules, resulting in an error in the gray level corresponding to the above pixel electrodes, resulting in color distortion of the image of the liquid crystal display and poor image quality. Falling flaws.

Contents of the invention

The invention provides an active element array substrate, which includes a pad layer that can prevent the above-mentioned crystals from being connected to adjacent two edges of the transparent conductive pattern layer.

The active element array substrate provided by at least one embodiment of the present invention includes a substrate, a first wiring layer, a first insulating layer, multiple semiconductor layers, a second wiring layer, a second insulating layer, a transparent conductive pattern layer, and multiple pad layers (padlayer). The substrate has a plane, and the first circuit layer is arranged on the plane of the substrate. The first insulating layer is configured on the first circuit layer and covers the first circuit layer. These semiconductor layers are arranged on the first insulating layer, wherein each layer of semiconductor layers overlaps with part of the first circuit layer. The second circuit layer is disposed on the first insulating layer and connected to these semiconductor layers, wherein the first circuit layer, the first insulating layer, these semiconductor layers and the second circuit layer form a plurality of active elements. The second insulating layer is disposed on the second circuit layer and covers the second circuit layer and the semiconductor layers. The transparent conductive pattern layer is configured on the second insulating layer and electrically connected to the second circuit layer. The transparent conductive pattern layer has a plurality of gap regions (gap regions), and each gap region is formed between two adjacent edges of the transparent conductive pattern layer, and overlaps with the first circuit layer, but does not overlap with the second circuit layer and these semiconductor layer. These cushion layers are interposed between the first insulating layer and the second insulating layer, and are respectively located in the gap regions. Each pad layer overlaps part of the first circuit layer and protrudes from the edge of the first circuit layer.

In at least one embodiment of the present invention, the above-mentioned first circuit layer protrudes from the adjacent two edges of the transparent conductive pattern layer forming the gap area, and the first circuit layer located in the same gap area protrudes from the adjacent two edges of the transparent conductive pattern layer. One of the edges extends to the other.

In an embodiment of the present invention, in the same gap area, the edge of the first circuit layer is perpendicular to two adjacent edges of the transparent conductive pattern layer.

In an embodiment of the present invention, the above-mentioned first circuit layer includes a plurality of metal lines, and a plurality of segments of each metal line overlap with a plurality of gap regions respectively.

In an embodiment of the present invention, the transparent conductive pattern layer includes a plurality of pixel electrodes, and at least one gap region is located between two adjacent pixel electrodes.

In an embodiment of the present invention, the above-mentioned first circuit layer includes a plurality of common lines. These common lines partially overlap with these pixel electrodes, and multiple line segments of each common line overlap with multiple gap regions respectively.

In an embodiment of the present invention, the line segments of the common lines respectively extend along the gap regions.

In an embodiment of the invention, at least one common line comprises a plurality of U-shaped segments.

In an embodiment of the present invention, the transparent conductive pattern layer includes a plurality of pixel electrodes and a plurality of bridging lines, and the first circuit layer includes a plurality of common line segments. Each bridging line is connected to two adjacent common line segments to form a plurality of parallel common lines, and at least one gap area is formed between adjacent bridging lines and pixel electrodes.

In an embodiment of the present invention, the above-mentioned first circuit layer further includes a plurality of parallel scan lines. The scan lines intersect with the bridge lines, and the scan lines partially overlap with the gap regions. At least one pad overlaps a part of one of the scanning lines and protrudes from the edge of the scanning line.

In an embodiment of the present invention, the above-mentioned second circuit layer and the pad layers are the same film layer.

In an embodiment of the present invention, the above-mentioned semiconductor layer and the pad layers are the same film layer.

Based on the above, the above pad layer can prevent the growth of crystals in the gap region along the edge of the first circuit layer, and prevent the crystals from being connected to the adjacent two edges of the transparent conductive pattern layer (for example, the edges of two adjacent pixel electrodes) , to prevent the pixel electrode from being electrically connected to other parts of the transparent conductive pattern layer (such as other pixel electrodes or bridge lines), and to prevent the pixel electrode from generating an improper electric field to rotate the liquid crystal molecules, thereby helping to maintain or improve image quality.

In order to make the above and other features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic wiring diagram of an active device array substrate according to at least one embodiment of the present invention;

Fig. 1B is a partially enlarged schematic diagram in Fig. 1A;

FIG. 1C is a schematic cross-sectional view along line 2C-2C in FIG. 1B;

2A is a schematic diagram of wiring of an active element array substrate according to another embodiment of the present invention;

Fig. 2B is a partially enlarged schematic diagram in Fig. 2A;

FIG. 2C is a schematic cross-sectional view taken along the line 3C-3C in FIG. 2B .

Symbol Description

200, 300: active element array substrate

210, 310: first line layer

211: shared line

211a, 211b, 211c: line segment

212, 312: scan line

220, 320: second line layer

222: data line

230: first insulating layer

240: second insulating layer

250: Substrate

252: plane

280, 380: Cushion

290, 390: transparent conductive pattern layer

291, 391: pixel electrodes

292, 392: Interstitial area

311: shared line segment

312e, 391e, 393e, E21, E29: Edge

313: electrode layer

393: Bridge line

C2: semiconductor layer

D2, D3: drain

G2, G3: Gate

S2, S3: source

T2, T3: active components

Detailed ways

FIG. 1A is a schematic wiring diagram of an active device array substrate according to at least one embodiment of the present invention. Referring to FIG. 1A , the active device array substrate 200 includes a first circuit layer 210 , a second circuit layer 220 , a transparent conductive pattern layer 290 and a plurality of semiconductor layers C2 . The second circuit layer 220 is located between the first circuit layer 210 and the transparent conductive pattern layer 290 , and the semiconductor layers C2 are located between the first circuit layer 210 and the second circuit layer 220 . In the active device array substrate 200 shown in FIG. 1A , the transparent conductive pattern layer 290 is located above the first wiring layer 210 , the second wiring layer 220 and these semiconductor layers C2 .

The transparent conductive pattern layer 290 is made of transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and has a plurality of gap regions 292 . Each gap region 292 is formed between two adjacent edges of the transparent conductive pattern layer 290 , wherein each gap region 292 overlaps with the first circuit layer 210 , but does not overlap with the second circuit layer 220 and the semiconductor layers C2 . In other words, neither the second circuit layer 220 nor the semiconductor layers C2 are in any gap region 292 , as shown in FIG. 1A . In addition, the transparent conductive pattern layer 290 includes a plurality of pixel electrodes 291, and at least one gap region 292 is located between two adjacent pixel electrodes 291, wherein each gap region 292 shown in FIG. 1A can be formed between two adjacent pixel electrodes. 291 between the edges.

The first circuit layer 210 includes a plurality of common lines 211, and each common line 211 can be a metal line, and has a plurality of line segments 211a, 211b, and 211c, wherein the line segments 211a, 211b, and 211c are connected to form a U-shaped segment, such as Figure 1A. At least one common line 211 may include a plurality of U-shaped segments, and from the embodiment of FIG. 1A , at least two common lines 211 each include a plurality of U-shaped segments. The common lines 211 partially overlap the pixel electrodes 291 to form storage capacitors (Cst on common) built on the common lines.

The U-shaped segments of the common line 211 , ie, the segments 211 a , 211 b and 211 c , substantially extend along the edge of the pixel electrode 291 , wherein the segments 211 c respectively extend along the gap regions 292 and overlap with the gap regions 292 . The first circuit layer 210 also includes a plurality of scanning lines 212, and each scanning line 212 can be a metal line, wherein the scanning lines 212 are not in contact with or connected to the common line 211, so there is no electrical connection between the scanning lines 212 and the common line 211. sexual conduction. In addition, in the first circuit layer 210 shown in FIG. 1A , only the common line 211 is located in the gap area 292 , and the scan line 212 is not located in the gap area 292 .

FIG. 1B is a partially enlarged schematic view of FIG. 1A . Referring to FIG. 1A and FIG. 1B , the first circuit layer 210 (here, for example, the common line 211 ) located in the same gap region 292 extends from one of two adjacent edges E29 of the transparent conductive pattern layer 290 to the other. Taking FIG. 1B as an example, in the same gap area 292, the first circuit layer 210 (here, for example, the common line 211) protrudes from two adjacent edges E29 of the transparent conductive pattern layer 290, and the first circuit layer 210 ( Here, for example, the edge E21 of the common line 211) is perpendicular to two adjacent edges E29 of the transparent conductive pattern layer 290, wherein the aforementioned vertical means substantially vertical. That is to say, when ordinary people only use an optical microscope to look down at the gap region 292 without using other measuring tools, most people will think that the edge E21 of the first circuit layer 210 (here, for example, the common line 211 ) is perpendicular to the transparent conductive layer 210 . Pattern layer 290 edge E29.

Since each gap area 292 is formed between two adjacent edges E29 of the transparent conductive pattern layer 290 (for example, the pixel electrode 291 here), and overlaps the first circuit layer 210 (for example, the common line 211 here), but does not Overlaid on the second circuit layer 220 and the semiconductor layer C2, the transparent conductive pattern layer 290 around the gap region 292 is prone to crystallization and produce crystallization after a process that generates more heat energy (such as baking and annealing). The active device array substrate 200 further includes a plurality of pad layers 280 . These pad layers 280 are respectively located in these gap regions 292, and each pad layer 280 overlaps a part of the first circuit layer 210 (for example, the common line 211 here), and protrudes from the first circuit layer 210 (for example, the common line 211 here). edge E21 of line 211). The pad layer 280 can prevent crystals from growing along the edge E21 to be connected to two adjacent edges E29 , preventing two adjacent pixel electrodes 291 from being electrically connected to each other.

FIG. 1C is a schematic cross-sectional view taken along line 2C-2C in FIG. 1B . Referring to FIGS. 1A to 1C , the active device array substrate 200 further includes a substrate 250 , a first insulating layer 230 and a second insulating layer 240 . The substrate 250 can be a transparent substrate, such as a glass substrate or a sapphire substrate. The substrate 250 has a plane 252 , and the first circuit layer 210 and the first insulating layer 230 are disposed on the plane 252 , and the first insulating layer 230 is disposed on the first circuit layer 210 and covers the first circuit layer 210 . Therefore, the first wiring layer 210 is sandwiched between the first insulating layer 230 and the substrate 250 .

These semiconductor layers C2 and the second circuit layer 220 are all disposed on the first insulating layer 230, wherein the second circuit layer 220 covers and connects these semiconductor layers C2, and each semiconductor layer C2 overlaps part of the first circuit layer 210, namely Each semiconductor layer C2 is located right above part of the first wiring layer 210 . The second insulating layer 240 is disposed on the second circuit layer 220 and covers the second circuit layer 220 and the semiconductor layers C2 , and the transparent conductive pattern layer 290 is disposed on the second insulating layer 240 .

The first wiring layer 210 , the first insulating layer 230 , the semiconductor layers C2 and the second wiring layer 220 form a plurality of active devices T2 , wherein the active devices T2 can be thin film transistors. Specifically, the first circuit layer 210 also includes a plurality of gates G2, wherein the gates G2 are connected to the scan lines 212, so that the scan lines 212 are electrically connected to the gates G2, and can transmit electrical signals to the gates G2 . In addition, the gates G2 are individually overlapped on the semiconductor layers C2, and the first insulating layer 230 is disposed between the gates G2 and the semiconductor layer C2 to separate the gates G2 from the semiconductor layer C2.

The second circuit layer 220 includes a plurality of data lines 222, a plurality of sources S2 and a plurality of drains D2, wherein the sources S2 are connected to the data lines 222, so that the data lines 222 are electrically connected to the sources S2, and can The electric signal is transmitted to the source S2. The source S2 and the drain D2 are separated from each other and contact and connect to the same layer of semiconductor layer C2, wherein both the source S2 and the drain D2 can form an ohmic contact with the semiconductor layer C2 to reduce impedance. The first insulating layer 230 , the gate G2 , the semiconductor layer C2 , the source S2 and the drain D2 form a plurality of active devices T2 , which have a field-effect transistor (Field-Effect Transistor, FET) structure.

In addition, the transparent conductive pattern layer 290 is electrically connected to the second circuit layer 220 . Specifically, the pixel electrodes 291 of the transparent conductive pattern layer 290 pass through the second insulating layer 240 and are individually connected to the drains D2, so that the active elements T2 are respectively electrically connected to the pixel electrodes 291, and can transmit electrical signals to these pixel electrode 291 . Since the gate G2 is connected to the scan line 212 and the source S2 is connected to the data line 222, the scan line 212 and the data line 222 can be used to control the active elements T2 to transmit electrical signals to the pixel electrodes 291, so that the pixel electrodes 291 generate an electric field to rotate liquid crystal molecules to display video images.

It is worth mentioning that the first circuit layer 210 and the second circuit layer 220 can be formed by photolithography and etching. That is to say, in the first circuit layer 210, the gates G2, the common lines 211 and the scan lines 212 can be formed by photolithography and etching of the same metal layer, so the gate G2, the common lines 211 and the scan lines The wires 212 can be the same film layer. Similarly, in the second wiring layer 220, the data lines 222, the source S2 and the drain D2 can also be formed by photolithography and etching on the same metal layer, that is, the data lines 222, the source S2 and the drain D2 can also be the same film layer. In addition, the second circuit layer 220 and the pad layers 280 may be the same film layer. That is to say, the second circuit layer 220 and the pad layer 280 can be formed by the same metal layer after photolithography and etching, so the pad layer 280 can also be a metal layer.

The pad layers 280 are disposed on the first insulating layer 230 , and the second insulating layer 240 covers the pad layers 280 . Therefore, these pad layers 280 are interposed between the first insulating layer 230 and the second insulating layer 240 . Accordingly, the pad layer 280 can bulge the second insulating layer 240 within the gap region 292 . Even if the transparent conductive pattern layer 290 produces crystals at the gap region 292 after processes that generate more heat energy (such as baking and annealing), the crystals will be caused by the bulging of the second insulating layer 240 caused by the pad layer 280. It is difficult to electrically connect two adjacent pixel electrodes 291 because of obstacles. Secondly, because the pad layer 280 protrudes from the edge E21 of the first circuit layer 210 (eg, the common line 211 here), the pad layer 280 can hinder the growth of crystals along the edge E21 . It can be seen that the pad layer 280 can prevent crystals from electrically connecting two adjacent pixel electrodes 291, so as to ensure that the two adjacent pixel electrodes 291 will not be electrically connected to each other and short-circuited, thereby helping to maintain or improve Image quality.

2A is a schematic diagram of wiring of an active device array substrate according to another embodiment of the present invention, FIG. 2B is a partially enlarged schematic diagram of FIG. 2A , and FIG. 2C is a schematic cross-sectional view along line 3C-3C in FIG. 2B. Please refer to FIG. 2A to FIG. 2C , the active device array substrate 300 of this embodiment is similar to the active device array substrate 200 of the previous embodiment, both have the same function, and also include the same or similar components.

For example, the active device array substrate 300 includes a substrate 250, a first wiring layer 310, a second wiring layer 320, a plurality of pad layers 380, a plurality of semiconductor layers C2, a first insulating layer 230, a second insulating layer 240 and a transparent conductive pattern layer 390, wherein the first wiring layer 310, the second wiring layer 320, these semiconductor layers C2 and the first insulating layer 230 can form a plurality of active elements T3 having a field effect transistor (FET) structure. Each active device T3 has a gate G3 , a source S3 and a drain D3 . The first circuit layer 310 includes a plurality of parallel scan lines 312, and the second circuit layer 320 includes a plurality of parallel data lines 322, wherein the scan lines 312 are connected to the gate G3, the data lines 322 are connected to the source S3, and the transparent conductive pattern Layer 390 is connected to drain D3. The relative positions and configurations of the first circuit layer 310 , the second circuit layer 320 , the semiconductor layers C2 and the first insulating layer 230 are substantially the same as those of the active device array substrate 200 of the foregoing embodiment.

Secondly, the constituent materials of the first circuit layer 310, the second circuit layer 320 and the transparent conductive pattern layer 390 may be the same as those of the first circuit layer 210, the second circuit layer 220 and the transparent conductive pattern layer 290 respectively. , and the forming method of the first wiring layer 310 and the second wiring layer 320 may also be the same as the forming method of the first wiring layer 210 and the second wiring layer 220 . The differences between the active device array substrates 300 and 200 are mainly described below, and the same technical features of the active device array substrates 300 and 200 will not be repeated in principle.

The transparent conductive pattern layer 390 also has a plurality of gap regions 392 , wherein each gap region 392 is also located between two adjacent edges of the transparent conductive pattern layer 390 . However, the gap area 392 is still different from the aforementioned gap area 292 . Specifically, the transparent conductive pattern layer 390 includes a plurality of pixel electrodes 391 and a plurality of bridging lines 393, wherein at least one of the bridging lines 393 is surrounded by four adjacent pixel electrodes 391, and at least one gap region 392 is formed in Between the adjacent bridge lines 393 and the pixel electrodes 391 . Taking FIG. 2A and FIG. 2B as an example, each gap region 392 is located between the adjacent bridging line 393 and the edge of the pixel electrode 391 .

The first wiring layer 310 is formed on the plane (not shown) of the substrate 250, and is sandwiched between the substrate 250 and the first insulating layer 230, wherein the formation method of the first wiring layer 310 can be the same as that of the aforementioned first wiring layer 210. method of formation. The first circuit layer 310 includes a plurality of common line segments 311, and each bridge line 393 passes through the second insulating layer 240 and the first insulating layer 230 in sequence and connects to two adjacent common line segments 311 to form multiple parallel lines. shared line. In addition, the scan lines 312 of the first circuit layer 310 are intersected with the bridge lines 393 . Different from the foregoing embodiments, the scanning line 312 partially overlaps the gap area 392 , but the common line segment 311 does not overlap the gap area 392 .

In the same gap region 392, the edge 312e of the scan line 312 is perpendicular to the edge 393e of the bridge line 393 and the edge 391e of the pixel electrode 391, wherein the edge 393e is adjacent to the edge 391e. As described in the foregoing embodiments, the vertical here refers to substantially vertical, which means that when ordinary people only use an optical microscope to look down at the gap region 392 without using other measurement tools, most people will think that the edge of the scan line 312 is 312e is perpendicular to the edge 393e of the bridge line 393 and the edge 391e of the pixel electrode 391 .

At least one pad layer 380 overlaps a portion of one of the scan lines 312 . Taking FIG. 2A and FIG. 2B as an example, each pad layer 380 overlaps a part of the scan line 312 located in the gap region 392 and protrudes from the edge 312 e of the scan line 312 . Therefore, when the transparent conductive pattern layer 390 crystallizes, the pad layer 380 can also prevent crystals from growing along the edge 312 e of the scan line 312 , preventing the crystals from connecting adjacent bridge lines 393 and pixel electrodes 391 .

Secondly, these pad layers 380 are also sandwiched between the first insulating layer 230 and the second insulating layer 240, so the pad layer 380 can also make the second insulating layer 240 in the gap region 392 bulge, so as to prevent the crystallization from connecting adjacent The bridge line 393 and the pixel electrode 391. It can be seen from this that the pad layer 380 can prevent the crystals from electrically connecting the adjacent bridge lines 393 and the pixel electrodes 391, and prevent the pixel electrodes 391 from being at a common potential due to directly receiving the electrical signal transmitted by the bridge lines 393, so as to avoid occurrence of pixel electrode 391. 391 corresponding to the gray level error, which helps to maintain or improve the image quality.

It is worth mentioning that, in the embodiment shown in FIGS. 2A to 2C , the semiconductor layers C2 and the pad layers 380 may be the same film layer. Therefore, the semiconductor layers C2 and the pad layers 380 can be formed from the same semiconductor layer after photolithography and etching, that is, the pad layer 380 can be a semiconductor layer. However, in other embodiments, the pad layer 380 and the second circuit layer 320 can also be the same film layer, so the pad layer 380 can also be a metal layer. It should be noted that, in the embodiment shown in FIG. 1A to FIG. 1C , the pad layer 280 and the semiconductor layers C2 may also be the same film layer, so the pad layer 280 shown in FIG. 1C may also be a semiconductor layer.

In addition, different from the previous embodiments, in this embodiment, the first circuit layer 310 further includes a plurality of electrode layers 313, and these electrode layers 313 overlap with part of the pixel electrodes 391, wherein the electrode layer 313 and the pixel electrode 391 The first insulating layer 230 is separated to form a storage capacitor. In addition, from FIG. 2A and FIG. 2B , these scan lines 312 overlap with part of the pixel electrodes 391 to form a storage capacitor (Cs on gate).

To sum up, the cushion layer disclosed in the above embodiments of the present invention can prevent the short circuit caused by the crystallization of the transparent conductive pattern layer, so as to prevent the pixel electrode from generating an inappropriate electric field to rotate the liquid crystal molecules, and reduce the degree of distortion of the image color, thereby Help maintain or improve image quality.

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (12)

1. a kind of active component array base board, which is characterized in that including：

Substrate has a plane；

First line layer is configured in the plane of the substrate；

First insulating layer is configured on the first line layer, and covers the first line layer；

Multiple semiconductor layers are configured on first insulating layer, wherein respectively the semiconductor layer is Chong Die with the part first line layer；

Second line layer is configured on first insulating layer, and connects those semiconductor layers, wherein the first line layer, this One insulating layer, those semiconductor layers and second line layer form multiple active members；

Second insulating layer is configured on second line layer, and covers second line layer and those semiconductor layers；

Transparent conductive layer is configured in the second insulating layer, and is electrically connected second line layer, wherein the electrically conducting transparent figure Pattern layer has multiple interstitial areas, and respectively the interstitial area is formed between the adjacent two edges of the transparent conductive layer, and with this First line layer is overlapped, but is not overlapped in second line layer and those semiconductor layers；And

Multiple bed courses are folded between first insulating layer and the second insulating layer, and are located in those interstitial areas, respectively should Bed course is overlapped in the part first line layer, and protrudes from the edge of the first line layer.

2. active component array base board as described in claim 1, wherein the first line layer protrude to form the interstitial area The adjacent two edges of the transparent conductive layer, and the first line layer in the same interstitial area is from the transparent conductive layer One of adjacent two edges extend to another one.

3. active component array base board as described in claim 1, wherein in same interstitial area, the edge of the first line layer Perpendicular to the adjacent two edges of the transparent conductive layer.

4. active component array base board as described in claim 1, wherein the first line layer include a plurality of metal wire, and respectively should Multiple line segments of metal wire respectively with multiple gap area overlappings.

5. active component array base board as described in claim 1, the wherein transparent conductive layer include multiple pixel electrodes, And at least one interstitial area is between two neighboring pixel electrode.

6. active component array base board as claimed in claim 5, wherein the first line layer include a plurality of bridging line, those are total It is Chong Die with those pixel electrode parts with line, and respectively multiple line segments of the bridging line respectively with multiple gap area overlappings.

7. active component array base board as claimed in claim 6, wherein those line segments of those bridging lines are respectively along those Interstitial area extends.

8. active component array base board as claimed in claim 6, wherein at least one bridging line includes multiple U sections.

9. active component array base board as described in claim 1, the wherein transparent conductive layer include multiple pixel electrodes With a plurality of bridging line, and the first line layer includes a plurality of shared line segment, and the respectively bridging line is connected to adjacent two shared lines section, To form a plurality of bridging line arranged side by side, and at least one interstitial area is formed between the adjacent bridging line and the pixel electrode.

10. active component array base board as claimed in claim 9, wherein the first line layer further include a plurality of scanning arranged side by side Line, those scan lines are interlocked with those bridging lines, and those scan lines partly overlap with those interstitial areas, an at least bed course weight It is laminated on a part for wherein one scan line, and protrudes from the edge of the scan line.

11. active component array base board as described in claim 1, wherein second line layer are same film with those bed courses Layer.

12. active component array base board as described in claim 1, the wherein semiconductor layer are same film layer with those bed courses.