CN108574565B

CN108574565B - Signal quality detection device and method for S-mode transmitter

Info

Publication number: CN108574565B
Application number: CN201810379611.XA
Authority: CN
Inventors: 刘志勇; 林琳; 刘引川
Original assignee: Sichuan Ads B Technology Co ltd
Current assignee: Sichuan Ads B Technology Co ltd
Priority date: 2018-04-25
Filing date: 2018-04-25
Publication date: 2024-05-31
Anticipated expiration: 2038-04-25
Also published as: CN108574565A

Abstract

The invention discloses a signal quality detection device and method of an S-mode transmitter, which relate to the technical field of transmitter detection and comprise a power management unit, a buffer unit for converting a radio frequency signal transmitted by an ADS-B transmitter into a linear voltage signal, a conversion unit for carrying out signal amplification and direct current voltage bias on one path of linear voltage signal, a decoding unit for carrying out synchronous head detection and PPM decoding on the other path of linear voltage signal and then assembling the signal into an ADS-B data message, sampling the amplified and direct current voltage biased analog voltage signal and then converting the sampled analog voltage signal into a digital signal, and a control unit for reading the digital signal of an analog-to-digital conversion part and receiving the ADS-B data message output by the ADS-B data decoding part and then analyzing and processing the signal and outputting the signal.

Description

Signal quality detection device and method for S-mode transmitter

Technical Field

The invention relates to the technical field of transmitter detection, in particular to a device and a method for detecting signal quality of an S-mode transmitter.

Background

The ADS-B transmitter is a device capable of transmitting ADS-B broadcast information of an aircraft, and has the function of transmitting information of flight number, ICAO address, longitude and latitude, altitude, speed, lifting rate, heading and the like of the aircraft outwards in a broadcast mode.

At present, the ADS-B transmitter generally determines whether to work normally by sending a signal to another receiving end, which is troublesome to implement and time-consuming, and no device capable of performing professional comprehensive detection on the ADS-B transmitter exists in the market, which cannot accurately determine whether a certain index or parameter of the ADS-B transmitter is normal, so that it is necessary to design a device capable of performing rapid and comprehensive detection on the ADS-B transmitter.

Disclosure of Invention

The invention aims at: the device and the method for detecting the signal quality of the S-mode transmitter solve the problems that the state of the ADS-B transmitter cannot be detected rapidly and qualitatively and the parameters of the ADS-B transmitter cannot be obtained accurately and quantitatively in the prior art.

The technical scheme adopted by the invention is as follows:

An S-mode transmitter signal quality detection device comprises a power supply management unit, a buffer unit, a conversion unit, a decoding unit, a control unit and an output unit;

buffer unit: for converting the radio frequency signal transmitted by the ADS-B transmitter into a linear voltage signal;

a conversion unit: the linear voltage signal amplifying circuit is used for amplifying a signal of one path of linear voltage signal and biasing direct current voltage;

Decoding unit: the method comprises the steps of performing synchronous head detection and PPM decoding on another linear voltage signal, assembling the other linear voltage signal into an ADS-B data message, sampling the amplified analog voltage signal subjected to DC voltage bias, and converting the sampled analog voltage signal into a digital signal;

And a control unit: the ADS-B data processing unit is used for reading the digital signal of the analog-to-digital conversion part and receiving the ADS-B data message output by the ADS-B data decoding part, analyzing and processing the ADS-B data message and outputting the ADS-B data message.

Further, the buffer unit comprises an attenuator for attenuating the radio frequency signal transmitted by the ADS-B transmitter and a logarithmic detector for linearly detecting the attenuated signal.

Further, the conversion unit includes an operational amplifier for amplifying a signal of one line of the linear voltage signal and a baseline bias for performing a direct current voltage bias on the amplified voltage signal.

Further, the decoding unit includes an ADS-B data decoding portion and an analog-to-digital converting portion.

Still further, the ADS-B data decoding part includes a 1bit digitizing module that digitizes another linear voltage signal, a decoder that performs synchronous header detection and PPM decoding of the digital pulse signal, and an ADS-B data output module that assembles the decoded signal.

Still further, the analog-to-digital conversion section includes an analog-to-digital converter that samples the analog voltage signal and converts the analog voltage signal into a digital signal, a FIFO memory that stores the digital signal, and a clock logic module that provides the analog-to-digital converter and the FIFO memory with a synchronous operating clock SCLK.

Still further, a sample lockout module is also provided between the decoder and the FIFO memory.

Further, the output unit comprises a keyboard and a display screen, and is matched with the indexes, waveform display and interactive parameter setting of the whole system.

A method for detecting signal quality of an S-mode transmitter, comprising the steps of:

step 1: converting a radio frequency signal transmitted by an ADS-B transmitter into a linear voltage signal and outputting the linear voltage signal;

step 2: carrying out signal amplification and direct-current voltage bias on one path of linear voltage signal;

Step 3: performing synchronous head detection and PPM decoding on the other route of linear voltage signal, then assembling the other route of linear voltage signal into an ADS-B data message, sampling the amplified analog voltage signal subjected to DC voltage bias, and then converting the sampled analog voltage signal into a digital signal;

step 4: reading the digital signal of the analog-to-digital conversion part, receiving the ADS-B data message output by the ADS-B data decoding part, analyzing and processing the ADS-B data message, and outputting the ADS-B data message.

In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:

1. The signal quality detection device and method of the S-mode transmitter can accurately and quantitatively obtain the power of the transmitter, the waveform parameter of each PPM code transmitting pulse and the power of a single pulse, and simultaneously can intuitively display the waveform and the tested parameter result, so that the user can conveniently check the signal quality;

2. The invention can not only rapidly and qualitatively detect the state of the transmitter in the external field, but also be used as a special internal field detection device;

3. The analog-to-digital conversion part comprises the FIFO memory for storing the digital signals, and a user can repeatedly read the data acquired before from the FIFO memory before the data is not updated and display the data in a text or graphic mode, so that the subsequent consulting and using are convenient;

4. The analog-to-digital conversion part of the invention also comprises a clock logic module for providing a synchronous working clock SCLK for the analog-to-digital converter and the FIFO memory, wherein the analog-to-digital converter stops subsequent data storage after acquiring an ADS-B signal of a frame so that a control unit can timely read the data in the FIFO memory;

5. The ADS-B data decoding part comprises a 1bit digitizing module for digitizing another route voltage signal, and the 1bit digitizing module can simply and effectively convert the analog signal into data stream information.

Drawings

The invention will now be described by way of example and with reference to the accompanying drawings in which:

fig. 1 is a schematic block diagram of an S-mode transmitter signal quality detection apparatus;

FIG. 2 is a graph of the output linearity of the logarithmic detector of the present invention;

FIG. 3 is a block diagram of a FIFO memory according to the present invention;

FIG. 4 is a schematic diagram of the 1bit digitization of the present invention;

fig. 5 is a decoder workflow diagram of step 7.

Detailed Description

All of the features disclosed in this specification, or all of the steps in a method or process disclosed, may be combined in any combination, except for mutually exclusive features and/or steps.

The present invention will be described in detail with reference to fig. 1 to 5.

The working principle of the invention is as follows:

the radio frequency signal transmitted by the ADS-B transmitter is connected to the radio frequency port of the device, the output signal of the transmitter is reduced to below 0dBm after passing through the attenuator of the buffer unit of the device, and then the signal is input to the logarithmic detector AD8313, and the logarithmic detector obtains and outputs a linear detection voltage signal of 20mV/dB within the input signal range of-60-0 dBm, thereby providing a basis for accurate power measurement.

The signal after the logarithmic detector is detected is divided into two paths of outputs: one path of the output signals are output to a conversion unit, the signal conditioning circuit formed by the operational amplifier LT1801 carries out signal amplification, and then the baseline bias carries out direct current voltage bias, and the output signals are not output until the output signals are suitable for the range which can be acquired by the analog-to-digital converter ADS830 of the analog-to-digital conversion part; and the other path is output to an ADS-B data decoding part of the decoding unit, and synchronous head detection and PPM decoding are carried out on the ADS-B signal.

According to the output linear diagram of the logarithmic detector of fig. 2, since the detected dc output voltage is about 0.5V when the logarithmic detector AD8313 inputs a signal of-60 dBm, and about 1.7V when the maximum signal is input of 0dBm, the maximum variation voltage in the entire 60dB linear input dynamic range is: Δv=1.7 to 0.5=1.2V. Therefore, the signal conditioning circuit amplification is set to 2/1.2=1.67 times, which is just suitable for the 2V full-amplitude Vpp input range of the analog-to-digital converter ADS830, and then the resolution of the analog-to-digital converter ADS830 is designed to be maximum: 2V/2 ⁸ = 7.8125mV.

And according to the formula, the detection linearity slope of the logarithmic detector is designed to be 20mV/dB, and the equivalent power value of each millivolt voltage in the whole 60dB dynamic range is as follows: 60dB/2000 mV=0.03 dB/mV, and the resolution of the analog-digital converter is 7.8125mV, so that the theoretical design power resolution is 7.8125 x 0.03= 0.234375dB, and the requirements of internal and external field detection can be completely met in actual requirements.

Because the analog-to-digital converter ADS830 uses the differential reference voltage mode, the direct current voltage at the common mode end is 2.5V, the maximum allowable input analog voltage is +/-1V, and the voltage input range for the 0V reference voltage end is 1.5-3.5V, therefore, the baseline bias circuit adjusts the voltage output by the logarithmic detector to direct current 1.5V output when-60 dBm is input, one of the dual operational amplifiers TL1801 is designed into an adder mode, the static output level of the operational amplifier is adjusted through a trimming potentiometer, the output voltage is 1.5V when the input signal is less than or equal to-60 dBm, and the output voltage is 3.5V when the input signal is 0 dBm.

The analog-to-digital converter ADS830 has a sampling rate up to 60M and a resolution up to 8bit, and completely satisfies the acquisition of PPM signals modulated by 1MHz of ADS-B, samples and converts the output analog voltage into digital signals, and then stores the digital signals in the FIFO memory. According to the nyquist theorem, the sampling frequency is at least 2 times of the highest frequency of the measured signal to reproduce the measured signal, and the invention adopts 32 times of sampling rate to sample the PPM signal, so as to restore the authenticity of the original analog signal after logarithmic detection as much as possible. For the case that the narrowest pulse width of the PPM signal of the ADS-B is 0.5us, under the condition of a 32M sampling rate, the sampling point of one pulse is 16 points, namely 16 pixels can be displayed on the liquid crystal display per pulse, and the index has good cost performance in consideration of compromise performance and realization cost. Meanwhile, the measurement theoretical value of the pulse width is 0.5 us/16=0.03125 us, and the requirement of the pulse width tolerance of 0.05-0.1 us defined by the international standard RTCA DO260B can be met.

The FIFO memory adopts an IDT7205 high-speed FIFO memory, is a dual-port SRAM, has no address line, and realizes memory area addressing by adding or subtracting data address pointers along with writing or reading signals. And a FIFO memory is added between the analog-to-digital converter and the control unit, so that the function of high-speed data buffering is achieved. Because the highest working frequency of the analog-to-digital converter is 32MHz, which is far higher than the processing capacity of the MCU processor, so that the data sampled by the analog-to-digital converter is prevented from being lost due to the fact that the data are not processed, the FIFO memory and the analog-to-digital converter synchronously work and store the output data of the analog-to-digital converter.

According to the FIFO memory block diagram of fig. 3, the FIFO memory has 3 flag bit pins, respectively FF (full flag: after the memory is full of the internal memory area, set the flag, at which time the memory will ignore any write data operation); HF (half full flag: after half storage area is full of memory, set the flag); EF (empty flag: when the memory contents are read empty, this flag is set, when the memory ignores all read data operations). The invention uses the HF mark for the cross-linking of the MCU processor and the reset end of the FIFO memory, stores ADS-B information before the synchronous head before the ADS-B synchronous trigger signal arrives, so as to avoid the front-end signal loss caused by restarting the analog-to-digital converter to store data after the ADS-B synchronous head is detected.

The capacity selection of the FIFO memory is calculated according to the following formula:

FIFO_size＝2(S_clk*T_ADS-B)

Wherein, FIFO _size is the total capacity selection of the FIFO memory, and the unit is bytes; s _clk is the sampling rate of the analog-to-digital converter in hertz, here 32MHz; t _ADS-B is the sampling time in seconds; from the international standard RTCA DO260B, it can be derived that the length of a frame ADS-B information is 120us, and FIFO _size =2 (3200000×0.00012) =7680 bytes. Thus, the FIFO memory uses an IDT7205 high speed FIFO memory, the IC size is 8K bytes (8192 bytes), meeting the basic requirements of the system 7680 bytes.

In the above formula for selecting FIFO memory capacity, at least 2 times the sampling time is required because: after the HF signal and the FIFO automatic reset enabling signal (FIFO_AUTO_RST_EN) of the MCU are logically and, when the FIFO_AUTO_RST_EN is valid and the FIFO memory is stored to a half space, if the ADS-B data decoding part does not detect the ADS-B synchronous head, the reset pin of the FIFO memory is triggered (15 ns) while the HF signal is valid, the FIFO memory is automatically reset, the HF signal is cleared (25 ns) after reset, and the FIFO memory starts to automatically store sampling data; when the FIFO memory automatically stores the sampled data, if the ADS-B data decoding part detects the ADS-B synchronous head, the FIFO memory outputs a trigger signal to the MCU, the MCU sends out a FIFO_AUTO_RST_EN blocking signal after judging, and the FIFO memory is not allowed to be automatically cleared, at the moment, the FIFO memory continuously stores the sampled data until 120us later, and the MCU actively stops the writing operation of the FIFO memory.

The analog-digital conversion part also comprises a clock logic module for providing a synchronous working clock SCLK for the analog-digital converter and the FIFO memory, wherein the SCLK of the analog-digital converter part is in a continuous running state, and the SCLK of the FIFO memory part is in a controlled working state, so that the subsequent analog-digital conversion data storage is stopped after a frame ADS-B signal is acquired, and the MCU can read the data in the FIFO memory in time. SCLK is output to WR port of FIFO memory, and controlled by CLK_EN port of MCU by AND gate mode. The MCU reads the FIFO memory in time to obtain the analog-to-digital conversion data stored in the FIFO memory before stopping sampling, and starts the write operation of the FIFO memory again after the reading is finished, and after the MCU obtains the analog-to-digital conversion data, the MCU performs data analysis and displays the data on the liquid crystal display screen.

The other path of signal input to the decoding unit is not directly sent to the ADS-B data decoding part for digital judgment because the amplitude and width of the analog pulse signal output by the logarithmic detector are not fixed due to the influence of the input signal strength along with the logarithmic relation of the amplitude of the analog pulse signal output by the logarithmic detector, and the analog pulse signal is required to be changed into a single logic level digital pulse signal through 1bit digital processing, and is sent to the decoder as an idealized 1bit data stream for decoding. According to the 1-bit digital schematic diagram of fig. 4, a high-speed comparator is used as a core component, an original detection signal is input from the positive end of the comparator, the negative end of the comparator is coupled with a part of the original signal to perform RC integration, and the integral parameter is strictly regulated, so that the amplitude of the negative end of the comparator is about 3dB lower than that of the positive end, and the comparator outputs a neat pulse square wave, thereby achieving the 1-bit quantization purpose.

According to the decoder workflow diagram of fig. 5, the decoder parses the quantized digital pulse signal, and the specific flow is: the decoder initializes the quantized pulse signal; capturing a synchronization head and caching a synchronization head sequence; judging the synchronous head, if the synchronous head is judged to be correct, carrying out subsequent bit capturing; if the judgment is wrong, the synchronous head is captured again; the captured subsequent bits are buffered in bit sequence; judging whether bit capturing is completed or not, and if so, performing CRC (cyclic redundancy check); if not, re-capturing the subsequent bit; judging whether the CRC is correct, if so, sending a decoding message to ADS-B data output; if the check is wrong, the recapture synchronization head is returned. And after judging by the synchronous head and checking by CRC, assembling into an ADS-B data message, and transmitting the ADS-B data message to ADS-B data output for interactive processing.

And a sampling locking module is also arranged between the decoder and the FIFO memory, when the FIFO memory automatically stores sampling data, if the decoder of the ADS-B data decoding part detects an ADS-B synchronous head signal, the resetting signal of the current FIFO memory is locked, so that the FIFO memory is not reset by invalid data, the ADS-B data information of the current frame can be stored, and the data information of at least 120us can be continuously collected.

The control unit adopts an MCU processor to read the FIFO memory, obtains sampling data and analog-to-digital conversion data stored in the FIFO memory before the analog-to-digital converter stops sampling, obtains ADS-B data, outputs ADS-B decoding data transmitted to the MCU, carries out MCU processing analysis, and displays the ADS-B decoding data through the display unit.

The display unit and the input unit are matched to complete the index, waveform display, interactive parameter setting and the like of the whole system. The input unit adopts a keyboard for input, the display unit adopts a 320 x 240 lattice TFT liquid crystal display screen for horizontally displaying 320 points, and the sampling points of 320 can be displayed in a 1:1 mode, namely PPM coding waveforms with the length of 10us, under a waveform display interface. The whole frame of ADS-B waveform single screen needs to be displayed for 12 times, and the pulse waveform concerned can be conveniently checked and displayed in a left-right moving mode in cooperation with keyboard operation. In waveform amplitude display, since the analog-to-digital converter adopts 8-bit resolution, the display range is from 0 to 255, and according to the parameters, the power is converted into 0.234375dB per unit, and the resolution of the liquid crystal display screen in the vertical direction is 240, so that each pixel represents 60/240=0.25 dB.

The liquid crystal display screen finally obtains the information such as the power waveform, pulse parameter width, pulse rising edge, pulse falling edge, original decoding data, the ICAO address of the aircraft, the flight number, longitude and latitude, altitude, speed, heading and the like of the ADS-B transmitter, and displays the information in a graphic and text mode, so that the information is convenient for a user to check.

The invention can accurately and quantitatively obtain the power of the transmitter, the waveform parameter of each PPM code transmitting pulse and the power of a single pulse, simultaneously can intuitively display the waveform and the tested parameter result, is convenient for a user to check, can rapidly and qualitatively detect the state of the transmitter in an external field, and can be used as a special internal field detection device.

The above description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that are not creatively contemplated by those skilled in the art within the technical scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope defined by the claims.

Claims

1. An S-mode transmitter signal quality detection apparatus, characterized in that: the device comprises a power supply management unit, a buffer unit, a conversion unit, a decoding unit, a control unit and an output unit; buffer unit: for converting the radio frequency signal transmitted by the ADS-B transmitter into a linear voltage signal; a conversion unit: the linear voltage signal amplifying circuit is used for amplifying a signal of one path of linear voltage signal and biasing direct current voltage; decoding unit: the method comprises the steps of performing synchronous head detection and PPM decoding on another linear voltage signal, assembling the other linear voltage signal into an ADS-B data message, sampling the amplified analog voltage signal subjected to DC voltage bias, and converting the sampled analog voltage signal into a digital signal; and a control unit: the ADS-B data decoding part is used for receiving the digital signals of the analog-to-digital conversion part and receiving the ADS-B data messages output by the ADS-B data decoding part, analyzing and processing the ADS-B data messages and outputting the ADS-B data messages;

The buffer unit comprises an attenuator for attenuating the radio frequency signal transmitted by the ADS-B transmitter and a logarithmic detector for linearly detecting the attenuated signal;

the decoding unit includes an ADS-B data decoding section and an analog-to-digital conversion section.

2. An S-mode transmitter signal quality detection apparatus as claimed in claim 1, wherein: the conversion unit comprises an operational amplifier for amplifying one path of linear voltage signal and a base line bias for carrying out direct current voltage bias on the amplified voltage signal.

3. An S-mode transmitter signal quality detection apparatus as claimed in claim 1, wherein: the ADS-B data decoding part comprises a 1bit digitizing module for digitizing another route voltage signal, a decoder for synchronous head detection and PPM decoding of digital pulse signals, and an ADS-B data output module for assembling the decoded signals.

4. An S-mode transmitter signal quality detection apparatus as claimed in claim 1, wherein: the analog-to-digital conversion part comprises an analog-to-digital converter for sampling the analog voltage signal and converting the analog voltage signal into a digital signal, a FIFO memory for storing the digital signal, and a clock logic module for providing a synchronous working clock SCLK for the analog-to-digital converter and the FIFO memory.

5. An S-mode transmitter signal quality detection apparatus according to claim 3 or 4, wherein: and a sampling locking module is also arranged between the decoder and the FIFO memory.

6. An S-mode transmitter signal quality detection apparatus as claimed in claim 1, wherein: the output unit comprises a keyboard and a display screen, and is matched with the indexes, waveform display and interactive parameter setting of the whole system.

7. An S-mode transmitter signal quality detection method, comprising the S-mode transmitter signal quality detection apparatus of any one of claims 1-6;

when the signal quality detection device of the S-mode transmitter is adopted for signal quality detection, the method comprises the following steps: