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CN108573924B - Semiconductor structure and method of forming the same - Google Patents

Semiconductor structure and method of forming the same Download PDF

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Publication number
CN108573924B
CN108573924B CN201710131086.5A CN201710131086A CN108573924B CN 108573924 B CN108573924 B CN 108573924B CN 201710131086 A CN201710131086 A CN 201710131086A CN 108573924 B CN108573924 B CN 108573924B
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layer
opening
work function
forming
doping
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CN108573924A (en
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王彦
纪世良
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

一种半导体结构及其形成方法，方法包括：提供衬底，衬底包括第一区域和第二区域，第一区域和第二区域衬底上具有介质层，第一区域介质层中具有第一开口，第二区域介质层中具有第二开口；在第一开口和第二开口底部和侧壁形成功能层；在第一开口底部和侧壁的功能层上形成第一掺杂层，第一掺杂层中具有第一功函调节离子；在第二开口底部和侧壁的功能层上形成第二掺杂层，第二掺杂层中具有第二功函调节离子；形成第一掺杂层和第二掺杂层之后，进行退火处理；去除第一掺杂层和第二掺杂层；在第一开口和第二开口中的功能层上形成功函数层；在第一开口和第二开口中形成栅极。形成方法能够改善所形成半导体结构性能。

Figure 201710131086

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate includes a first region and a second region, the first region and the second region have a dielectric layer on the substrate, and the first region has a first region in the dielectric layer. opening, the dielectric layer in the second region has a second opening; a functional layer is formed on the bottom and sidewalls of the first opening and the second opening; a first doped layer is formed on the functional layer on the bottom and sidewalls of the first opening, the first There are first work function adjusting ions in the doping layer; a second doping layer is formed on the functional layer of the bottom and sidewalls of the second opening, and the second doping layer has second work function adjusting ions; forming a first doping layer After the layer and the second doped layer, perform annealing treatment; remove the first doped layer and the second doped layer; form a work function layer on the functional layer in the first opening and the second opening; A gate is formed in the two openings. The formation method can improve the performance of the formed semiconductor structure.

Figure 201710131086

Description

半导体结构及其形成方法Semiconductor structure and method of forming the same

技术领域technical field

本发明涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

背景技术Background technique

随着半导体技术的不断进步，半导体器件的集成度不断提高，这就要求在一块芯片上能够形成更多的晶体管。With the continuous advancement of semiconductor technology, the integration level of semiconductor devices is continuously improved, which requires that more transistors can be formed on a chip.

阈值电压是晶体管的重要参数，对晶体管的性能具有重要影响。不同功能的晶体管往往对阈值电压具有不同的要求，在形成不同晶体管的过程中，需要对不同晶体管的阈值电压进行调节。为了对不同晶体管的阈值电压进行调节，往往在晶体管的栅介质层上形成功函数层。通过对功函数层的厚度和材料的选择能够使晶体管具有不同的阈值电压。Threshold voltage is an important parameter of a transistor and has an important impact on the performance of the transistor. Transistors with different functions often have different requirements on threshold voltages, and in the process of forming different transistors, the threshold voltages of different transistors need to be adjusted. In order to adjust the threshold voltage of different transistors, a work function layer is often formed on the gate dielectric layer of the transistor. The transistors can have different threshold voltages through the choice of the thickness and material of the work function layer.

然而，现有的半导体结构的形成方法所形成的半导体结构的性能较差。However, the semiconductor structure formed by the existing method for forming the semiconductor structure has poor performance.

发明内容SUMMARY OF THE INVENTION

本发明解决的问题是提供一种半导体结构及其形成方法，以提高所形成半导体结构的性能。The problem to be solved by the present invention is to provide a semiconductor structure and a method of forming the same to improve the performance of the formed semiconductor structure.

为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括第一区域和第二区域，所述第一区域和第二区域衬底上具有介质层，所述第一区域介质层中具有第一开口，所述第二区域介质层中具有第二开口；分别在所述第一开口和第二开口底部和侧壁形成功能层；在所述第一开口底部和侧壁的功能层上形成第一掺杂层，所述第一掺杂层中具有第一功函调节离子；在所述第二开口底部和侧壁的功能层上形成第二掺杂层，所述第二掺杂层中具有第二功函调节离子；形成所述第一掺杂层和第二掺杂层之后，进行退火处理，使所述第一功函调节离子扩散进入第一开口的功能层中，使第二功函调节离子扩散进入第二开口的功能层中；所述退火处理之后，去除所述第一掺杂层和第二掺杂层；去除所述第一掺杂层和第二掺杂层之后，在所述第一开口和第二开口中的功能层上形成功函数层；形成所述功函数层之后，在所述第一开口和第二开口中形成栅极。In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, and the first region and the second region have a dielectric layer on the substrate , the dielectric layer in the first region has a first opening, and the dielectric layer in the second region has a second opening; a functional layer is formed on the bottom and sidewalls of the first opening and the second opening respectively; A first doped layer is formed on the functional layer at the bottom and sidewalls of an opening, and the first doped layer has first work function adjusting ions; a second doped layer is formed on the functional layer at the bottom and sidewalls of the second opening Doping layer, the second doping layer has second work function adjusting ions; after forming the first doping layer and the second doping layer, annealing is performed to diffuse the first work function adjusting ions into the functional layer of the first opening, so that the second work function adjustment ions are diffused into the functional layer of the second opening; after the annealing treatment, remove the first doping layer and the second doping layer; remove the After the first doping layer and the second doping layer, a work function layer is formed on the functional layers in the first opening and the second opening; after the work function layer is formed, a work function layer is formed on the first opening and the second opening. A gate is formed in the opening.

可选的，形成所述第一掺杂层之后，形成所述第二掺杂层。Optionally, after forming the first doped layer, the second doped layer is formed.

可选的，所述第二掺杂层还位于所述第一掺杂层上。Optionally, the second doped layer is also located on the first doped layer.

可选的，形成所述第二掺杂层之后，形成所述第一掺杂层。Optionally, after forming the second doped layer, the first doped layer is formed.

可选的，所述第一区域用于形成NMOS晶体管，所述第一功函调节离子为镁离子。Optionally, the first region is used to form an NMOS transistor, and the first work function adjusting ions are magnesium ions.

可选的，所述第一掺杂层的材料为氮化钽或氮化钛。Optionally, the material of the first doping layer is tantalum nitride or titanium nitride.

可选的，所述第一掺杂层的厚度为8埃～10埃；所述第一掺杂层中的第一功函调节离子的浓度为4E14atoms/cm2～6E14atoms/cm2。Optionally, the thickness of the first doped layer is 8 angstroms to 10 angstroms; the concentration of the first work function adjusting ions in the first doped layer is 4E14 atoms/cm 2 -6E14 atoms/cm 2 .

可选的，所述第二区域用于形成PMOS晶体管，所述第二功函调节离子为铝离子。Optionally, the second region is used to form a PMOS transistor, and the second work function adjusting ions are aluminum ions.

可选的，所述第二掺杂层的材料为氧化铝、氮化钽或氮化钽。Optionally, the material of the second doping layer is aluminum oxide, tantalum nitride or tantalum nitride.

可选的，所述第二掺杂层的厚度为8埃～10埃。Optionally, the thickness of the second doped layer is 8 angstroms to 10 angstroms.

可选的，所述功能层包括分别位于所述第一开口和第二开口底部的栅介质层，以及位于所述栅介质层上的覆盖层；或者所述功能层为位于所述第一开口和第二开口底部的栅介质层。Optionally, the functional layer includes a gate dielectric layer located at the bottom of the first opening and the second opening respectively, and a cover layer located on the gate dielectric layer; or the functional layer is located at the first opening and the gate dielectric layer at the bottom of the second opening.

可选的，所述功能层的材料为HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3或HfSiO4。Optionally, the material of the functional layer is HfO 2 , La 2 O 3 , HfSiON, HfAlO 2 , ZrO 2 , Al 2 O 3 or HfSiO 4 .

可选的，所述退火处理的温度为750℃～900℃，退火时间为10分钟～30分钟。Optionally, the temperature of the annealing treatment is 750°C to 900°C, and the annealing time is 10 minutes to 30 minutes.

可选的，所述功函数层包括氮化钛层。Optionally, the work function layer includes a titanium nitride layer.

可选的，所述功函数层的材料还可以包括氮化钽层或钛铝层，或者氮化钽层和钛铝层形成的叠层结构。Optionally, the material of the work function layer may further include a tantalum nitride layer or a titanium aluminum layer, or a stacked structure formed by a tantalum nitride layer and a titanium aluminum layer.

可选的，所述功函数层的厚度为20埃～40埃。Optionally, the thickness of the work function layer is 20 angstroms to 40 angstroms.

可选的，形成所述栅极之后，所述形成方法还包括：对所述功能层和功函数层进行刻蚀，使所述第一开口和第二开口侧壁的功能层和功函数暴露出部分栅极侧壁。Optionally, after forming the gate, the forming method further includes: etching the functional layer and the work function layer to expose the functional layer and work function on the sidewalls of the first opening and the second opening part of the gate sidewall.

相应的，本发明还提供一种半导体结构，包括：衬底，所述衬底包括第一区域和第二区域，所述第一区域和第二区域衬底上具有介质层，所述第一区域介质层中具有第一开口，所述第二区域介质层中具有第二开口；覆盖所述第一开口和第二开口底部和侧壁的功能层，所述第一开口底部和侧壁的功能层中具有第一功函调节离子，所述第二开口底部和侧壁的功能层中具有第二功函调节离子；位于所述第一开口和第二开口中的功能层上的功函数层；位于所述第一开口和第二开口中的功函数层上的栅极。Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate includes a first region and a second region, the first region and the second region have a dielectric layer on the substrate, and the first region and the second region have a dielectric layer on the substrate. The regional dielectric layer has a first opening, and the second regional dielectric layer has a second opening; a functional layer covering the bottom and sidewalls of the first opening and the second opening, the bottom and sidewalls of the first opening are There are first work function adjusting ions in the functional layer, and second work function adjusting ions are present in the functional layers at the bottom and sidewalls of the second openings; the work function on the functional layers located in the first openings and the second openings layer; a gate on the work function layer in the first opening and the second opening.

可选的，所述功能层的材料为HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3或HfSiO4。Optionally, the material of the functional layer is HfO 2 , La 2 O 3 , HfSiON, HfAlO 2 , ZrO 2 , Al 2 O 3 or HfSiO 4 .

可选的，所述第一区域用于形成NMOS晶体管，所述第一功函调节离子为镁离子；所述第二区域用于形成PMOS晶体管，所述第二功函调节离子为铝离子。Optionally, the first region is used to form an NMOS transistor, and the first work function adjustment ions are magnesium ions; the second region is used to form a PMOS transistor, and the second work function adjustment ions are aluminum ions.

与现有技术相比，本发明的技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:

本发明技术方案提供的半导体结构的形成方法中，形成所述栅极之前，形成所述第一掺杂层和第二掺杂层，并进行退火处理。在所述退火处理过程中，所述第一掺杂层中的第一功函调节离子能够扩散进入所述第一开口底部和侧壁的功能层中，从而能够对所述第一开口中的功能层的功函数进行调节，从而对所形成晶体管的阈值电压进行调节；所述第二掺杂层中的第二功函调节离子能够扩散进入所述第二开口底部和侧壁的功能层中，从而能够对所述第二开口中的功能层的功函数进行调节，进而对所述第二区域形成的晶体管的阈值电压进行调节，从而能够使所述第一区域和第二区域形成的晶体管的阈值电压分别符合不同设计要求。形成栅极之前，所述第一掺杂层和第二掺杂层被去除，且所述第一开口与第二开口中的功能层的厚度相同，从而使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，从而能够保证形成于第一区域和第二区域的晶体管的性能均一，改善所形成的半导体结构的性能。In the method for forming a semiconductor structure provided by the technical solution of the present invention, before forming the gate, the first doped layer and the second doped layer are formed and annealed. During the annealing process, the first work function adjustment ions in the first doping layer can diffuse into the functional layers at the bottom and sidewalls of the first opening, so that the ions in the first opening can be The work function of the functional layer is adjusted, so as to adjust the threshold voltage of the formed transistor; the second work function adjustment ions in the second doping layer can diffuse into the functional layer at the bottom and sidewalls of the second opening , so that the work function of the functional layer in the second opening can be adjusted, and then the threshold voltage of the transistor formed in the second area can be adjusted, so that the transistor formed in the first area and the second area can be adjusted. The threshold voltages of respectively meet different design requirements. Before forming the gate, the first doped layer and the second doped layer are removed, and the thickness of the functional layer in the first opening and the second opening is the same, so that the gate in the first opening has the same thickness The size of the gate in the second opening is the same in the direction parallel to the substrate surface and perpendicular to the substrate surface, so as to ensure uniform performance of the transistors formed in the first region and the second region, and improve the Properties of the formed semiconductor structures.

进一步，形成栅极之前，所述第一掺杂层和第二掺杂层被去除，且所述第一开口与第二开口中的功能层的厚度相同，能够使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，从而在对所述功函数层和功能层进行刻蚀的过程中，所述第一开口与所述第二开口中的栅极在垂直于衬底表面方向上的刻蚀深度相同，从而能够保证第一区域和第二区域形成的晶体管性能的均一性，并能够较容易地对刻蚀过程进行控制。具体的，当使所述第一开口侧壁的功能层和功函数层低于所述第一开口中的栅极顶部表面时，不容易使所述第二开口中的栅极损伤过大；同时，当使所述第二开口侧壁的功能层和功函数层低于所述第二开口中的栅极顶部表面时，不容易使所述第一开口中的栅极损伤过大。因此，所述形成方法能够改善所形成半导体结构的性能。Further, before forming the gate, the first doping layer and the second doping layer are removed, and the thickness of the functional layer in the first opening and the second opening is the same, so that the thickness of the functional layer in the first opening is the same. The gate electrode and the gate electrode in the second opening have the same dimensions in the directions parallel to the substrate surface and perpendicular to the substrate surface, so that in the process of etching the work function layer and the functional layer , the gate electrode in the first opening and the gate in the second opening have the same etching depth in the direction perpendicular to the surface of the substrate, so as to ensure the uniformity of the performance of the transistors formed in the first region and the second region, and can The etching process is easier to control. Specifically, when the functional layer and the work function layer of the sidewall of the first opening are made lower than the top surface of the gate in the first opening, it is not easy to cause excessive damage to the gate in the second opening; Meanwhile, when the functional layer and the work function layer of the sidewalls of the second opening are made lower than the top surface of the gate electrode in the second opening, it is not easy to cause excessive damage to the gate electrode in the first opening. Therefore, the formation method can improve the performance of the formed semiconductor structure.

本发明技术方案提供的半导体结构中，所述第一掺杂层中具有第一功函调节离子，所述第一功函调节离子能够对所述第一开口中的功能层的功函数进行调节，进而对所述第一区域形成的晶体管的阈值电压进行调节；所述第二掺杂层中具有第二功函调节离子，所述第二功函调节离子能够对所述第二开口中的功能层的功函数进行调节，进而对所述第二区域形成的晶体管的阈值电压进行调节，从而能够使所述第一区域和第二区域形成的晶体管的阈值电压符合不同的设计要求。所述第一开口与第二开口中的功能层的厚度相同，从而使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，因此，所述形成方法能够改善所形成的半导体结构的性能。In the semiconductor structure provided by the technical solution of the present invention, the first doped layer has first work function adjustment ions, and the first work function adjustment ions can adjust the work function of the functional layer in the first opening , and then adjust the threshold voltage of the transistor formed in the first region; the second doping layer has second work function adjustment ions, and the second work function adjustment ions can adjust the threshold voltage of the transistor in the second opening. The work function of the functional layer is adjusted, thereby adjusting the threshold voltage of the transistor formed in the second region, so that the threshold voltage of the transistor formed in the first region and the second region can meet different design requirements. The thickness of the functional layer in the first opening and the second opening is the same, so that the gate electrode in the first opening and the gate electrode in the second opening are parallel to the surface of the substrate and perpendicular to the substrate. The dimensions in the direction of the bottom surface are all equal, and thus, the formation method can improve the performance of the formed semiconductor structure.

附图说明Description of drawings

图1至图3是一种半导体结构的形成方法各步骤的结构示意图；1 to 3 are schematic structural diagrams of each step of a method for forming a semiconductor structure;

图4至图12是本发明一实施例中半导体结构的形成方法各步骤的结构示意图。4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

具体实施方式Detailed ways

正如背景技术所述，半导体结构的形成方法形成的半导体结构的性能较差。As described in the background art, semiconductor structures formed by methods of forming semiconductor structures have poor performance.

现结合一种半导体结构的形成方法，分析所形成的半导体结构的性能较差的原因：Now combined with a method for forming a semiconductor structure, the reasons for the poor performance of the formed semiconductor structure are analyzed:

图1至图3是一种半导体结构的形成方法各步骤的结构示意图。FIG. 1 to FIG. 3 are schematic structural diagrams of various steps of a method for forming a semiconductor structure.

请参考图1，提供衬底100，所述衬底100包括第一区域A和第二区域B，所述第一区域A和第二区域B的衬底100上具有介质层110，所述第一区域A介质层110中具有第三开口101，所述第二区域B介质层110中具有第二开口102。Referring to FIG. 1 , a substrate 100 is provided. The substrate 100 includes a first region A and a second region B. The substrate 100 in the first region A and the second region B has a dielectric layer 110 thereon. A region A dielectric layer 110 has a third opening 101 therein, and the second region B dielectric layer 110 has a second opening 102 therein.

继续参考图1，在所述第三开口101和第二开口102的底部和侧壁表面形成栅介质层111；在所述第三开口101中的栅介质层111上形成第一功函数层121，在所述第三开口101中的第一功函数层121和第二开口102中的栅介质层111上形成第二功函数层122。Continuing to refer to FIG. 1 , a gate dielectric layer 111 is formed on the bottom and sidewall surfaces of the third opening 101 and the second opening 102 ; a first work function layer 121 is formed on the gate dielectric layer 111 in the third opening 101 , forming a second work function layer 122 on the first work function layer 121 in the third opening 101 and the gate dielectric layer 111 in the second opening 102 .

请参考图2，形成所述第二功函数层122后，在所述第三开口101和第二开口102中形成栅极130。Referring to FIG. 2 , after the second work function layer 122 is formed, a gate 130 is formed in the third opening 101 and the second opening 102 .

请参考图3，对所述栅介质层111、第一功函数层121和第二功函数层122进行刻蚀，使所述第三开口101(如图1所述)和第二开口102(如图1所示)侧壁上的栅介质层111、第一功函数层121和第二功函数层122暴露出部分所述栅极130侧壁。Referring to FIG. 3 , the gate dielectric layer 111 , the first work function layer 121 and the second work function layer 122 are etched, so that the third opening 101 (as described in FIG. 1 ) and the second opening 102 ( As shown in FIG. 1 ) the gate dielectric layer 111 , the first work function layer 121 and the second work function layer 122 on the sidewalls expose part of the sidewalls of the gate electrode 130 .

后续形成连接所述栅极130的插塞。A plug connecting the gate 130 is subsequently formed.

其中，所述第三开口101中具有栅介质层111、第一功函数层121、第二功函数层122以及所述栅极130，所述第二开口102中具有栅介质层111、第二功函数层122以及所述栅极130。由于所述第三开口101和第二开口102的尺寸相同，则使所述第三开口101中的栅极130与所述第二开口102中的栅极130在垂直于所述栅极130延伸方向上的尺寸不相同。Wherein, the third opening 101 has a gate dielectric layer 111, a first work function layer 121, a second work function layer 122 and the gate 130, and the second opening 102 has a gate dielectric layer 111, a second The work function layer 122 and the gate 130 . Since the sizes of the third opening 101 and the second opening 102 are the same, the gate 130 in the third opening 101 and the gate 130 in the second opening 102 extend perpendicular to the gate 130 The dimensions in the directions are not the same.

具体的，所述第三开口101中的栅极130在垂直于所述栅极130延伸方向上的尺寸小于所述第二开口102中的栅极130。因此，在对所述栅介质层111、第一功函数层121和第二功函数层122进行刻蚀的过程中，所述第三开口101中栅极130沿垂直于衬底表面方向上的刻蚀深度较大，从而所述栅介质层111、第一功函数层121和第二功函数层122不容易暴露出所述第三开口101中的栅极130侧壁；所述第二开口102中栅极130在沿垂直于衬底表面方向上的刻蚀深度较小，从而所述栅介质层111、第一功函数层121和第二功函数层122容易暴露出所述第三开口101中的栅极130侧壁。因此，如果对所述栅介质层111、第一功函数层121和第二功函数层122的刻蚀量较小，不容易使所述第三开口101中的栅极130侧壁暴露出来，从而不利于增加栅极130与插塞的接触面积，降低接触电阻；如果对所述栅介质层111、第一功函数层121和第二功函数层122的刻蚀量较大，容易使所述第二开口102中的栅极130损耗较多，从而增加所述第二开口102中的栅极130的缺陷，降低所形成半导体结构性能。Specifically, the size of the gate 130 in the third opening 101 in a direction perpendicular to the extending direction of the gate 130 is smaller than that of the gate 130 in the second opening 102 . Therefore, in the process of etching the gate dielectric layer 111 , the first work function layer 121 and the second work function layer 122 , the gate electrode 130 in the third opening 101 is along the direction perpendicular to the substrate surface. The etching depth is relatively large, so that the gate dielectric layer 111, the first work function layer 121 and the second work function layer 122 are not easily exposed to the sidewalls of the gate electrode 130 in the third opening 101; the second opening In 102, the etching depth of the gate 130 in the direction perpendicular to the surface of the substrate is small, so that the gate dielectric layer 111, the first work function layer 121 and the second work function layer 122 are easily exposed to the third opening Gate 130 sidewalls in 101. Therefore, if the etching amount of the gate dielectric layer 111, the first work function layer 121 and the second work function layer 122 is small, it is not easy to expose the sidewalls of the gate electrode 130 in the third opening 101, Therefore, it is unfavorable to increase the contact area between the gate 130 and the plug and reduce the contact resistance; if the etching amount of the gate dielectric layer 111, the first work function layer 121 and the second work function layer 122 is large, it is easy to make all the The gate 130 in the second opening 102 has more loss, thereby increasing the defects of the gate 130 in the second opening 102 and reducing the performance of the formed semiconductor structure.

为解决所述技术问题，本发明提供了一种半导体结构的形成方法，包括：提供衬底，所述衬底包括第一区域和第二区域，所述第一区域和第二区域衬底上具有介质层，所述第一区域介质层中具有第一开口，所述第二区域介质层中具有第二开口；分别在所述第一开口和第二开口底部和侧壁形成功能层；在所述第一开口底部和侧壁的功能层上形成第一掺杂层，所述第一掺杂层中具有第一功函调节离子；在所述第二开口底部和侧壁的功能层上形成第二掺杂层，所述第二掺杂层中具有第二功函调节离子；形成所述第一掺杂层和第二掺杂层之后，进行退火处理，使所述第一功函调节离子扩散进入第一开口的功能层中，使第二功函调节离子扩散进入第二开口的功能层中；所述退火处理之后，去除所述第一掺杂层和第二掺杂层；去除所述第一掺杂层和第二掺杂层之后，在所述第一开口和第二开口中的功能层上形成功函数层；形成所述功函数层之后，在所述第一开口和第二开口中形成栅极。In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, and the first region and the second region are on the substrate There is a dielectric layer, the first region dielectric layer has a first opening, and the second region dielectric layer has a second opening; a functional layer is formed on the bottom and sidewall of the first opening and the second opening respectively; A first doped layer is formed on the functional layer at the bottom and sidewalls of the first opening, and the first doped layer has first work function adjusting ions; on the functional layer on the bottom and sidewalls of the second opening forming a second doping layer with second work function adjusting ions in the second doping layer; after forming the first doping layer and the second doping layer, annealing is performed to make the first work function Adjusting ions to diffuse into the functional layer of the first opening, so that the second work function adjusting ions diffuse into the functional layer of the second opening; after the annealing treatment, remove the first doping layer and the second doping layer; After removing the first doping layer and the second doping layer, a work function layer is formed on the functional layer in the first opening and the second opening; after the work function layer is formed, a work function layer is formed on the first opening and a gate is formed in the second opening.

其中，形成所述栅极之前，形成所述第一掺杂层和第二掺杂层，并进行退火处理。在所述退火处理过程中，所述第一掺杂层中的第一功函调节离子能够扩散进入所述第一开口底部和侧壁的功能层中，从而能够对所述第一开口中的功能层的功函数进行调节，从而对所形成晶体管的阈值电压进行调节；所述第二掺杂层中的第二功函调节离子能够扩散进入所述第二开口底部和侧壁的功能层中，从而能够对所述第二开口中的功能层的功函数进行调节，进而对所述第二区域形成的晶体管的阈值电压进行调节，从而能够使所述第一区域和第二区域形成的晶体管的阈值电压分别符合不同设计要求。形成栅极之前，所述第一掺杂层和第二掺杂层被去除，且所述第一开口与第二开口中的功能层的厚度相同，从而使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，从而能够保证形成于第一区域和第二区域的晶体管的性能均一，改善所形成的半导体结构的性能。Wherein, before forming the gate, the first doped layer and the second doped layer are formed and annealed. During the annealing process, the first work function adjustment ions in the first doping layer can diffuse into the functional layers at the bottom and sidewalls of the first opening, so that the ions in the first opening can be The work function of the functional layer is adjusted, so as to adjust the threshold voltage of the formed transistor; the second work function adjustment ions in the second doping layer can diffuse into the functional layer at the bottom and sidewalls of the second opening , so that the work function of the functional layer in the second opening can be adjusted, and then the threshold voltage of the transistor formed in the second area can be adjusted, so that the transistor formed in the first area and the second area can be adjusted. The threshold voltages of respectively meet different design requirements. Before forming the gate, the first doped layer and the second doped layer are removed, and the thickness of the functional layer in the first opening and the second opening is the same, so that the gate in the first opening has the same thickness The size of the gate in the second opening is the same in the direction parallel to the substrate surface and perpendicular to the substrate surface, so as to ensure uniform performance of the transistors formed in the first region and the second region, and improve the Properties of the formed semiconductor structures.

为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

图4至图12是本发明一实施例中半导体结构的形成方法各步骤的结构示意图。4 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

请参考图4，提供衬底200，所述衬底200包括第一区域I和第二区域II，所述第一区域I和第二区域II衬底200上具有介质层210，所述第一区域I介质层210中具有第一开口201，所述第二区域II介质层210中具有第二开口202。Referring to FIG. 4 , a substrate 200 is provided. The substrate 200 includes a first region I and a second region II. The first region I and the second region II have a dielectric layer 210 on the substrate 200 . The first region I and the second region II The region I dielectric layer 210 has a first opening 201 therein, and the second region II dielectric layer 210 has a second opening 202 therein.

所述第一区域I用于形成NMOS晶体管，所述第二区域II用于形成PMOS晶体管。在其他实施例中，所述第一区域还可以用于形成NMOS晶体管，所述第二区域还可以用于形成PMOS晶体管。The first region I is used to form NMOS transistors, and the second region II is used to form PMOS transistors. In other embodiments, the first region can also be used to form NMOS transistors, and the second region can also be used to form PMOS transistors.

所述介质层210用于实现后续形成的栅极之间的电绝缘。所述第一开口201和第二开口202用于后续容纳栅极。The dielectric layer 210 is used to achieve electrical insulation between gates formed subsequently. The first opening 201 and the second opening 202 are used to accommodate the gate subsequently.

本实施例中，所述衬底200为硅衬底、锗衬底、硅锗衬底、绝缘体上硅、绝缘体上锗或绝缘体上硅锗等半导体衬底。In this embodiment, the substrate 200 is a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, silicon-on-insulator, germanium-on-insulator, or silicon-germanium-on-insulator.

本实施例中，形成所述介质层210、第一开口201和第二开口202的步骤包括：在所述第一区域I衬底200上形成第一伪栅极结构；在所述第二区域II衬底200上形成第二伪栅极结构；在所述衬底200上形成介质层210，所述介质层210覆盖所述第一伪栅极结构和第二伪栅极结构侧壁；去除所述第一伪栅极结构，在所述第一区域I介质层210中形成第一开口201；去除所述第二伪栅极结构，在所述第二区域II介质层210中形成第二开口202。In this embodiment, the steps of forming the dielectric layer 210, the first opening 201 and the second opening 202 include: forming a first dummy gate structure on the substrate 200 in the first region I; II forming a second dummy gate structure on the substrate 200; forming a dielectric layer 210 on the substrate 200, the dielectric layer 210 covering the sidewalls of the first dummy gate structure and the second dummy gate structure; removing For the first dummy gate structure, a first opening 201 is formed in the dielectric layer 210 in the first region I; Opening 202 .

本实施例中，所述介质层210的材料为氧化硅。In this embodiment, the material of the dielectric layer 210 is silicon oxide.

本实施例中，所述衬底200中具有隔离结构203，所述隔离结构203用于隔离所述第一区域I和第二区域II。In this embodiment, the substrate 200 has an isolation structure 203, and the isolation structure 203 is used to isolate the first region I and the second region II.

本实施例中，所述隔离结构203的材料为氧化硅。In this embodiment, the material of the isolation structure 203 is silicon oxide.

请参考图5，分别在所述第一开口201和第二开口202底部和侧壁形成功能层211。Referring to FIG. 5 , a functional layer 211 is formed on the bottom and sidewalls of the first opening 201 and the second opening 202 , respectively.

所述功能层211用于后续容纳第一功函调节离子和第二功函调节离子，从而对所形成晶体管的阈值电压进行调节。The functional layer 211 is used to subsequently accommodate the first work function adjusting ions and the second work function adjusting ions, so as to adjust the threshold voltage of the formed transistor.

通过后续对所述功能层进行掺杂，从而实现对所形成NMOS晶体管和PMOS晶体管的阈值电压的调节。具体的，本实施例中，通过对所述功能层211进行掺杂降低所形成NMOS晶体管和PMOS晶体管的阈值电压。在其他实施例中，还可以增加NMOS晶体管或PMOS晶体管的阈值电压。By subsequently doping the functional layer, the threshold voltages of the formed NMOS transistors and PMOS transistors can be adjusted. Specifically, in this embodiment, the threshold voltages of the formed NMOS transistors and PMOS transistors are reduced by doping the functional layer 211 . In other embodiments, the threshold voltage of NMOS transistors or PMOS transistors may also be increased.

此外，本实施例中，所述功能层211为所形成晶体管的栅介质层。所述功能层211用做所形成晶体管的栅介质层，能够简化工艺流程。在其他实施例中，所述功能层层可以包括所述第一开口底部和第二开口底部的栅介质层和位于所述栅介质层上的覆盖层。所述覆盖层的材料为氮化钛或氮化钽。或者，所述功能层仅包括覆盖层。In addition, in this embodiment, the functional layer 211 is the gate dielectric layer of the formed transistor. The functional layer 211 is used as the gate dielectric layer of the formed transistor, which can simplify the process flow. In other embodiments, the functional layer may include a gate dielectric layer at the bottom of the first opening and the bottom of the second opening and a capping layer on the gate dielectric layer. The material of the covering layer is titanium nitride or tantalum nitride. Alternatively, the functional layer includes only the cover layer.

本实施例中，所述功能层211的材料为高k(k大于3.9)介质材料，例如HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3或HfSiO4。In this embodiment, the material of the functional layer 211 is a high-k (k greater than 3.9) dielectric material, such as HfO 2 , La 2 O 3 , HfSiON, HfAlO 2 , ZrO 2 , Al 2 O 3 or HfSiO 4 .

本实施例中，形成所述功能层211的工艺包括化学气相沉积工艺。In this embodiment, the process of forming the functional layer 211 includes a chemical vapor deposition process.

本实施例中，所述功能层211的厚度为18埃～22埃。In this embodiment, the thickness of the functional layer 211 is 18 angstroms to 22 angstroms.

请参考图6，在所述第一开口201底部和侧壁的功能层211表面形成第一掺杂层221，所述第一掺杂层221中具有第一功函调节离子。Referring to FIG. 6 , a first doping layer 221 is formed on the surface of the functional layer 211 at the bottom and sidewalls of the first opening 201 , and the first doping layer 221 has first work function adjusting ions therein.

所述第一掺杂层221用于对所述功能层211进行掺杂，在所述功能层211中掺入第一功函调节离子，从而调节所述第一区域I功能层211的功函数，进而对所形成NMOS晶体管的阈值电压进行调节。The first doping layer 221 is used for doping the functional layer 211, and doping the first work function adjusting ions into the functional layer 211, so as to adjust the work function of the functional layer 211 in the first region I , and then adjust the threshold voltage of the formed NMOS transistor.

本实施例中，形成所述第一掺杂层221的步骤包括：在所述第一区域I和第二区域II的功能层211上形成第一初始掺杂层；去除所述第二区域II的第一初始掺杂层，形成第一掺杂层221。In this embodiment, the step of forming the first doping layer 221 includes: forming a first initial doping layer on the functional layers 211 of the first region I and the second region II; removing the second region II The first initial doping layer is formed to form the first doping layer 221 .

本实施例中，所述第一掺杂层221的材料为氮化钛或氮化钽。In this embodiment, the material of the first doping layer 221 is titanium nitride or tantalum nitride.

本实施例中，所述第一功函调节离子为镁离子。后续在所述功能层211中掺入镁离子能够增加所述功能层211的功函数，从而减小所形成的NMOS晶体管的栅极与栅介质层费米能级之差，从而降低所形成NMOS晶体管的阈值电压。In this embodiment, the first work function adjusting ions are magnesium ions. Subsequent doping of magnesium ions into the functional layer 211 can increase the work function of the functional layer 211, thereby reducing the Fermi level difference between the gate of the formed NMOS transistor and the gate dielectric layer, thereby reducing the formed NMOS Threshold voltage of the transistor.

如果所述第一掺杂层221中的第一功函调节离子的浓度过高，后续退火处理过程中，容易使所述第一区域I功能层211中的第一功函调节离子的浓度过高，从而使第一区域I功能层211的功函数过大，不利于降低后续形成于第一开口中的栅极与第一区域I功能层211的费米能级之差，不利于降低所形成NMOS晶体管的阈值电压；如果所述第一掺杂层221中的第一功函调节离子的浓度过低，后续退火处理过程中，容易使所述第一区域I功能层211中的第一功函调节离子的浓度过低，从而不利于增加第一区域I功能层211的功函数，也不利于降低后续形成于第一开口201中的栅极与第一区域I功能层211的费米能级之差。具体的，本实施例中，所述第一掺杂层221中的第一功函调节离子的浓度为4E14 atoms/cm2～6E14 atoms/cm2。If the concentration of the first work function adjusting ions in the first doped layer 221 is too high, in the subsequent annealing process, the concentration of the first work function adjusting ions in the first region I functional layer 211 is likely to be excessively high. Therefore, the work function of the first region I functional layer 211 is too large, which is not conducive to reducing the difference between the Fermi level between the gate electrode formed in the first opening and the first region I functional layer 211, and is not conducive to reducing all the The threshold voltage of the NMOS transistor is formed; if the concentration of the first work function adjusting ions in the first doping layer 221 is too low, in the subsequent annealing process, it is easy to make the first region I functional layer 211 in the first region. The concentration of work function adjusting ions is too low, which is not conducive to increasing the work function of the first region I functional layer 211, and is also not conducive to reducing the Fermi between the gate and the first region I functional layer 211 formed in the first opening 201 subsequently. difference in energy levels. Specifically, in this embodiment, the concentration of the first work function adjusting ions in the first doping layer 221 is 4E14 atoms/cm 2 -6E14 atoms/cm 2 .

如果所述第一掺杂层221的厚度过大，容易给后续的去除工艺带来困难，如果所述第一掺杂层221的厚度过小，容易使所述第一掺杂层221中第一功函调节离子的量过小，在后续的退火处理过程中，不容易在所述功能层211中掺入第一功函调节离子。具体的，所述第一掺杂层221的厚度为8埃～10埃。If the thickness of the first doping layer 221 is too large, it is easy to bring difficulties to the subsequent removal process. If the thickness of the first doping layer 221 is too small, it is easy to make the first doping layer 221 The amount of one work function adjusting ion is too small, and it is not easy to incorporate the first work function adjusting ion into the functional layer 211 in the subsequent annealing process. Specifically, the thickness of the first doped layer 221 is 8 angstroms to 10 angstroms.

请参考图7，在所述第二开口202底部和侧壁的功能层211上形成第二掺杂层222，所述第二掺杂层222中具有第二功函调节离子。Referring to FIG. 7 , a second doping layer 222 is formed on the functional layer 211 at the bottom and sidewalls of the second opening 202 , and the second doping layer 222 has second work function adjusting ions therein.

所述第二掺杂层222用于对所述第二开口202底部和侧壁的功能层211进行掺杂，在所述第二开口202底部和侧壁的功能层211中掺入第二功函调节离子，从而调节所述第二区域II功能层211的功函数，从而减小所形成的PMOS晶体管的栅极与功能层费米能级之差，进而对所形成的PMOS晶体管的阈值电压进行调节。The second doping layer 222 is used for doping the functional layer 211 on the bottom and sidewalls of the second opening 202 , and a second functional layer is doped into the functional layer 211 on the bottom and sidewalls of the second opening 202 . adjust the ions, so as to adjust the work function of the second region II functional layer 211, thereby reducing the difference between the gate of the formed PMOS transistor and the Fermi level of the functional layer, which in turn affects the threshold voltage of the formed PMOS transistor. Make adjustments.

本实施例中，所述第二掺杂层222还位于所述第一掺杂层221上。在其他实施例中，所述第二掺杂层还可以仅位于所述第二区域。In this embodiment, the second doping layer 222 is also located on the first doping layer 221 . In other embodiments, the second doping layer may also be located only in the second region.

本实施例中，所述第二掺杂层222的材料为氧化铝。在其他实施例中，所述第二掺杂层的材料还可以为掺有铝离子的氮化钛或氮化钽。In this embodiment, the material of the second doping layer 222 is aluminum oxide. In other embodiments, the material of the second doping layer may also be titanium nitride or tantalum nitride doped with aluminum ions.

本实施例中，所述第二功函调节离子为铝离子。所述第二掺杂层222用于后续在所述功能层211中掺入铝离子，增加所述功能层211的功函数，从而降低功能层211与后续形成于所述第二开口202中的栅极费米能级之差，进而降低所形成PMOS晶体管的阈值电压。In this embodiment, the second work function adjusting ions are aluminum ions. The second doping layer 222 is used for subsequently doping aluminum ions into the functional layer 211 to increase the work function of the functional layer 211 , thereby reducing the amount of ions between the functional layer 211 and the second opening 202 . The gate Fermi level difference, which in turn lowers the threshold voltage of the resulting PMOS transistor.

需要说明的是，本实施例中，所述第二掺杂层222为氧化铝，氧化铝中具有铝离子，从而不需要对所述第二掺杂层222进行掺杂。在其他实施例中，所述第二掺杂层的材料可以为氮化钛或氮化钽，形成所述第二掺杂层时需要在第二掺杂层中掺入第二功函调节离子。It should be noted that, in this embodiment, the second doping layer 222 is aluminum oxide, and aluminum oxide contains aluminum ions, so that the second doping layer 222 does not need to be doped. In other embodiments, the material of the second doping layer may be titanium nitride or tantalum nitride, and a second work function adjusting ion needs to be doped into the second doping layer when forming the second doping layer .

如果所述第二掺杂层222的厚度过大，容易给后续的去除工艺带来困难，如果所述第二掺杂层222的厚度过小，容易使所述第二掺杂层222中第二功函调节离子的量过小，在后续的退火处理过程中，不容易在所述第二区域II功能层211中掺入第二功函调节离子。具体的，所述第二掺杂层222的厚度为8埃～10埃。If the thickness of the second doping layer 222 is too large, it is easy to bring difficulties to the subsequent removal process. If the thickness of the second doping layer 222 is too small, it is easy to make the second doping layer 222 The amount of the two work function adjusting ions is too small, and it is not easy to incorporate the second work function adjusting ions into the second region II functional layer 211 during the subsequent annealing process. Specifically, the thickness of the second doping layer 222 is 8 angstroms to 10 angstroms.

请参考图8，形成所述第一掺杂层221和第二掺杂层222之后，进行退火处理，使所述第一功函调节离子扩散进入所述第一开口201的功能层211中，使所述第二功函调节离子扩散进入所述第二开口202中的功能层211中。Referring to FIG. 8 , after forming the first doping layer 221 and the second doping layer 222 , annealing is performed to diffuse the first work function adjusting ions into the functional layer 211 of the first opening 201 . The second work function adjusting ions are diffused into the functional layer 211 in the second opening 202 .

所述退火处理用于使所述第一功函调节离子和第二功函调节离子扩散进入所述功能层211中。The annealing treatment is used for diffusing the first work function adjusting ions and the second work function adjusting ions into the functional layer 211 .

所述退火处理的过程中，所述第一掺杂层221中的第一功函调节离子能够扩散进入所述第一开口201底部和侧壁的功能层211中，从而能够对所述第一开口201中的功能层211的功函数进行调节，进而对所述第一区域I形成的NMOS晶体管的阈值电压进行调节；所述第二掺杂层222中的第二功函调节离子能够扩散进入所述第二开口202底部和侧壁的功能层211中，从而能够对所述第二开口202中的功能层211的功函数进行调节，进而对所述第二区域II形成的晶体管的阈值电压进行调节，从而能够使所述第一区域I和第二区域II形成的晶体管的阈值电压符合不同的设计要求。During the annealing process, the first work function adjusting ions in the first doping layer 221 can diffuse into the functional layer 211 at the bottom and sidewalls of the first opening 201, so that the first work function adjustment ions can be The work function of the functional layer 211 in the opening 201 is adjusted, thereby adjusting the threshold voltage of the NMOS transistor formed in the first region I; the second work function adjustment ions in the second doping layer 222 can diffuse into the In the functional layer 211 at the bottom and sidewalls of the second opening 202, the work function of the functional layer 211 in the second opening 202 can be adjusted, thereby adjusting the threshold voltage of the transistor formed in the second region II By adjusting, the threshold voltages of the transistors formed in the first region I and the second region II can meet different design requirements.

需要说明的是，本实施例中，所述第一开口201底部和侧壁的第一掺杂层221上也具有所述第二掺杂层222，因此，在所述退火处理的过程中，所述第二掺杂层222中的第二功函调节离子会进入所述第一开口201底部和侧壁的功能层211中，对所形成NMOS晶体管的阈值电压进行调节。It should be noted that, in this embodiment, the second doped layer 222 is also provided on the first doped layer 221 at the bottom and sidewall of the first opening 201 . Therefore, during the annealing process, The second work function adjusting ions in the second doping layer 222 enter into the functional layer 211 at the bottom and sidewalls of the first opening 201 to adjust the threshold voltage of the formed NMOS transistor.

如果退火温度过低，退火时间过短，不利于所述第一功函调节离子和第二功函调节离子的扩散，从而容易使所述功能层211中第一功函调节离子和第二功函调节离子的浓度过低，不利于增加所述功能层211的功函数；如果退火温度过高，退火时间过长，容易使第一功函调节离子和第二功函调节离子的浓度过高，所述功能层211的功函数过大，也容易增加功能层211与后续形成的栅极的费米能级之差。具体的，本实施例中，所述退火处理的温度为750℃～900℃，退火时间为10分钟～30分钟。If the annealing temperature is too low and the annealing time is too short, it is not conducive to the diffusion of the first work function adjusting ions and the second work function adjusting ions, so it is easy to make the first work function adjusting ions and the second work function adjusting ions in the functional layer 211 . If the concentration of the function regulating ions is too low, it is not conducive to increase the work function of the functional layer 211; if the annealing temperature is too high and the annealing time is too long, it is easy to make the concentrations of the first work function regulating ions and the second work function regulating ions too high , the work function of the functional layer 211 is too large, and it is easy to increase the difference between the Fermi levels of the functional layer 211 and the gate electrode formed subsequently. Specifically, in this embodiment, the temperature of the annealing treatment is 750° C.˜900° C., and the annealing time is 10 minutes˜30 minutes.

请参考图9，所述退火处理之后，去除所述第一掺杂层221(如图8所示)和第二掺杂层222(如图8所示)。Referring to FIG. 9 , after the annealing process, the first doping layer 221 (shown in FIG. 8 ) and the second doping layer 222 (shown in FIG. 8 ) are removed.

本实施例中，去除所述第一掺杂层221和第二掺杂层222的工艺包括干法刻蚀或湿法刻蚀工艺。In this embodiment, the process of removing the first doping layer 221 and the second doping layer 222 includes a dry etching process or a wet etching process.

请参考图10，去除所述第一掺杂层221和第二掺杂层222之后，在所述第一开口201和第二开口202中的功能层211上形成功函数层230。Referring to FIG. 10 , after the first doping layer 221 and the second doping layer 222 are removed, a work function layer 230 is formed on the functional layer 211 in the first opening 201 and the second opening 202 .

所述功函数层230用于调节所形成的NMOS晶体管和PMOS晶体管的阈值电压，使所形成的NMOS晶体管和PMOS晶体管的阈值电压符合设计要求。The work function layer 230 is used to adjust the threshold voltages of the formed NMOS transistors and the PMOS transistors, so that the formed threshold voltages of the NMOS transistors and the PMOS transistors meet design requirements.

本实施例中，所述功函数层230包括氮化钛层。在其他实施例中，所述功函数层还可以包括氮化钽层或钛铝层，或者氮化钽层和钛铝层形成的叠层结构。In this embodiment, the work function layer 230 includes a titanium nitride layer. In other embodiments, the work function layer may further include a tantalum nitride layer or a titanium aluminum layer, or a stacked structure formed by a tantalum nitride layer and a titanium aluminum layer.

本实施例中，形成所述功函数层230的工艺包括化学气相沉积工艺。In this embodiment, the process of forming the work function layer 230 includes a chemical vapor deposition process.

本实施例中，所述功函数层230的厚度为20埃～40埃。In this embodiment, the thickness of the work function layer 230 is 20 angstroms to 40 angstroms.

请参考图11，形成所述功函数层230之后，在所述第一开口201(如图10所示)和第二开口202(如图10所示)中形成栅极240。Referring to FIG. 11 , after the work function layer 230 is formed, a gate electrode 240 is formed in the first opening 201 (as shown in FIG. 10 ) and the second opening 202 (as shown in FIG. 10 ).

本实施例中，所述栅极240的材料为金属，例如钨。In this embodiment, the material of the gate 240 is metal, such as tungsten.

本实施例中，形成所述栅极240的步骤包括：在所述第一开口201和第二开口202中以及所述介质层210上形成金属层；对所述金属层进行平坦化处理，去除所述介质层210上的金属层，形成栅极240。In this embodiment, the step of forming the gate 240 includes: forming a metal layer in the first opening 201 and the second opening 202 and on the dielectric layer 210; performing a planarization process on the metal layer, and removing the The metal layer on the dielectric layer 210 forms the gate electrode 240 .

本实施例中，形成所述金属层的工艺包括：化学气相沉积工艺。In this embodiment, the process of forming the metal layer includes: a chemical vapor deposition process.

本实施例中，所述平坦化处理的工艺包括化学机械研磨。In this embodiment, the planarization process includes chemical mechanical polishing.

本实施例中，去除所述介质层210上的金属层之后，还包括：去除所述介质层210上的功能层211和功函数层230。In this embodiment, after removing the metal layer on the dielectric layer 210 , the method further includes: removing the functional layer 211 and the work function layer 230 on the dielectric layer 210 .

请参考图12，对所述第一开口201(如图10所示)和第二开口202(如图10所示)侧壁的功能层211和功函数层230进行刻蚀，暴露出部分栅极240侧壁。Referring to FIG. 12 , the functional layer 211 and the work function layer 230 on the sidewalls of the first opening 201 (as shown in FIG. 10 ) and the second opening 202 (as shown in FIG. 10 ) are etched to expose part of the gate Pole 240 sidewall.

使所述功能层211和功函数层230暴露出部分栅极240侧壁能够增加后续形成的插塞与栅极240的接触面积，从而减小插塞与栅极240之间的接触电阻。Exposing part of the sidewall of the gate 240 from the functional layer 211 and the work function layer 230 can increase the contact area between the plug and the gate 240 formed subsequently, thereby reducing the contact resistance between the plug and the gate 240 .

本实施例中，对所述第一开口201和第二开口202侧壁的功能层211和功函数层230进行刻蚀的工艺包括干法刻蚀工艺。In this embodiment, the process of etching the functional layer 211 and the work function layer 230 on the sidewalls of the first opening 201 and the second opening 202 includes a dry etching process.

综上，本发明实施例提供的半导体结构的形成方法中，形成所述栅极之前，形成所述第一掺杂层和第二掺杂层，并进行退火处理。在所述退火处理过程中，所述第一掺杂层中的第一功函调节离子能够扩散进入所述第一开口底部和侧壁的功能层中，从而能够对所述第一开口中的功能层的功函数进行调节，从而对所形成晶体管的阈值电压进行调节；所述第二掺杂层中的第二功函调节离子能够扩散进入所述第二开口底部和侧壁的功能层中，从而能够对所述第二开口中的功能层的功函数进行调节，进而对所述第二区域形成的晶体管的阈值电压进行调节，从而能够使所述第一区域和第二区域形成的晶体管的阈值电压分别符合不同设计要求。形成栅极之前，所述第一掺杂层和第二掺杂层被去除，且所述第一开口与第二开口中的功能层的厚度相同，从而使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，从而能够保证形成于第一区域和第二区域的晶体管的性能均一，改善所形成的半导体结构的性能。To sum up, in the method for forming a semiconductor structure provided by the embodiment of the present invention, before forming the gate, the first doped layer and the second doped layer are formed and annealed. During the annealing process, the first work function adjustment ions in the first doping layer can diffuse into the functional layers at the bottom and sidewalls of the first opening, so that the ions in the first opening can be The work function of the functional layer is adjusted, so as to adjust the threshold voltage of the formed transistor; the second work function adjustment ions in the second doping layer can diffuse into the functional layer at the bottom and sidewalls of the second opening , so that the work function of the functional layer in the second opening can be adjusted, and then the threshold voltage of the transistor formed in the second area can be adjusted, so that the transistor formed in the first area and the second area can be adjusted. The threshold voltages of respectively meet different design requirements. Before forming the gate, the first doped layer and the second doped layer are removed, and the thickness of the functional layer in the first opening and the second opening is the same, so that the gate in the first opening has the same thickness The size of the gate in the second opening is the same in the direction parallel to the substrate surface and perpendicular to the substrate surface, so as to ensure uniform performance of the transistors formed in the first region and the second region, and improve the Properties of the formed semiconductor structures.

进一步，形成栅极之前，所述第一掺杂层和第二掺杂层被去除，且所述第一开口与第二开口中的功能层的厚度相同，能够使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，从而在对所述功函数层和功能层进行刻蚀的过程中，所述第一开口与所述第二开口中的栅极在垂直于衬底表面方向上的刻蚀深度相同，从而能够保证第一区域和第二区域形成的晶体管性能的均一性，并能够较容易地对刻蚀过程进行控制。具体的，当使所述第一开口侧壁的功能层和功函数层低于所述第一开口中的栅极顶部表面时，不容易使所述第二开口中的栅极损伤过大；同时，当使所述第二开口侧壁的功能层和功函数层低于所述第二开口中的栅极顶部表面时，不容易使所述第一开口中的栅极损伤过大。因此，所述形成方法能够改善所形成半导体结构的性能。Further, before forming the gate, the first doping layer and the second doping layer are removed, and the thickness of the functional layer in the first opening and the second opening is the same, so that the thickness of the functional layer in the first opening is the same. The gate electrode and the gate electrode in the second opening have the same dimensions in the directions parallel to the substrate surface and perpendicular to the substrate surface, so that in the process of etching the work function layer and the functional layer , the gate electrode in the first opening and the gate in the second opening have the same etching depth in the direction perpendicular to the surface of the substrate, so as to ensure the uniformity of the performance of the transistors formed in the first region and the second region, and can The etching process is easier to control. Specifically, when the functional layer and the work function layer of the sidewall of the first opening are made lower than the top surface of the gate in the first opening, it is not easy to cause excessive damage to the gate in the second opening; Meanwhile, when the functional layer and the work function layer of the sidewalls of the second opening are made lower than the top surface of the gate electrode in the second opening, it is not easy to cause excessive damage to the gate electrode in the first opening. Therefore, the formation method can improve the performance of the formed semiconductor structure.

继续参考图12，本发明的实施例还提供一种半导体结构，包括：衬底200，所述衬底200包括第一区域I和第二区域II，所述第一区域I和第二区域II衬底200上具有介质层210，所述第一区域I介质层210中具有第一开口，所述第二区域II介质层210中具有第二开口；覆盖所述第一开口和第二开口底部和侧壁的功能层211，所述第一开口底部和侧壁的功能层211中具有第一功函调节离子，所述第二开口底部和侧壁的功能层211中具有第二功函调节离子；位于所述第一开口和第二开口中的功能层211上的功函数层230；位于所述第一开口和第二开口中的功函数层230上的栅极240。Continuing to refer to FIG. 12 , an embodiment of the present invention further provides a semiconductor structure, including: a substrate 200 , the substrate 200 includes a first region I and a second region II, the first region I and the second region II The substrate 200 has a dielectric layer 210, the first region I dielectric layer 210 has a first opening, and the second region II dielectric layer 210 has a second opening; covering the first opening and the bottom of the second opening and the functional layer 211 of the sidewall, the functional layer 211 at the bottom and sidewall of the first opening has a first work function adjustment ion, and the functional layer 211 at the bottom and sidewall of the second opening has a second work function adjustment ion ions; the work function layer 230 located on the functional layer 211 in the first opening and the second opening; the gate electrode 240 located on the work function layer 230 in the first opening and the second opening.

本实施例中，所述功能层的材料为HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3或HfSiO4。In this embodiment, the material of the functional layer is HfO 2 , La 2 O 3 , HfSiON, HfAlO 2 , ZrO 2 , Al 2 O 3 or HfSiO 4 .

本实施例中，所述第一区域I用于形成NMOS晶体管，所述第一功函调节离子为镁离子；所述第二区域II用于形成PMOS晶体管，所述第二功函调节离子为铝离子。In this embodiment, the first region I is used to form an NMOS transistor, and the first work function adjustment ions are magnesium ions; the second region II is used to form a PMOS transistor, and the second work function adjustment ions are aluminum ions.

综上，本实施例提供的半导体结构中，所述第一掺杂层中具有第一功函调节离子，所述第一功函调节离子能够对所述第一开口中的功能层的功函数进行调节，进而对所述第一区域形成的晶体管的阈值电压进行调节；所述第二掺杂层中具有第二功函调节离子，所述第二功函调节离子能够对所述第二开口中的功能层的功函数进行调节，进而对所述第二区域形成的晶体管的阈值电压进行调节，从而能够使所述第一区域和第二区域形成的晶体管的阈值电压符合不同的设计要求。所述第一开口与第二开口中的功能层的厚度相同，从而使所述第一开口中的栅极和第二开口中的栅极在平行于所述衬底表面和垂直于所述衬底表面方向上的尺寸均相等，因此，所述形成方法能够改善所形成的半导体结构的性能。To sum up, in the semiconductor structure provided in this embodiment, the first doping layer has first work function adjusting ions, and the first work function adjusting ions can adjust the work function of the functional layer in the first opening. performing adjustment, thereby adjusting the threshold voltage of the transistor formed in the first region; the second doping layer has second work function adjusting ions, and the second work function adjusting ions can adjust the second opening The work function of the functional layer in the device is adjusted, thereby adjusting the threshold voltage of the transistor formed in the second region, so that the threshold voltage of the transistor formed in the first region and the second region can meet different design requirements. The thickness of the functional layer in the first opening and the second opening is the same, so that the gate electrode in the first opening and the gate electrode in the second opening are parallel to the surface of the substrate and perpendicular to the substrate. The dimensions in the direction of the bottom surface are all equal, and thus, the formation method can improve the performance of the formed semiconductor structure.

虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, a dielectric layer is arranged on the first area and the second area, a first opening is formed in the dielectric layer of the first area, and a second opening is formed in the dielectric layer of the second area;
forming functional layers on the bottoms and the side walls of the first opening and the second opening respectively;
forming a first doping layer on the functional layer at the bottom and on the side wall of the first opening, wherein the first doping layer is provided with first work function adjusting ions;
forming a second doping layer on the functional layer at the bottom and on the side wall of the second opening, wherein the second doping layer is provided with second work function adjusting ions;
after the first doping layer and the second doping layer are formed, annealing treatment is carried out, so that the first work function adjusting ions are diffused into the functional layer of the first opening, and the second work function adjusting ions are diffused into the functional layer of the second opening;
after the annealing treatment, removing the first doping layer and the second doping layer;
after removing the first doping layer and the second doping layer, forming a work function layer on the functional layer in the first opening and the second opening;
after the work function layer is formed, forming a grid electrode in the first opening and the second opening, and enabling the size of the grid electrode in the first opening and the size of the grid electrode in the second opening in the direction parallel to the surface of the substrate to be equal to that of the grid electrode in the second opening in the direction perpendicular to the surface of the substrate;
after forming the gate, the forming method further includes: and etching the functional layer and the work function layer to enable the functional layer and the work function layer on the side walls of the first opening and the second opening to expose partial side walls of the grid electrode.
2. The method of forming a semiconductor structure according to claim 1, wherein the second doped layer is formed after the first doped layer is formed.
3. The method of forming a semiconductor structure of claim 2, wherein the second doped layer is further located on the first doped layer.
4. The method of forming a semiconductor structure according to claim 1, wherein the first doped layer is formed after the second doped layer is formed.
5. The method of claim 1, wherein the first region is used to form an NMOS transistor, and wherein the first work function adjusting ions are magnesium ions.
6. The method according to claim 5, wherein a material of the first doped layer is TaN or TiN.
7. The method of forming a semiconductor structure according to claim 6, wherein a thickness of the first doped layer is 8 to 10 angstroms; the concentration of the first work function adjusting ions in the first doping layer is 4E14atoms/cm2～6E14atoms/cm2。
8. The method of claim 1, wherein the second region is used to form a PMOS transistor, and wherein the second work function adjusting ions are aluminum ions.
9. The method of claim 8, wherein a material of the second doped layer is aluminum oxide, titanium nitride, or tantalum nitride.
10. The method of forming a semiconductor structure according to claim 9, wherein a thickness of the second doped layer is 8 a to 10 a.
11. The method of claim 1, wherein the functional layer comprises a gate dielectric layer at the bottom of the first opening and the second opening, respectively, and a capping layer on the gate dielectric layer; or the functional layer is a gate dielectric layer positioned at the bottoms of the first opening and the second opening.
12. The method of forming a semiconductor structure of claim 1, wherein the functional layer is formed of a material that is HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
13. The method of claim 1, wherein the annealing is performed at a temperature of 750 ℃ to 900 ℃ for a time of 10 minutes to 30 minutes.
14. The method of forming a semiconductor structure of claim 1, wherein the work function layer comprises a titanium nitride layer.
15. The method of claim 14, wherein the material of the work function layer further comprises a tantalum nitride layer or a titanium aluminum layer, or a stacked structure of a tantalum nitride layer and a titanium aluminum layer.
16. The method of forming a semiconductor structure of claim 14, wherein the work function layer has a thickness of 20 to 40 angstroms.
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