CN108573881A - A kind of semiconductor device and its manufacturing method and electronic device - Google Patents

Abstract

The present invention provides a kind of semiconductor devices and its manufacturing method and electronic devices.The method includes：The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, and alignment mark and the image sensor element positioned at the alignment mark side are formed in the first surface；There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；The second surface of first wafer is thinned to exposing the alignment mark.The method forms readily identified alignment mark, can further increase the performance and yield of the semiconductor devices in the case where ensureing to be bonded quality.

Description

A kind of semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

Generally, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors include Charge Coupled Devices (CCD) and Complementary Metal Oxide Semiconductor (CMOS) image sensors.

Since CMOS image sensors (CMOS image sensors, CIS) have improved manufacturing technologies and characteristics, various aspects of semiconductor manufacturing technologies are focused on developing CMOS image sensors. CMOS image sensors are manufactured using CMOS technology, and have lower power consumption, are easier to achieve high integration, and produce smaller devices. Therefore, CMOS image sensors are widely used in various products, such as digital cameras and digital video cameras.

3D CIS's enhanced imaging integration makes it uniquely positioned in the image sensor market. The back-illuminated 3D CIS with Cu-Cu bonding is usually used. Due to the special bonding process, the alignment mark area used for backside lithography is usually not bonded, resulting in the risk of silicon burst. The method of increasing Cu bonding dummy patterns will form interference patterns, which will greatly affect the quality of alignment marks.

Therefore, it is necessary to propose a method for manufacturing a semiconductor device to solve the above technical problems.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

Aiming at the deficiencies in the prior art, the invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a first wafer, the first wafer comprising a first surface and a second surface oppositely disposed, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed in the first surface;

providing a second wafer, and bonding the first surface of the first wafer to the second wafer;

Thinning the second surface of the first wafer to expose the alignment marks.

Optionally, the bonding method includes:

forming a dielectric layer on the alignment mark and the pattern sensor element, forming a plurality of protruding first metal pillars spaced apart from each other in the dielectric layer;

providing a second wafer, on which a plurality of second metal pillars spaced apart from each other are formed;

Bonding the first metal post and the second metal post.

Optionally, after exposing the alignment mark, the method further includes:

etching the exposed alignment mark to form a recess;

A functional film layer is formed on the second surface and the recessed surface.

Optionally, the method for forming the alignment mark includes:

patterning the first surface to form a plurality of spaced apart grooves on the first surface;

filling the groove and covering the first surface with a marking material;

The marking material is etched to or below the first surface to form the alignment mark.

Optionally, the depth of the groove is 2um-2.5um, and the width of the groove is 0.7um-2.5um.

Optionally, an interconnection structure electrically connected to the first metal pillar and the pattern sensor element is formed between the first metal pillar and the pattern sensor element in the dielectric layer.

Optionally, a shielding layer shielding the alignment mark is formed in isolation between the first metal pillar and the alignment mark in the dielectric layer.

Optionally, the first metal pillars are uniformly dispersed throughout the dielectric layer.

The present invention also provides a semiconductor device, the semiconductor device comprising:

A first wafer, the first wafer includes a first surface and a second surface oppositely arranged, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed on the first surface, wherein, the alignment mark runs through the first wafer and is exposed on the second surface;

For the second wafer, the first surface of the first wafer is bonded to the second wafer.

Optionally, the semiconductor device also includes:

a dielectric layer, located on the first surface, covering the alignment marks and graphic sensor elements;

The first metal pillars are arranged at intervals in the dielectric layer and protrude from the surface of the dielectric layer;

A second wafer, a plurality of second metal pillars spaced apart from each other are formed on the second wafer, wherein the first metal pillars and the second metal pillars are bonded to each other.

Optionally, on the second surface, the height of the alignment mark is lower than that of the second surface, thereby forming a recess.

Optionally, a functional film layer is formed on the second surface and the recessed surface.

Optionally, an interconnection structure electrically connected to the first metal pillar and the pattern sensor element is formed between the first metal pillar and the pattern sensor element in the dielectric layer.

Optionally, a shielding layer shielding the alignment mark is formed in isolation between the first metal pillar and the alignment mark in the dielectric layer.

The present invention also provides an electronic device, which includes the above-mentioned semiconductor device.

To sum up, in the semiconductor device of the present invention, the alignment mark is designed on one side of the graphic sensor element during the manufacturing process, instead of the upper and lower positional relationship, and the alignment mark runs through all The first wafer is exposed on the second surface, and under the condition of ensuring the bonding quality, easily identifiable alignment marks are formed, which can further improve the performance and yield of the semiconductor device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1A-FIG. 1I are structural schematic diagrams of devices obtained in related steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

2 is a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 3 shows a schematic diagram of an electronic device in an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

At present, the manufacturing method of the semiconductor device including the alignment mark includes the following steps: firstly, a first wafer is provided, wherein the first wafer is a device wafer, and various functional devices are first formed on the device wafer , such as an image sensor device, and then form an alignment mark on the wafer, usually the alignment mark is formed on the device area, for example, formed above the functional device in the vertical direction, and on the forming metal pillars on the outside of the quasi-mark, and then providing a second wafer on which metal pillars are also formed, and then bonding the first wafer and the second wafer through the metal pillars After bonding, the alignment mark area is usually not bonded, so a cavity will be formed between the metal pillars. When the backside process is performed on the first wafer, the first wafer There is a limited amount of pressure to which there is a risk of silicon bursting. In order to solve this problem, generally, a dummy metal pillar can be formed in the alignment mark area inside the metal pillar to support the first wafer, so as to increase the stress on the first wafer, but such a Then, the virtual metal pillars will form interference patterns, which will greatly affect the quality of quasi-marks.

Therefore, in order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

A first wafer is provided, the first wafer includes a first surface and a second surface oppositely arranged, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed in the first surface;

providing a second wafer, and bonding the first surface of the first wafer to the second wafer;

Thinning the second surface of the first wafer to expose the alignment marks.

In the manufacturing process of the semiconductor device of the present invention, the alignment mark is designed on one side of the graphic sensor element instead of the upper and lower positional relationship, and the alignment mark runs through the first wafer , exposed on the second surface, under the condition of ensuring the bonding quality, an easily identifiable alignment mark is formed, which can further improve the performance and yield of the semiconductor device.

Embodiment one

Next, the method for manufacturing a semiconductor device of the present invention will be described in detail with reference to FIGS. 1A-1I and FIG. 2 , wherein FIGS. 1A-1I are devices obtained in the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process flow diagram of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

As shown in Figure 2, the manufacturing method of the semiconductor device specifically includes the following steps:

Step S1: providing a first wafer, the first wafer includes a first surface and a second surface opposite to each other, an alignment mark and a pattern on one side of the alignment mark are formed on the first surface sensor element;

Step S2: providing a second wafer, and bonding the first surface of the first wafer to the second wafer;

Step S3: Thinning the second surface of the first wafer to expose the alignment marks.

First, step 1 is performed, as shown in FIG. 1A, a first wafer 100 is provided, the first wafer includes a first surface and a second surface oppositely arranged, and an alignment mark 1011 and a second surface are formed on the first surface. A graphic sensor element 102 located on one side of the alignment mark.

Specifically, the first wafer 100 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

Wherein the first wafer 100 may be formed with various logic devices, such as various CMOS devices and passive devices, etc., here the second wafer is a CMOS image sensor (CIS) wafer as an example for illustration, Specifically, it is a back-illuminated CIS.

In this embodiment, the constituent material of the first wafer 100 is single crystal silicon.

The first wafer 100 is a device wafer, wherein the device wafer is used to realize the main circuit functions of a predetermined integrated chip, for example, a central processing unit, which is roughly rectangular in shape, and the central processing unit can be composed of many MOSFETs, etc. active circuit components.

The first wafer 100 includes a first surface and a second surface opposite to each other, wherein the first surface is defined as the front side, and the second surface is defined as the back side, all refer to The explanation.

Wherein, in the present invention, the first surface of the first wafer can be divided into a mark area and a device area, so that alignment marks and pattern sensor elements are formed in different areas, instead of being formed in the current process the same area.

For example, in the present invention, the first surface includes a marking area and a device area adjacently arranged, wherein the alignment mark is formed in the marking area, and the pattern sensor element is formed in the device area.

Optionally, the device area can be set in the center area of the wafer, and the mark area can be set in the edge area. Of course, the division of the mark area and the device area is for better illustration, which is on the first wafer There are no clear boundaries.

Wherein, the method for forming the alignment mark includes:

Step 1: patterning the first surface to form a plurality of grooves spaced apart from each other on the first surface;

Step 2: filling the groove and covering the first surface with a marking material;

Step 3: Etching the marking material to the first surface or below the first surface to form the alignment mark 1011 .

In the step 1, a mask layer is formed and patterned on the first surface of the first wafer, so as to form a plurality of mutually spaced grooves on the first surface, as shown in FIG. 1A .

Wherein, the groove may have a relatively large aspect ratio, such as an elongated columnar structure.

Optionally, the depth of the groove is 2um-2.5um, and the width of the groove is 0.7um-2.5um.

In this step, the method of deep reactive ion etching (DRIE) is selected to form the groove, for example, in the step of deep reactive ion etching (DRIE), silicon hexafluoride (SF ₆ ) is selected as the process gas, and the RF power supply makes silicon hexafluoride react with intake air to form high ionization. In the etching step, the working pressure is controlled to be 20mTorr-8Torr, the power is 600W, the frequency is 13.5MHz, and the DC bias voltage can be continuously controlled within -500V-1000V. To ensure the needs of anisotropic etching, the selection of deep reactive ion etching (DRIE) can maintain a very high etching photoresist selectivity ratio. The deep reactive ion etching (DRIE) system can choose equipment commonly used in the field, and is not limited to a certain model.

In the step 2, a marking material 101 is deposited to fill the groove and cover the first surface, wherein the marking material 101 can be selected from a material having a larger etch selectivity than that of the first wafer, for example Dielectric materials can be selected, such as SiO ₂ , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN).

Optionally, SiO ₂ is selected as the marking material 101 in this embodiment.

Wherein, in order to fully fill the groove, after filling the groove, continue to deposit to cover the first surface to a certain thickness, as shown in FIG. 1B .

In the step 3, it is advisable to completely remove the SiO ₂ on the first surface and keep as much SiO ₂ in the groove as possible, as shown in FIG. 1C , and then form an alignment mark 1011 .

A CIS process step is then performed on the device region of the first surface to form patterned sensor elements 102 in the device region. Wherein, the specific type and forming method of the pattern sensor element 102 can refer to the commonly used methods in the field, and are not limited to a certain one, which will not be repeated here.

Execute step 2, forming a dielectric layer 103 on the alignment mark and the pattern sensor element, forming an interconnection structure electrically connected to the pattern sensor element in the dielectric layer, and at the same time A blocking layer that blocks the alignment marks is formed in the layer.

Specifically, as shown in FIG. 1D , the interconnection structure 104 includes several metal layers located in different layers, and through holes are provided between the metal layers, thereby forming an interconnection structure in which metal layers and through holes are alternately connected.

In the alignment mark area, however, the shielding layer is not in contact with the alignment mark, as shown in FIG. 1D .

Wherein, the shielding layer can be a metal layer, which can be formed at the same time as the metal layer in the interconnection structure, and can be located on the same layer as any metal layer in the interconnection structure, that is, it can be selected to be in the same layer as the metal layer in the interconnection structure. Any metal layers are formed together, as shown in Figure 1E.

Wherein, the formation method of the interconnection structure can adopt a conventional manufacturing method, such as forming a dielectric layer, and then patterning the dielectric layer to form an opening and filling the opening with a conductive material, forming each metal layer in turn. layers and vias to form the interconnection structure, and a second dielectric layer 105 is further deposited after forming the top metal layer to cover and planarize the top metal layer.

Step 3 is performed to form a plurality of protruding first metal pillars 106 spaced apart from each other in the second dielectric layer 105 .

Specifically, as shown in FIG. 1E, in this step, several metal pillars 106 are formed at intervals in a dielectric layer, and the dielectric layer can be made of SiO ₂ , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN), etc.

Exemplarily, the material of the first metal pillar 106 can use any suitable metal material, and can use one or more materials selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al. conductive materials and metal compounds.

In this embodiment, the material of the first metal pillar 106 includes Cu.

Further, the top of the first metal pillar 106 is exposed from the dielectric layer, thereby forming a protruding first metal pillar, as shown in FIG. 1E .

Step 4 is performed to provide a second wafer 200 on which a number of second metal pillars 202 spaced apart from each other are formed; and the first metal pillars 106 and the second metal pillars 202 are bonded.

Specifically, as shown in FIG. 1F, the second wafer 200 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), stack-on-insulator Silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

The second wafer 200 is a logic wafer, and various logic devices, such as various CMOS devices and passive devices, are formed in the second wafer 200 .

As an example, functional components 201 such as transistors, interconnect structures and radio frequency devices may also be formed in the second wafer 200 . In this embodiment, transistors are used to form various circuits, and radio frequency devices are used to form radio frequency components or modules.

Wherein, the transistor may be an ordinary transistor, a high-k metal gate transistor, a fin transistor or other suitable transistors. The interconnect structure may include metal layers (eg, copper or aluminum layers), metal plugs, and the like. The radio frequency device may include devices such as inductors.

In addition to transistors, radio frequency devices and interconnection structures, CMOS devices may also include various other feasible components, such as resistors, capacitors, MEMS devices, etc., which are not limited here.

Wherein, the specific structure and formation method of each component in the CMOS device can be selected by those skilled in the art with reference to the prior art according to actual needs, and will not be repeated here.

A second metal column 202 is formed on the second wafer, and the material of the second metal column 202 can use any suitable metal material, and can use materials with materials ranging from Ag, Au, Cu, Pd, Cr, Mo, Ti , one or more conductive materials and metal compounds selected from Ta, W and Al.

In this embodiment, the material of the second metal pillar 202 includes Cu.

Further, the top of the second metal pillar 202 is exposed from the dielectric layer, thereby forming a protruding second metal pillar, as shown in FIG. 1E .

Then bonding the first metal pillar and the second metal pillar, so as to bond the first wafer and the second wafer.

Exemplarily, when the material of the first metal pillar and the second metal pillar is copper metal, Cu-Cu bonding is performed. Optionally, the bonding pressure is 20kN-50kN, preferably 30kN-40kN, and the bonding temperature is 300° C. to 450° C., and the bonding time is 20 minutes to 60 minutes.

Wherein, the first metal pillar and the second metal pillar are evenly distributed in the first wafer and the second wafer, so after bonding, the metal pillar can bear the burden of the first wafer in the subsequent process. in the stress.

Step 5 is performed, thinning the second surface of the first wafer to expose the alignment marks 1011 .

Specifically, as shown in FIG. 1G , the thinning method can be a commonly used method in the field, and is not limited to a certain one, so details will not be repeated here.

In this step, the second surface of the first wafer is ground to the top of the alignment marks to expose the alignment marks.

In the present invention, after the alignment mark is exposed, the alignment mark penetrates the first wafer and is exposed on the second surface, forming an easily identifiable alignment mark while ensuring the bonding quality , the performance and yield of the semiconductor device can be further improved.

Step 6 is performed, etching the exposed alignment mark to form a recess; forming a low-transmittance or opaque film layer on the second surface and the recess.

Specifically, as shown in FIG. 1H , in this step, the exposed alignment mark is etched back to form a recess, and then an uneven structure is formed on the second surface.

When the first layer on the back defines the film layer as a low-transmittance or opaque film (such as Al), a step of silicon oxide etching is performed after thinning to form an uneven shape. After the film is prepared to form a topographical mark, a high-quality topographical mark can still be formed, as shown in Figure 1I.

So far, the introduction of the preparation of the semiconductor gas device according to the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which will not be repeated here. Moreover, in addition to the above-mentioned steps, the manufacturing method of this embodiment may also include other steps among the above-mentioned steps or between different steps. Let me repeat.

In the manufacturing process of the semiconductor device of the present invention, the alignment mark is designed on one side of the graphic sensor element instead of the upper and lower positional relationship, and the alignment mark runs through the first wafer , exposed on the second surface, under the condition of ensuring the bonding quality, an easily identifiable alignment mark is formed, which can further improve the performance and yield of the semiconductor device.

Embodiment two

The present invention also provides a semiconductor device prepared by using the manufacturing method of the foregoing embodiment 1. Specifically, the semiconductor device of the present invention will be described in detail with reference to FIG. 1I .

The semiconductor device includes:

A first wafer, the first wafer includes a first surface and a second surface oppositely arranged, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed on the first surface, wherein, the alignment mark runs through the first wafer and is exposed on the second surface;

The second wafer, the first surface of the first wafer and the second wafer are bonded to each other.

Wherein, on the second surface, the height of the alignment mark is lower than that of the second surface, thereby forming a depression.

Wherein, a low-transmittance or opaque film layer is formed on the second surface and the groove.

Wherein, an interconnection structure electrically connected to the first metal pillar and the pattern sensor element is formed between the first metal pillar and the pattern sensor element in the dielectric layer.

Wherein, a shielding layer shielding the alignment mark is formed in isolation between the first metal pillar and the alignment mark in the dielectric layer.

Optionally, as shown in FIG. 1I, the first wafer includes a first surface and a second surface that are oppositely arranged, and an alignment mark 1011 and an alignment mark 1011 on one side of the alignment mark are formed on the first surface. Graphic sensor element 102 .

Specifically, the first wafer 100 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

Wherein the first wafer 100 may be formed with various logic devices, such as various CMOS devices and passive devices, etc., here the second wafer is a CMOS image sensor (CIS) wafer as an example for illustration, Specifically, it is a back-illuminated CIS.

In this embodiment, the constituent material of the first wafer 100 is single crystal silicon.

The first wafer 100 is a device wafer, wherein the device wafer is used to realize the main circuit functions of a predetermined integrated chip, for example, a central processing unit, which is roughly rectangular in shape, and the central processing unit can be composed of many MOSFETs, etc. active circuit components.

The first wafer 100 includes a first surface and a second surface opposite to each other, wherein the first surface is defined as the front side, and the second surface is defined as the back side, all refer to The explanation.

Wherein, in the present invention, the first surface of the first wafer can be divided into a mark area and a device area, so that alignment marks and pattern sensor elements are formed in different areas, instead of being formed in the current process the same area.

For example, in the present invention, the first surface includes a marking area and a device area adjacently arranged, wherein the alignment mark is formed in the marking area, and the pattern sensor element is formed in the device area.

Optionally, the device area can be set in the center area of the wafer, and the mark area can be set in the edge area. Of course, the division of the mark area and the device area is for better illustration, which is on the first wafer There are no clear boundaries.

Optionally, the alignment mark has a depth of 2um-2.5um, and the alignment mark has a width of 0.7um-2.5um.

A dielectric layer 103 is formed on the alignment mark and the graphic sensor element, an interconnect structure electrically connected to the graphic sensor element is formed in the dielectric layer, and an interconnection structure is formed in the dielectric layer at the same time. A shielding layer that shields the alignment marks.

Wherein, the interconnection structure 104 includes several metal layers located in different layers, and through holes are provided between the metal layers, thereby forming an interconnection structure in which metal layers and through holes are alternately connected.

In the alignment mark area, the shielding layer does not contact the alignment mark.

Wherein, the shielding layer can be a metal layer, which can be formed at the same time as the metal layer in the interconnection structure, and can be located on the same layer as any metal layer in the interconnection structure, that is, it can be selected to be in the same layer as the metal layer in the interconnection structure. Any metal layers are formed together.

A plurality of protruding first metal pillars 106 spaced apart from each other are formed in the dielectric layer.

The plurality of first metal pillars 106 are formed at intervals in a dielectric layer, and the dielectric layer can be made of, for example, SiO ₂ , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN) and so on.

Exemplarily, the material of the first metal pillar 106 can use any suitable metal material, and can use one or more materials selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al. conductive materials and metal compounds.

In this embodiment, the material of the first metal pillar 106 includes Cu.

Further, the top of the first metal pillar 106 is exposed from the dielectric layer, thereby forming a protruding first metal pillar.

The second wafer 200 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), Silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

The second wafer 200 is a logic wafer, and various logic devices, such as various CMOS devices and passive devices, are formed in the second wafer 200 .

As an example, functional components 201 such as transistors, interconnect structures and radio frequency devices may also be formed in the second wafer 200 . In this embodiment, transistors are used to form various circuits, and radio frequency devices are used to form radio frequency components or modules.

Wherein, the transistor may be an ordinary transistor, a high-k metal gate transistor, a fin transistor or other suitable transistors. The interconnect structure may include metal layers (eg, copper or aluminum layers), metal plugs, and the like. The radio frequency device may include devices such as inductors.

In addition to transistors, radio frequency devices and interconnection structures, CMOS devices may also include various other feasible components, such as resistors, capacitors, MEMS devices, etc., which are not limited here.

Wherein, the specific structure and formation method of each component in the CMOS device can be selected by those skilled in the art with reference to the prior art according to actual needs, and will not be repeated here.

A second metal column 202 is formed on the second wafer, and the material of the second metal column 202 can use any suitable metal material, and can use materials with materials ranging from Ag, Au, Cu, Pd, Cr, Mo, Ti , one or more conductive materials and metal compounds selected from Ta, W and Al.

In this embodiment, the material of the second metal pillar 202 includes Cu.

Further, the top of the second metal pillar 202 is exposed from the dielectric layer, thereby forming a protruding second metal pillar.

In the present invention, the alignment mark runs through the first wafer and is exposed on the second surface. In the case of ensuring the bonding quality, an easily identifiable alignment mark is formed, which can further improve the semiconductor device. performance and yield.

The height of the alignment mark is lower than the second surface, thereby forming a depression, and a low-transmittance or light-impermeable film layer is formed on the second surface and the depression.

Specifically, in this step, the exposed alignment mark is etched back to form a recess, and then an uneven structure is formed on the second surface.

When the first layer on the back defines the film layer as a low-transmittance or opaque film (such as Al), a step of silicon oxide etching is performed after thinning to form an uneven shape. After the formation of topography marks after preparation, high-quality topography marks can still be formed, as shown in Figure 1I.

Since the semiconductor device of the present invention is prepared by using the method in the first embodiment above, it also has the same advantages.

Embodiment Three

The present invention also provides an electronic device, including the semiconductor device described in Embodiment 2, and the semiconductor device is prepared according to the method described in Embodiment 1.

The electronic device of this embodiment can be any electronic device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV set, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, etc. Product or equipment, but also any intermediate product including electrical circuits. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

Among them, FIG. 3 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

Wherein the mobile phone includes the semiconductor device described in Embodiment 2, and the semiconductor device includes:

A first wafer, the first wafer includes a first surface and a second surface oppositely arranged, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed on the first surface, wherein, the alignment mark runs through the first wafer and is exposed on the second surface;

The second wafer, the first surface of the first wafer and the second wafer are bonded to each other.

The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (15)

1. A method for manufacturing a semiconductor device, characterized in that the method comprises: providing a first wafer, the first wafer comprising a first surface and a second surface oppositely disposed, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed in the first surface; providing a second wafer, and bonding the first surface of the first wafer to the second wafer; Thinning the second surface of the first wafer to expose the alignment marks. 2. The method according to claim 1, wherein the bonding method comprises: forming a dielectric layer on the alignment mark and the pattern sensor element, forming a plurality of protruding first metal pillars spaced apart from each other in the dielectric layer; providing a second wafer, on which a plurality of second metal pillars spaced apart from each other are formed; Bonding the first metal post and the second metal post. 3. The method according to claim 1, further comprising: after exposing the alignment mark, the method further comprises: etching the exposed alignment mark to form a recess; A functional film layer is formed on the second surface and the recessed surface. 4. The method according to claim 1, wherein the method for forming the alignment mark comprises: patterning the first surface to form a plurality of spaced apart grooves on the first surface; filling the groove and covering the first surface with a marking material; The marking material is etched to or below the first surface to form the alignment mark. 5 . The method according to claim 4 , wherein the depth of the groove is 2um˜2.5um, and the width of the groove is 0.7um˜2.5um. 6. The method according to claim 1, characterized in that, a contact between the first metal post and the pattern sensor element is formed in the dielectric layer between the first metal post and the pattern sensor element. An interconnection structure in which components are electrically connected. 7 . The method according to claim 1 , wherein a shielding layer for shielding the alignment mark is formed in isolation between the first metal pillar and the alignment mark in the dielectric layer. 8. The method of claim 1, wherein the first metal pillars are uniformly dispersed throughout the dielectric layer. 9. A semiconductor device, characterized in that the semiconductor device comprises: A first wafer, the first wafer includes a first surface and a second surface oppositely arranged, an alignment mark and a pattern sensor element located on one side of the alignment mark are formed on the first surface, wherein, the alignment mark runs through the first wafer and is exposed on the second surface; For the second wafer, the first surface of the first wafer is bonded to the second wafer. 10. The semiconductor device according to claim 9, wherein the semiconductor device further comprises: a dielectric layer, located on the first surface, covering the alignment marks and graphic sensor elements; The first metal pillars are arranged at intervals in the dielectric layer and protrude from the surface of the dielectric layer; A second wafer, a plurality of second metal pillars spaced apart from each other are formed on the second wafer, wherein the first metal pillars and the second metal pillars are bonded to each other. 11. The semiconductor device according to claim 9, wherein on the second surface, the height of the alignment mark is lower than that of the second surface, thereby forming a recess. 12. The semiconductor device according to claim 11, wherein a functional film layer is formed on the second surface and the recessed surface. 13. The semiconductor device according to claim 10, characterized in that, between the first metal pillar and the pattern sensor element in the dielectric layer, there is a contact between the first metal pillar and the pattern sensor element. The interconnect structure to which the sensor elements are electrically connected. 14. The semiconductor device according to claim 10, wherein a shielding layer is formed between the first metal pillar and the alignment mark in the dielectric layer to shield the alignment mark . 15. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 9 to 14.