CN108565315A - Thin film semiconductor's photoelectric device with veining front surface and/or back surface - Google Patents

Abstract

The present invention relates to thin film semiconductor's photoelectric devices with veining front surface and/or back surface.A kind of method for providing veining layer in the opto-electronic device is disclosed.Method includes depositing template layer on the first layer.Template layer has apparent inhomogeneities on thickness or in composition or in the two, including forms one or more islands to provide the possibility of at least one texturizing surfaces of island nitride layer.Method further includes that template layer and first layer are exposed to etch process to generate or change at least one texturizing surfaces.At least one texturizing surfaces changed cause light scattering in operation.

Description

Thin-film semiconductor optoelectronic devices with textured front and/or back surfaces

This application is a divisional application of the application dated August 5, 2015, the application number is 201510475349.5, and the title of the invention is "thin-film semiconductor optoelectronic device with textured front surface and/or back surface".

Cross References to Related Applications

This application is a continuation-in-part of U.S. Patent Application Serial No. 13/354,175, entitled "TEXTURING A LAYER IN ANOPTOELECTRONIC DEVICE FOR IMPROVED ANGLE RANDOMIZATION OF LIGHT," filed January 19, 2012, which is incorporated by reference at It is incorporated herein in its entirety.

technical field

Embodiments of the invention generally relate to optoelectronic semiconductor devices, such as photovoltaic devices including solar cells, and methods for fabricating such devices.

Background technique

Optoelectronic devices, such as photovoltaic devices and light emitting diodes (LEDs), are becoming more widely used because of the increased importance of energy efficiency. In a photovoltaic device such as a solar cell, the junction of the solar cell absorbs photons to generate electron-hole pairs that are separated by the junction's internal electric field to generate a voltage, thereby converting light energy into electrical energy. The absorber layer of an ideal photovoltaic (PV) device will absorb all photons impinging on the front side of the PV device facing the light source, since the open circuit voltage (V _oc ) or short circuit current (I _sc ) is proportional to the light intensity. However, several loss mechanisms typically interfere with the absorber layer of a PV device, which absorbs all the light reaching the front side of the device. For example, some photons can pass through the absorber layer without generating any electron-hole pairs and thus never contribute to the generation of electricity by the device. In other cases, the semiconducting layers of the PV device may be smooth and thus may reflect most of the impinging photons, preventing them from reaching the absorber layer.

Accordingly, there is a need for optoelectronic devices with increased efficiency and methods for fabricating such optoelectronic devices at reduced cost and greater flexibility compared to conventional optoelectronic device fabrication.

Contents of the invention

A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on the first layer. The template layer is substantially non-uniform in thickness or composition, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The at least one textured surface causes light scattering in operation.

Methods for providing optoelectronic devices are disclosed. The method includes depositing an absorber layer and depositing an emitter layer. The method also includes depositing a first layer of a first material on the emitter layer and the absorber layer. Additionally, the method includes depositing a template layer of a second material on the first layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The at least one textured surface causes light scattering in operation. Finally, the method includes depositing a dielectric layer on the island layer and depositing a metal layer on the dielectric layer.

Methods for providing optoelectronic devices are disclosed. The method includes depositing an emitter layer and depositing an absorber layer. The method also includes depositing a first layer of a first material on the emitter layer and the absorber layer. Additionally, the method includes depositing a template layer of a second material on the first layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The at least one textured surface causes light scattering in operation. Finally, the method includes depositing an anti-reflection layer on the island layer.

Description of drawings

The drawings merely illustrate certain embodiments and are therefore not to be considered limiting in scope.

Figures 1A-1C show top-down views of a template island layer above a first layer;

Figure 2 depicts a cross-sectional view of a photovoltaic device according to certain embodiments described herein;

Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H depict cross-sectional views of the photovoltaic device of Figure 1, wherein an island layer has been deposited on a base layer;

Figure 4 depicts a cross-sectional view of the photovoltaic device of Figure 3, wherein a semiconductor contact layer and a dielectric layer have been deposited on the island layer;

Figure 5 depicts a cross-sectional view of the photovoltaic device of Figure 4 wherein holes have been formed in the dielectric layer;

6A and 6B depict top views of different embodiments of masks that may be used to form holes in the dielectric layer shown in FIG. 5;

Figure 7 depicts a cross-sectional view of the photovoltaic device of Figure 5, wherein a metal layer has been deposited on the dielectric layer;

8 depicts a cross-sectional view of one embodiment of a photovoltaic cell produced by the photovoltaic device of FIG. 7 after a lift-off process;

Figure 9 depicts a cross-sectional view of another embodiment of a photovoltaic cell produced by the photovoltaic device of Figure 3A;

Figure 10 depicts a cross-sectional view of a photovoltaic cell illustrating scattering of light by a textured layer on the back of the device;

11 depicts a cross-sectional view of a photovoltaic device providing a front-side light-harvesting textured layer, according to certain embodiments described herein;

FIG. 12 depicts a cross-sectional view of the photovoltaic device of FIG. 11 in which an island layer has been deposited on a substrate layer; and

Figure 13 depicts a cross-sectional view of the photovoltaic device of Figure 12 where layers have been deposited on the island layer.

Detailed ways

Embodiments of the present invention relate generally to optoelectronic devices and processes, and more particularly to optoelectronic semiconductor devices including one or more textured layers and fabrication processes for forming such optoelectronic devices.

Herein, a layer may be described as being deposited on one or more other layers. This term indicates that a layer may be deposited directly on top of other layers, or in certain embodiments may indicate that one or more additional layers may be deposited between a layer and other layers. Additionally, other layers may be arranged in any order.

The term template layer is defined herein to indicate a layer having significant inhomogeneity in thickness or in composition or both. This includes the possibility that the thickness non-uniformity is so great that the template layer is multiple separate islands. A textured surface is created or altered when the template layer and layers below the template layer are exposed to an etchant or etching process. Textured surfaces can induce light scattering, which can improve light trapping in optoelectronic devices.

The term island refers to a layer of material that is discontinuous in plan, which allows etchant to potentially reach underlying layers. The island layer can form multiple distinct unconnected regions (FIG. 1A), or can be fully connected but with gaps (FIG. 1B), or can be a combination of both (FIG. 1C). Each of these figures shows a top-down view of template island layer 152 over first layer 112 . These layers are described in more detail herein.

Embodiments disclosed herein relate to light trapping using textured layers for greater device efficiency.

Figure 2 illustrates a cross-sectional view of one embodiment of a photovoltaic device 100 suitable for use with embodiments described herein. Although the embodiments herein relate to photovoltaic devices, the described features may also be applied to other optoelectronic semiconductor devices such as LEDs, for example to scatter light in the device to provide increased or more efficient light production.

Device 100 includes a cell 120 coupled to a growth wafer 101 with an ELO release or sacrificial layer 104 disposed therebetween. Multiple layers of epitaxial material having different compositions are deposited within photovoltaic device 100 . Multiple layers of epitaxial material may be grown or otherwise formed by suitable methods for semiconductor growth. Cell 120 may be, for example, a gallium arsenide-based cell having layers made of Group III-V materials. Group III-V materials are thin films of epitaxially grown layers. In certain embodiments, the epitaxially grown layer can be formed by growing a Group III-V material, for example, during a high growth rate vapor deposition process. High growth rate deposition processes allow growth rates greater than 5 μm/hr, such as about 10 μm/hr or greater, or up to about 100 μm/hr or greater. The high growth rate process involves heating the wafer to a deposition temperature of about 550°C or greater within the processing system, exposing the wafer to a deposition gas containing chemical precursors, such as gallium precursor gas and arsine, and a layer containing gallium arsenide is deposited on the wafer. The deposition gas may contain a Group V precursor, such as arsine, phosphine, or ammonia.

As described herein, deposition processes for depositing or forming Group III-V materials can be performed in various types of deposition chambers. For example, one continuous feed deposition chamber that may be used to grow, deposit, or otherwise form Group III-V materials is described in commonly assigned U.S. Patent Application Serial No. 12/475,131, both filed May 29, 2009 and Ser. No. 12/475,169, which are incorporated herein by reference in their entirety.

Some examples of layers useful in device 100 and methods for forming such layers are disclosed in co-pending U.S. Patent Application Serial No. 12/939,077, filed November 3, 2010, and incorporated by reference in its Incorporated into this article as a whole.

In certain embodiments, one or more buffer layers 102 may be formed on the growth wafer 101 to initiate formation of the photovoltaic device 100 . Growth wafer 101 may comprise, for example, an n-type or semi-insulating material, and may comprise the same or similar material as one or more subsequently deposited buffer layers. In other embodiments p-type materials may be included.

A sacrificial layer (ELO release layer) 104 may be deposited on growth wafer 101 or buffer layer 102 (if present). Sacrificial layer 104 may comprise a suitable material, such as aluminum arsenide (AlAs) or aluminum arsenide, and is used to form a lattice structure for the layers contained within cell 120, and is then etched and be removed.

Layers of a photovoltaic cell 120 can be deposited on the sacrificial layer 104, which in some embodiments can include a front contact layer 105, a front window 106, an absorber layer 108 formed adjacent to the front window 106, an emitter layer 110, and on the textured base layer 112. A front semiconductor contact layer 105 , or an interfacial layer, may be deposited on the sacrificial layer 104 . The front contact layer 105 may in some embodiments be an n-doped layer comprising a Group III-V material, such as gallium arsenide.

A front window 106, also referred to as a passivation layer, may be formed on the substrate 101 on the sacrificial layer 104, or on the optional contact layer 105 if present. The front window 106 may be transparent to allow incident photons to pass through the front window 106 on the front side of the cell 120 to other underlying layers. In some embodiments, the front window 106 may comprise a Group III-V material.

Absorber layer 108 may be formed on window layer 106 . The absorber layer 108 may comprise any suitable Group III-V compound semiconductor, such as gallium arsenide (GaAs). In certain embodiments, the absorber layer 108 can be monocrystalline and can be n-doped. Different embodiments may provide different doping concentrations, such as ranging from about 1×10 ¹⁶ cm ⁻³ to about 1×10 ¹⁹ cm ⁻³ .

In certain embodiments, emitter layer 110 may be formed on absorber layer 108 . In certain embodiments, emitter layer 110 may be p-doped (eg, p ⁺ doped). Emitter layer 110 may comprise any suitable Group III-V compound semiconductor and may be single crystal. For example, the doping concentration of the heavily p-doped emitter layer 110 may range from about 1×10 ¹⁷ cm ⁻³ to about 1×10 ²⁰ cm ⁻³ . In certain embodiments, emitter layer 110 may form a heterojunction with absorber layer 108 .

In certain embodiments, the contact of the n-type absorber layer 108 with the p-type emitter layer 110 creates a p-n junction for absorbing photons. Other embodiments may include one or more intermediate layers between the absorber layer 108 and the emitter layer 110 . Other embodiments may use p-doped substrate/absorber layers and n-doped back/emitter layers, and/or other p/n-doped layers instead of n/p in the description herein doped layer.

A base layer 112 for texturing may optionally be deposited on the emitter layer 110 . The base layer 112 may provide a first layer and may facilitate island formation by having a different composition than the template layer on which the template layer is deposited for texturing purposes. In certain embodiments, base layer 112 may be monocrystalline and p-doped and have a doping concentration in the range of about 5×10 ¹⁷ cm ⁻³ to about 2×10 ¹⁹ cm ⁻³ . The base layer 112 and the template layer are described in more detail below. In certain other embodiments, base layer 112 is not included in device 100 . For example, a template layer (described below) may be deposited on the emitter layer 110 or on the absorber layer 108 (if located above the emitter layer).

3A is a cross-sectional view of a photovoltaic device 100 comprising depositing a template layer 140 on a substrate layer 112 according to one embodiment of a textured surface for use as a back reflector. Template layer 140 has an inconsistent thickness, which can cause light reflection and light scattering in the device, thereby increasing light trapping.

The template layer used can vary in different embodiments. In one embodiment, the template layer has significant thickness inconsistencies, including the possibility of multiple distinct islands of template material. In another embodiment, the template layer has compositional inconsistencies, but may or may not have significant thickness inconsistencies.

When the template layer and other layers in the device are exposed to an etchant or etching process, the template layer may not be etched significantly, or may be etched (but at a slower rate than the first layer the template layer is deposited on rate), or may be etched at a rate comparable to or greater than the rate at which the first layer on which the template layer is deposited is etched. Thus, the template layer may (but need not) be completely etched away during the process of forming or altering the textured surface. Alternatively, the template layer may still be partially or entirely present after the etching process, but may be partially or entirely removed in a subsequent processing step before fabrication of the optoelectronic device is complete.

Template layers can have inconsistent compositions. Different portions of the template layer having different material compositions may etch at different rates when exposed to an etchant or etching process. In this way, the template layer can develop or increase thickness inconsistencies during the etching process, even though the thickness was consistent prior to etching.

A template layer having an inconsistent thickness prior to etching may generally be referred to as an island layer. Island growth can arise, at least in part, from strain between different materials caused by lattice mismatch between the materials. Alternatively, island growth can result from the fact that the island layer is very thin and does not form a continuous layer. Alternatively, the island growth can arise due to dynamic etching itself during the deposition process.

For example, in some embodiments, such as the example embodiment shown in FIG. 3A , a Stranski-Krastanov process may be used to form template layer 140 . The process involves depositing a particular material by first forming a wet layer 142 of template layer material (which may include one or more individual layers), followed by forming islands 144 of the same material on the wet layer 142 . In other embodiments, other types of island growth processes may be used. For example, FIG. 3B illustrates the formation of islands using the Volmer-Weber process, which may not provide a wet layer of template layer material on which the islands grow, as described below.

The template layer 140 may include a semiconductor material, and may be a different material than that of the base layer 112 on which the template layer 140 is deposited. In some embodiments, template layer 140 may be a material having a larger bandgap than the material of base layer 112 . In some examples, template layer 140 may include phosphorus, gallium, aluminum, indium, arsenic, antimony, nitrogen, derivatives thereof, and/or combinations thereof. For example, in some embodiments, base layer 112 may include gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs), and template layer 140 may include indium gallium arsenide (InGaAs) or gallium arsenide antimony (GaAsSb). In other embodiments, base layer 112 may include aluminum gallium arsenide (AlGaAs), and template layer 140 may include gallium phosphide (GaP). In other embodiments, base layer 112 may include indium arsenide (InAs), and template layer 140 may include indium arsenide antimony (InAsSb). In still other embodiments, base layer 112 may include gallium indium phosphide (GaInP), and template layer 140 may include gallium phosphide (GaP) or aluminum phosphide (AlP). In still other embodiments, base layer 112 may include indium phosphide (InP), and template layer 140 may include indium phosphorus antimony (InPSb). In some embodiments, the template layer may include gallium indium arsenide nitride (GaInNAs), gallium nitrogen arsenide (GaNAs), gallium arsenide phosphide (GaAsP), aluminum gallium arsenide phosphide (AlGaAsP), or aluminum gallium arsenide phosphide (AlGaP). In any of these embodiments, derivatives and/or combinations of these materials may be used. Some embodiments may use doped materials for the template layer 140; for example, ^the material may ^be p-doped ^and may have ^a (eg about 1×10 ¹⁸ cm ^-3 ) doping concentration.

In some embodiments, template layer 140 includes a material having a refractive index (n) and absorptivity (k) that increases or maximizes the ability to scatter or reflect light. For example, template layer 140 may include a transparent material that allows light to pass through the template layer. The term "transparent" as used herein refers to a negligible amount of absorption in the wavelength range in which the optoelectronic device operates. For example, in some embodiments, template layer 140 may have a refractive index in the range of about 1 to about 3.5. Furthermore, in some embodiments, the material of template layer 140 may have an absorbance (k) in the range of about 0 to about 1×10 ⁻² , such as about 1×10 ⁻³ or about 1×10 ⁻⁴ . In some embodiments, template layer 140 may include multiple transparent layers.

In some embodiments, various parameters of the deposition process may be changed or adjusted for the deposition of the template layer 140 as compared to the deposition parameters used during the deposition of previous layers, such as the base layer 112 . For example, the temperature, pressure, deposition gas, and/or growth rate of the deposition process may be varied, as described in more detail below.

In FIG. 3A , wet layer 142 and islands 144 have been deposited on base layer 112 using the Stranski-Krastanov process. The wet layer comprises a complete film of adsorbate that accumulates on a substrate, which is the substrate layer 112 in the depicted example. Wet layer 142 may grow using the deposited material until a certain thickness is achieved, after which further deposition causes one or more islands 144 to grow. Accordingly, islands 144 comprise the same material as wet layer 142 . Once the wet layer 142 has achieved a critical thickness in the Stranski-Krastanov process (as determined by the chemical and physical properties of the wet layer 144 and the base layer 112), the growth of the adsorbate on the base layer 112 continues through the islands 144 Buildup on the wet layer 142 occurs due to strain or stretch in the wet layer material.

Islands 144 provide a textured surface for island layer 140 . The growth of islands 144 is controlled to increase or maximize angular randomization of light impinging on or propagating through template layer 140 . This angular randomization of light can be augmented or maximized by adjusting or tailoring different parameters of the growth conditions of the islands 144 (and thus causing the growth to be adjusted or tailored) so that the islands acquire specific properties. Some of the different parameters include the amount of material deposited for the template layer, the deposition temperature, the deposition pressure, the growth rate of the template layer material, the group V elements flowing in the deposition gas, and the influence of crystallization between the substrate layer and the template layer material. Composition of lattice mismatched template materials. The amount of template layer material deposited can affect island growth. For example, larger amounts of deposited material tend to encourage Stranski-Krastanov island growth over Volmer-Weber island growth (described in more detail below).

Another parameter that may be selected to control the growth of islands 144 includes the temperature provided during the deposition process of island layer 140 . For example, the temperature can be made higher to produce islands 144 with larger dimensions. Some examples of temperature ranges for depositing template layer 140 include about 600°C to about 900°C.

Another parameter used to control the growth of the islands 144 is the pressure provided during the deposition of the template layer 140 . For example, the pressure can be made higher to produce islands 144 with smaller dimensions. Some examples of pressure ranges that may be used to deposit template layer 140 include about 50 Torr to about 600 Torr.

Another parameter is the growth rate of the template layer 140, which can be controlled to affect the properties of the textured layer. For example, in some embodiments using the Stranski-Krastanov process, the growth rate of the template layer 140 can be controlled to be faster than the standard growth rate prior to using the Stranski-Krastanov process. In one example, the growth rate may be controlled according to the high growth rate used to deposit the other layers of optoelectronic device 100 as described above with respect to the epitaxially grown layers. In other embodiments, the islands 144 may grow more slowly, for example, if in some embodiments better control over specific features of the islands is desired, such as facets. In some embodiments, a growth rate range of greater than about 5 μm/hour may be used for template layer 140 .

Another parameter that can be controlled is the group V elements flowing in the deposition gas provided during deposition. For example, the deposition gas used to form the template layer 140 may have a certain ratio of group V precursors to group III precursors. In some embodiments, the Group V element is phosphine. This flow ratio can be controlled to tune template growth to desired characteristics. In general, for example, the rate of phosphine flow may be reduced (ie, provided a low rate) relative to the flow rate for a previously deposited layer (eg, base layer 112 ) to promote island formation. In some embodiments, the deposition gas may have a phosphine/Group III precursor in a range of about 50:1 to about 300:1.

Another parameter that may be selected to control the growth of islands 144 is the composition (type) of materials used in base layer 112 and template layer 140 . For example, the material may be selected based on the lattice parameter of the material of the contact layer 112 and the lattice parameter of the material of the template layer 140 . In general, the growth of islands 144 depends in part on the lattice mismatch between base layer 112 and template layer 140 . For example, in the Stanski-Krastanov process, a larger mismatch between lattice parameters results in a smaller critical thickness of wet layer 142 at which island growth begins to occur. The lattice parameter of the material of the base layer 112 and the lattice parameter of the material of the template layer 140 may be selected to provide a desired growth pattern or feature of the islands 144, such as the form of the islands, the islands deposited in a wet layer Then the point where it starts to grow and so on. In some example embodiments, a lattice mismatch in the range of about 3% to about 20% may be used between the material of the base layer 112 and the material of the template layer 140 . In some embodiments, template layer 140 may be a material having a larger bandgap than the material of base layer 112 .

Islands 144 may be manipulated to have specific or general physical characteristics, such as regular or irregular shape, size and/or spacing. For example, the geometry and size of the islands can be controlled by controlling the growth rate of the wet layer and/or the islands, controlling the critical thickness, using a textured or patterned substrate layer 112, and the like.

Additionally, some or all of the physical characteristics (e.g., size, shape, and/or spacing) of the islands 144 may have a certain degree of variation or irregularity to provide varying, non-uniformly shaped, and non-uniformly spaced Island 144. Such a varying and randomized texture generally enhances the ability to randomly scatter light received by the template layer into the absorbing layer 108 compared to a uniform texture.

Because the textured surface comprising the template layer 140 is formed as an inactive scattering layer with a shape formed using the island growth deposition process, the inactive scattering layer has features not provided in the absorbing or emitting layers; and Because a greater degree of variation, irregularity, or randomness is preferred in island 144 formation, in some embodiments, a high quality semiconductor is not necessary as a material for template layer 140 . This may allow some reduction in cost of materials and/or processing compared to previous use of island growth processes, such as the Stranski-Krastanov process, where precisely sized and precisely spaced islands Shapes are grown in the absorbing layer of the device (for example, for tuning wavelength emission in semiconductor lasers). Furthermore, the use of lower quality semiconductors may allow for higher growth rates of the template layer 140 in some embodiments.

Figure 3B is a cross-sectional view of a photovoltaic device 100' comprising a deposition of a template layer 150 suitable for some embodiments disclosed herein, wherein the islands are formed using a different island growth process. In FIG. 3B , a Volmer-Weber growth process has been used for island growth instead of the Stranski-Krastanov process used in the example of FIG. 3A .

Template layer 150 includes islands 152 that have been formed by depositing a template layer material on base layer 112 (or other layers as described above in embodiments without base layer 112). Unlike template layer 140 of FIG. 3A , example template layer 150 does not include a wet layer deposited prior to island formation. Islands 152 are formed because atoms on the surface of base layer 112 have stronger interactions with atoms of the island material than they do with atoms on the surface of the base layer. This causes clusters of material or islands 152 to form as the island material is deposited. Accordingly, some or all of the islands 152 may be formed directly on the surface of the base layer 112, and/or some or all of the islands 152 may have island material formed between the surface of the base layer 112 and the islands 152. layer. Compared to the Stranski-Krastanov growth described above, Volmer-Weber island growth typically occurs at higher lattice mismatches between the template layer and the substrate layer and at lower thicknesses of the template layer. For example, in some embodiments, Volmer-Weber island growth can occur at a thickness of about 5 Angstroms or less of the template layer.

The template layer 150 includes a semiconductor material and is a different material than that of the base layer 112 on which the template layer 150 is deposited. For example, in some embodiments, template layer 150 can include phosphorous, gallium, aluminum, indium, arsenic, antimony, nitrogen, derivatives thereof, and/or combinations thereof. In some embodiments, base layer 112 and template layer 150 may be a combination or derivative of the materials described above for template layer 140 materials. Some embodiments may use doped materials for the template layer 150 .

Similarly, as explained above with respect to the embodiment of FIG. 3A , the growth of islands 152 can be controlled by adjusting one or more different parameters of the deposition process, including those described above.

In another embodiment, the template layer has compositional inconsistencies, but may or may not have significant thickness inconsistencies. Figure 3C is a cross-sectional view of a photovoltaic device 100" illustrating an example of such an embodiment. Template layer 155 comprises a composition of two or more materials, the first material being shown as unshaded regions 156 and 157, and the second material being shown as unshaded regions 156 and 157. Two materials are shown as shaded areas 158. Fig. 3C is intended to illustrate only one example, and is not intended to limit the scope of the invention. In particular, it is possible that there are more than two chemical compositions, 156 and 157 having the same or The material composition is different, and 156 is a connected layer rather than a disconnected island as shown.

The embodiment of FIG. 3C with compositional inconsistencies is then susceptible to an etch that may etch layers 156 and 158 at different rates. In one embodiment, layer 158 is etched more rapidly than layer 156 when the layer is exposed to an etchant or etching process, such that after etching, a structure similar to that of FIG. 3B remains. Layer 156 from Figure 3C then becomes equivalent to island layer 152 of Figure 3B.

In some example embodiments, template layer 155 may include two or more different compositions of one or more semiconductors, such as aluminum gallium arsenide (AlGaAs) (e.g., with different amounts of Al and Ga content), Or aluminum gallium indium phosphide (AlGaInP) (eg, with varying amounts of Al, Ga, and/or In content) or other materials.

To further modify the islands 152 and provide a rougher texture, etching can be performed after the islands are grown as shown in the alternative embodiment 100"' of FIG. 3D. Both islands growth and etching The parameters can control the morphology and size of the texture, thereby maximizing the benefit of the texture to the device performance. The change of the island 152 can include changing the physical size of the textured surface, wherein the changed physical size includes one or more of the textured surfaces The altered shape of the islands or the altered distance between the islands in the textured surface. In various embodiments, the etching can be chemical etching, laser etching, plasma etching, or ion etching or similar etching one or more of.

In another embodiment, after layer 158 is removed, layer 156 provides an island template for further etching.

In another embodiment, layer 140 is partially etched to create an island template (FIG. 3E). After etching, the remainder of layer 140 is labeled 146 . Further etching produces texture in layer 112 (FIG. 3F). FIG. 3F shows an embodiment in which the etchant that etches layer 112 has negligible effect on layer 146 . In yet another embodiment, the etchant that etches layer 112 is effective to simultaneously etch layer 146 (FIG. 3G). It is also possible that layer 146 is no longer present after the etching of layer 112 .

In yet another embodiment ( FIG. 3H ), etching is not limited to layer 112 and those layers above layer 112 , but extends to layer 110 as well. This may apply whether layer 146 or layer 152 or layer 156 is an island layer.

In FIG. 4, the optoelectronic device 100 of FIG. 3B is further processed by depositing an optional semiconductor contact layer 160 on the template layer 140, 150 or 155, followed by depositing a dielectric layer 162 on the contact layer (if present) or Formed by deposition on template layer 140, 150 or 155 (if contact layer 160 is not present). Template layer 140 is shown in the example figures described below, where template layer 150 or 155 may be used in place of template layer 140 as desired. Those of ordinary skill in the art readily appreciate that the optoelectronic device 100' of FIG. 3B can further be formed in the same manner and that it will be within the spirit and scope of the present invention. Furthermore, the following description of device 100 applies equally to devices 100"-100"""' of FIGS. 3A-3H. The semiconductor contact layer 160 may be deposited in some embodiments, for example, to provide a cap on the template layer and to allow other layers to be more easily deposited on the template layer, and/or to provide electrical connections in the device 100. Load sub-motion provides better ohmic contact. In some example embodiments, the contact layer 160 may include a semiconductor such as gallium arsenide (GaAs) (eg, having a smaller thickness because it may be less transparent), aluminum gallium arsenide (AlGaAs) (eg, because It can be more transparent with a larger thickness)) or other material, and in some embodiments can be p ^- doped, with a thickness in the range of about 5nm to about 500nm.

Dielectric layer 162 may be deposited on contact layer 160 and/or template layer 140, 150, or 155 in certain embodiments, and may facilitate reflection or scattering of light striking or traveling through template layer 140, 150, or 155 . In some examples, dielectric layer 162 may include, for example, an insulating material (eg, silicon dioxide (SiO ₂ )) having a dielectric constant between the template semiconductor material and 1 . In some embodiments, the dielectric layer 162 may have a thickness of one-quarter wavelength (or multiple quarter-wavelengths) of light intended to be scattered by the textured layer, and allow for a higher thickness than using only a metal layer (described below). ) greater reflectivity. In some embodiments, the dielectric layer may have a lower refractive index n than the template layer 140 , 150 or 155 .

Accordingly, the islands 144 or 152 may form recesses in a layer deposited on the template layer such that in back reflector embodiments, light traveling through the material of the template layer 140, 150, or 155 strikes the surface of the recess and exits the The surface of the recess is reflected off (eg, scattered by the surface of the recess). Some examples are shown in more detail with respect to FIG. 10 .

In some other embodiments, a different material may be deposited on the semiconductor layer 160 or on the template layer 140, 150 or 155 instead of the dielectric layer 162 (if the contact layer 160 is not present). For example, in some embodiments, a transparent conductive oxide (TCO) layer may be deposited to provide enhanced reflectivity similar to that of a dielectric layer, and also provide a barrier between the template layer and a conductive metal layer disposed on the TCO layer. The charge carriers provide a conductive path. In these embodiments, holes may not necessarily be formed in the TCO layer as described for the dielectric layer 162 in FIG. 5 . In some embodiments, a high resistivity transparent (HRT) layer may also be disposed between the TCO layer and the semiconductor layer (eg template layer 140/150/155, emissive layer 110 or absorber layer 108). The HRT layer can reduce the shunting of charge carriers through pin holes in the semiconductor material.

FIG. 5 shows device 100 after holes have been formed in dielectric layer 162 to allow conductive contacts through dielectric layer 162 . In an embodiment having a semiconductor contact layer 160 , such as the example embodiment shown in FIG. 5 , a hole 164 is formed through the dielectric layer 162 from a surface of the dielectric layer 162 to the semiconductor contact layer 160 . In other embodiments without semiconductor contact layer 160 , hole 164 may be formed from the surface of the dielectric layer to template layer 140 , 150 or 155 .

In some embodiments, the holes 164 are formed by etching using an etching process. The etching process can be performed using any suitable technique that is available.

In some example embodiments, the specific pattern of holes 164 in the dielectric layer 162 may be provided by a mask (eg, a photoresist/etch mask). 6A shows an example of a top view of a mask pattern 165 in which a hole 164 is provided in a dielectric layer 162, wherein the hole is a circular hole 166 with an approximately circular cross-section (approximately circular in the top view of FIG. 6A ). ). FIG. 6B shows another example of a top view of a mask pattern 167 providing holes 164 in the dielectric layer 162, wherein the holes are linear grooves. As shown, one or more grooves 168 may intersect one or more other grooves 169 . As shown, the grooves may be positioned approximately parallel and/or perpendicular to each other, or may be positioned at various other angles in other embodiments. Non-linear or irregular grooves may be used in other embodiments.

In FIG. 7 , optoelectronic device 100 has been further formed by depositing a reflective back metal layer 170 on dielectric layer 162 , providing an example of textured layer 180 . The metal layer 170 includes metal that effectively reflects light. For example, in some embodiments, metal layer 170 may include gold, silver, copper, or other reflective metals, derivatives thereof, and/or combinations thereof. Deposition of metal layer 170 provides an approximately flat surface opposite template layer 140 , 150 or 155 . In some embodiments, layer 140, 150, or 155 has been etched prior to subsequent processing steps. In some embodiments, the metal layer 170 may have an average thickness in a range of about 70 nm to about 10 μm. Metal layer 170 material is also deposited into holes 164 such that conductive contacts are formed between metal layer 170 and semiconductor contact layer 160, or between metal layer 170 and template layer 140, 150 or 155 (no contact is present). layer 160). In some other embodiments, metal layer 170 may be deposited on template layer 140, 150, or 155 without dielectric layer 162 and/or semiconductor contact layer 160 being deposited between the metal layer and the template layer.

In FIG. 8, photovoltaic cell 120 is shown reversed after the lift-off process has removed some of the layers shown in the previous steps in FIGS. 2-7. Once the epitaxial layers have been formed for the PV device 100 as shown in FIG. 180) may be separated from the substrate 101 and any buffer layer 102 during the ELO process.

In one example, photovoltaic device 100 may be exposed to an etching solution in order to etch sacrificial layer 104 and separate cell 120 from growth wafer 101 during an epitaxial lift off (ELO) process. Figure 8 shows the cell 120 in its resulting orientation, where the front of the cell 120 is oriented on top of the cell where light strikes and enters the cell. Thus, the textured layer 180 acts as a back reflector at a location farther from the front of the cell 120 than the p-n junction formed by the absorber and emitter layers. Once separated, cell 120 may be further processed to form various photovoltaic devices, including photovoltaic cells and modules. For example, a metal contact 190 may be deposited on the front contact layer 105 .

Figure 9 shows a cross-sectional view of an alternative embodiment 120' In this example, during layer deposition, some conductive contacts 194 may be deposited on the semiconductor contact layer 160', or on the template layer 140'/150'/155' if the contact layer 160' is not present. In some embodiments, layer 140', 150' or 155' has been etched prior to subsequent processing steps. Dielectric layer 162' is deposited over contacts 194 and semiconductor contact layer 160'. A metal contact layer 170' is deposited on the dielectric layer 162'. The device is then flipped to the orientation shown in Figure 9 after ELO or similar process.

Conductive contacts 194 are shown in cross-section and may extend into or out of the plane of FIG. 9 to one or more of the contacts routed through dielectric layer 162' to metal contact layer 170'. location (not shown). For example, in some embodiments, contacts 194 may be configured similar to recesses 168 and 169 of mask pattern 167 shown in FIG. or more connection nodes (e.g., similar to node 196 shown in FIG. Location outside of battery 120'. Embodiments that provide metal contacts 194 can avoid etching holes in the dielectric layer, saving processing steps in forming cell 120'.

FIG. 10 shows a diagram illustrating a portion 200 of the photovoltaic cell 120 of FIG. 8 and wherein light is received through the textured layer 180 acting as a back reflector. Active layer or region 202 is disposed on textured reflective layer 180 . For example, active layer 202 may be a solar cell active region, such as emissive layer 110 and/or absorber layer 108 . One or more other layers 204 may also be disposed between the active layer 202 and the textured layer 180 in some embodiments.

Light 206 has traveled into photovoltaic cell 120 and has been absorbed by the upper layers. This light 206 emerges from the active layer 202 and strikes the front surface 210 of the textured layer 180 . Light 206 passes through the transparent material of template layer 140 , 150 or 155 . In some embodiments, layer 140, 150, or 155 has been etched prior to subsequent processing steps. Some of the photons 206 may strike the surface of the dielectric layer 162 and be reflected from the layer. Other photons 206 may pass through the dielectric layer 162 and may strike the surface of the back metal layer 170 and be reflected from this layer. The reflected photons are directed back through template layer 140, 150, or 155 as indicated by arrow 212 and then into active layer 202, where they can "bounce around" and can be captured by absorbing layer 108 and emitting layer 110, and further ground to generate current in the battery.

Islands 144 of template layer 140 (or islands 152 of template layer 150 , or islands 156 of template layer 155 ) create recesses 172 in dielectric layer 162 and back metal layer 170 . This creates a randomized, roughened and angular front surface of the dielectric layer 162 and the back metal layer 170 . Textured layer 180 diffuses or scatters unabsorbed photons that pass through active layer 202 . The texture of the textured layer 180 can provide new angles for incident photons, some of which can be redirected back through the template layer 140, 150 or 155 and towards the interior of the photovoltaic cell. Although some light may be absorbed by the template layer, much light is redirected to the active layer 202 because photons are scattered and redirected internally. Thus, the different angles on the surface of the textured layer 180 and its recesses 172 thus effectively cause the photons 206 to reflect back into the active layer 202 at random angles to allow a larger number of photons to be recaptured by the active layer and converted into electrical energy, thereby enhancing The light harvesting performance of the cell 120 is improved and the efficiency is increased.

FIG. 11 is a cross-sectional view of another embodiment of a photovoltaic device 300 suitable for providing a textured layer on the front side of the photovoltaic device 300 . Instead of, or in addition to, the aforementioned backside light trapping, a textured layer may be provided for light trapping at the front side of the photovoltaic cell. This allows light striking the front side of the photovoltaic device to be scattered in the device by the textured surface created by the textured layer, increasing light trapping in the device.

Photovoltaic device 300 includes a cell 320 coupled to a growth wafer 301 with an ELO release or sacrificial layer 304 disposed therebetween. In some embodiments, one or more buffer layers 302 may be formed on the growth wafer 301 to initiate formation of the photovoltaic device 300 . The layers of the photovoltaic cell 320 can be deposited on the sacrificial layer 304, which in some embodiments can include the back semiconductor contact layer 312, the emitter layer 310 on the back contact layer 312, the absorber layer 308 on the emitter layer 310 ( or the emissive layer 310 on the absorber layer 308), the front window layer or passivation layer 306 on the absorber layer 308, and the base layer 305 disposed on the window layer 306 for texturing.

In some embodiments, the back contact layer 312 may include a non-metallic Group III-V compound semiconductor, such as gallium arsenide.

The base layer 305 for texturing is similar to the base layer 112 described above with reference to FIG. 1 . For example, base layer 305 provides a first layer upon which a template layer is deposited for texturing purposes, and may facilitate island formation, for example by having a different composition (eg, different lattice parameters) than the template layer.

In other embodiments, the device 300 is not grown on the sacrificial layer structure or the ELO release layer structure as shown. For example, in other embodiments, device 300 is not included with an ELO lift-off procedure and is grown on a substrate without sacrificial layer 104 or buffer layer 302 .

12 is a cross-sectional view of a photovoltaic device 300 comprising a deposition of a template layer 340 on a base layer 305 according to an embodiment used as a textured layer for the front-side light-harvesting layer. Template layer 340 may be created using an island growth process and provide islands 344 for texturing one or more surfaces of the template layer to induce light reflection and scattering in the device, increasing light trapping. Some embodiments may include a wetting layer 342, which is similar to the wetting layer described above. In other embodiments, there is no island growth in layer 340, but instead the template layer has compositional inhomogeneity and the subsequent etch process removes some materials faster than others. This is also similar to the situation described above for Figure 3C. In some embodiments, layer 340 has been etched prior to subsequent processing steps.

In FIG. 13 , optoelectronic device 300 has been further formed by depositing layers on template layer 340 . In some embodiments, an optional semiconductor contact layer 360 is deposited on the template layer 340 as in the example shown in FIG. 13 .

An anti-reflective coating (ARC) 362 may be deposited on the semiconductor contact layer (if present) or on the template layer 340 (if the contact layer 360 is not present). The ARC layer 362 includes a dielectric material that allows light to pass through while preventing light from being reflected from the surface of the ARC layer 362 . In some implementations, the ARC layer 362 may include multiple layers.

In an ELO embodiment, cell 320 (including layers 340, 360, and 362) may be removed from ELO layers 301, 302, and 304 using an ELO process. After removal, the battery 320 retains its orientation shown in FIGS. 11-13 and is not flipped in orientation with respect to the backside reflector embodiment described above. In other embodiments, no ELO process is used for battery 320 .

Layers 340 , 360 and 362 provide a frontside light-harvesting textured layer 380 . The frontside location of the textured layer 380 allows it to receive light striking the device 300 and scatter the light into the underlying layer of the device 300 at different angles due to the textured, randomized nature of the islands in the template layer 340 s surface. This strips away light trapping as photons bounce within the underlying layer, allowing more photons to be absorbed to generate current.

In other embodiments of devices 100 and 300, other layer arrangements, doping arrangements, layer thicknesses, etc. may be used. For example, an emissive layer may be deposited on an absorbing layer in some embodiments.

Various embodiments of optoelectronic devices and methods for providing such devices described herein may provide a textured layer comprising islands created to allow the textured layer to increase light trapping. The disclosed embodiments may also provide advantages over previous light harvesting layer formation techniques, including greater flexibility, reduced cost, and increased layer growth rates, saving time and expense in fabricating devices.

While the invention has been described in terms of the illustrated embodiments, those of ordinary skill in the art will readily appreciate that variations can be made from the embodiments and will remain within the spirit and scope of the invention. Accordingly, many modifications can be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims (22)

1. a kind of photoelectric device at least one texturizing surfaces, at least one texturizing surfaces include by executing The method of following steps is made：

The semiconductor layer of photoelectric device described in epitaxial growth in growth substrates；

The semiconductor layer is exposed to etch process to form at least one texturizing surfaces on the semiconductor layer； With

The photoelectric device is removed from the growth substrates.

2. photoelectric device according to claim 1, wherein it includes executing to remove the photoelectric device from the growth substrates Extension removes (ELO) technique.

3. photoelectric device according to claim 1, wherein the etch process is lost by the chemistry based on liquid or solution Agent is carved to complete.

4. photoelectric device according to claim 1, wherein etch process pass through gas etch, laser-induced thermal etching, plasma One or more of etching or ion(ic) etching are completed.

5. photoelectric device according to claim 1, wherein at least one texturizing surfaces are configured as that light is caused to dissipate It penetrates.

6. photoelectric device according to claim 5, wherein at least one texturizing surfaces be configured as making photon with Random angles scatter.

7. photoelectric device according to claim 1, wherein the semiconductor layer includes in gallium, aluminium, indium, phosphorus, nitrogen or arsenic It is at least one or more of.

8. photoelectric device according to claim 1 further includes in being deposited below at least one texturizing surfaces One or more：

Dielectric layer,

Transparent conductive oxide (TCO) layer,

Anti-reflective coating, or

Reflective metallic.

9. photoelectric device according to claim 1, wherein at least one texturizing surfaces are than the photoelectric device P-n junction further from the photoelectric device front side position back reflecting layer a part.

10. photoelectric device according to claim 1, wherein at least one texturizing surfaces are than the photoelectric device P-n junction closer to the photoelectric device front side position front window layer a part.

11. photoelectric device according to claim 1, wherein the photoelectric device is a part for solar cell or shines A part for diode.

12. a kind of method for providing at least one veining layer in the opto-electronic device, the method includes：

The semiconductor layer of photoelectric device described in epitaxial growth in growth substrates；

The semiconductor layer is exposed to etch process to form at least one texturizing surfaces on the semiconductor layer； With

The photoelectric device is removed from the growth substrates.

13. according to the method for claim 12, wherein it includes that execution is outer to remove the photoelectric device from the growth substrates Prolong stripping (ELO) technique.

14. according to the method for claim 12, wherein the etch process passes through the chemical etching based on liquid or solution Agent is completed.

15. method as claimed in claim 12, wherein etch process pass through gas etch, laser-induced thermal etching, plasma etching Or one or more of ion(ic) etching is completed.

16. according to the method for claim 12, wherein at least one texturizing surfaces are configured as causing light scattering.

17. according to the method for claim 16, wherein at least one texturizing surfaces be configured such that photon with Random angles scatter.

18. according to the method for claim 12, wherein the semiconductor layer include in gallium, aluminium, indium, phosphorus, nitrogen or arsenic extremely It is few one or more.

19. further including according to the method for claim 12, in being deposited below at least one texturizing surfaces It is one or more：

Dielectric layer,

Transparent conductive oxide (TCO) layer,

Anti-reflective coating, or

Reflective metallic.

20. according to the method for claim 12, wherein at least one texturizing surfaces are than the photoelectric device The part in the back reflecting layer that p-n junction is positioned further from the front side of the photoelectric device.

21. according to the method for claim 12, wherein at least one texturizing surfaces are than the photoelectric device A part for the front window layer that p-n junction is positioned closer to the front side of the photoelectric device.

22. according to the method for claim 12, wherein the photoelectric device is a part or luminous two for solar cell A part for pole pipe.