CN108550579A - Three-dimensional storage and its manufacturing method - Google Patents
Three-dimensional storage and its manufacturing method Download PDFInfo
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- CN108550579A CN108550579A CN201810466713.5A CN201810466713A CN108550579A CN 108550579 A CN108550579 A CN 108550579A CN 201810466713 A CN201810466713 A CN 201810466713A CN 108550579 A CN108550579 A CN 108550579A
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- raceway groove
- groove hole
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
A kind of three-dimensional storage of present invention offer and its manufacturing method, the three-dimensional storage includes substrate, form the alternately stacked conductive layer and insulating layer in direction on edge and the substrate transverse over the substrate, the raceway groove hole of the alternately stacked conductive layer and insulating layer is run through on edge with the direction of the substrate transverse, and the storage string being formed in the raceway groove hole；The storage string includes the charge storage layer and channel layer sequentially formed along the direction in side wall to the axle center in the raceway groove hole, and there is the channel layer p-type doped region, the p-type doped region to be in direct contact with the substrate, and the substrate is p-substrate.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of three-dimensional memory structure and preparation method thereof, especially
It is a kind of preparation process in raceway groove hole.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, a variety of different three-dimensional memory structures come into being, such as 3D NOR (3D or non-) flash memories and 3D NAND (3D with non-) dodge
It deposits.
The storage unit of 3D flash memories includes the conductive layer and interlayer insulating film and break-through conductive layer and interlayer of alternating deposit
The vertical-channel hole (hereinafter referred to as raceway groove hole) of insulating layer.In raceway groove hole by PECVD, HDPCVD, UHVCVD, MOCVD,
The techniques such as MBE, ALD are formed with charge storage layer.Charge storage layer includes tunnel insulation layer, electric charge capture layer and charge barrier
Layer.Tunnel insulation layer plays the energy potential barrier layer of charge F-N tunnellings, can be formed by silica.Electric charge capture layer can be with
It is the nitride layer that can capture charge.Electric charge barrier layer, which rises, prevents the charge being stored in electric charge capture layer to be moved to grid
Effect, can be formed by silica.The charge being made of tunnel insulation layer, electric charge capture layer and electric charge barrier layer is deposited below
Reservoir is referred to as ONO layer.
In general, after forming raceway groove hole, need for example, by selective epitaxial growth in raceway groove hole bottom growing single-crystal silicon
To form bottom selection transistor.
Invention content
The technical problems to be solved by the invention
In the case where manufacturing storage unit using the above method, due to the epitaxial growth technology not only cost of monocrystalline silicon
Height, and to be difficult to safeguard, therefore improve the manufacturing cost and technology difficulty of three-dimensional storage.
The present invention completes to solve the above-mentioned problems, and its purpose is to provide one kind without in raceway groove hole bottom selectivity
The three-dimensional storage and its manufacturing method of epitaxial growth monocrystalline silicon.
Solve technological means used by technical problem
The three-dimensional storage of the present invention includes substrate, and the edge and the direction of the substrate transverse formed over the substrate is handed over
For the conductive layer and insulating layer of stacking, run through the alternately stacked conductive layer and insulating layer along with the direction of the substrate transverse
Raceway groove hole, and the storage string that is formed in the raceway groove hole；The storage string includes the side wall along the raceway groove hole to axis
The charge storage layer and channel layer that the direction of the heart sequentially forms, the channel layer have p-type doped region, the p-type doped region and institute
It states substrate to be in direct contact, the substrate is p-substrate.
In at least embodiment of the present invention, the substrate is p-type substrate.
In at least embodiment of the present invention, formed in the side of the p-type substrate far from the storage string
There is peripheral circuit layer.
In at least embodiment of the present invention, it is formed between the peripheral circuit layer and the p-type substrate
Interconnection layer.
In at least embodiment of the present invention, the p-type doped region is for constituting bottom selection transistor.
In at least embodiment of the present invention, the charge storage layer is in direct contact with the substrate.
In at least embodiment of the present invention, the charge storage layer includes that the side wall along the raceway groove hole arrives axle center
Electric charge barrier layer, electric charge capture layer and the tunnel insulation layer that direction sequentially forms, the electric charge barrier layer and the substrate are direct
Contact.
The manufacturing method of three-dimensional storage of the present invention includes：Substrate is provided, the substrate is p-substrate；In the lining
On bottom formed by the first insulating layer and second insulating layer it is alternately laminated made of laminated body；Formed along with the substrate transverse
At least one raceway groove hole of the laminated body is run through in direction；Charge storage layer and channel layer are sequentially formed in the raceway groove hole；
P-type doped region is formed in the channel layer, which is in direct contact with the substrate.
In at least embodiment of the present invention, by thermal diffusion to the channel layer implanted dopant to form the p-type
Doped region.
In at least embodiment of the present invention, by carrying out p-type ion implanting to the channel layer to form the p-type
Doped region.
In at least embodiment of the present invention, the step of forming the raceway groove hole, further includes：It is used for over the substrate
The position for forming raceway groove hole forms etching barrier layer；After forming raceway groove pore structure on the etching barrier layer, the quarter is removed
Lose barrier layer.
In at least embodiment of the present invention, the step of forming the raceway groove hole, further includes：Form first part's stacking
Body forms first part's raceway groove hole in first part's laminated body, and etching resistance is formed in first part's raceway groove hole
Barrier obtains the stepped construction with etching barrier layer；Second part laminated body is formed in the stepped construction, described the
The top in first part's raceway groove hole forms second part raceway groove hole in two part laminated bodies, and the etching barrier layer is made to reveal
Go out；The etching barrier layer is removed, first part's raceway groove hole and second part raceway groove hole is made to constitute the raceway groove hole.
In at least embodiment of the present invention, the substrate is p-type substrate.
In at least embodiment of the present invention, the p-type doped region is for constituting bottom selection transistor.
In at least embodiment of the present invention, the etching barrier layer is alumina layer.
Invention effect
According to the present invention, p-type doping is carried out using p-substrate, and by the channel layer to raceway groove hole bottom, to replace
It is formed after raceway groove hole CH and constitutes bottom selection transistor (BSG) in the raceway groove hole bottoms CH selective epitaxial growth monocrystalline silicon, from
And it simplifies technique and reduces cost.
In addition, by being, for example, aluminium oxide forming NO heaps prestack to form the position formation in raceway groove hole on the surface of a substrate
The raceway groove hole etching barrier layer of layer, and can prevent from serving as a contrast by the raceway groove hole etching barrier layer removal after the completion of raceway groove hole etches
Bottom surface becomes out-of-flatness because raceway groove hole etches, and is conducive to the film thickness monitoring in subsequent technique, and can eliminate storage unit it
Between individual difference.
In addition, peripheral circuit, interconnection can further be arranged below substrate as substrate by using p-type
The structures such as layer.
Description of the drawings
Fig. 1 is the figure of the structure for the three-dimensional storage for being denoted as reference example.
Fig. 2 is the figure for the structure for indicating the three-dimensional storage involved by embodiment of the present invention 1.
Fig. 3 to Fig. 6 is the technological process for the manufacturing method for indicating the three-dimensional storage involved by embodiment of the present invention 1
Figure.
Fig. 7 to Fig. 9 is section of the three-dimensional storage in different manufacturing processes indicated involved by embodiment of the present invention 2
Figure.
Figure 10 is the figure of the structure for the three-dimensional storage for indicating the variation of the present invention.
Specific implementation mode
In the following, being carried out to the three-dimensional storage of the present invention and its embodiment and its variation of manufacturing method based on attached drawing
Illustrate, identical label is marked to same or equivalent component, position to illustrate in the various figures.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means and the relevant a certain feature of at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in different location in this specification or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
It should be noted that in order to simplify herein disclosed statement, to help to one or more inventive embodiments
Understanding, above in the description of the embodiment of the present application, sometimes by various features merger to one embodiment, attached drawing or to it
Description in.But what this disclosure method was not meant to refer in the required aspect ratio claim of the application object
Feature is more.In fact, the feature of embodiment will be less than whole features of the single embodiment of above-mentioned disclosure.
Fig. 1 is shown as the structure of the storage unit of the three-dimensional storage of reference example.When manufacturing the storage array, use
Following steps：
(1) substrate 101 is provided；
(2) the alternately laminated grid being for example made of silicon nitride reserves layer 102 and for example by silica structure on substrate 101
At interlayer insulating film 103 come formed NO stack；
(3) raceway groove hole CH is formed along being performed etching to NO stackings perpendicular to the direction of substrate 101；
(4) bottom selection transistor 201 is formed in the raceway groove hole bottoms CH selective epitaxial growth monocrystalline silicon；
(5) barrier layer 202 is sequentially formed along raceway groove hole CH side walls, electric charge capture layer 203, tunnel layer 204 are used as electricity
Lotus accumulation layer；
(6) it is further formed channel layer 205 in tunnel layer 204 and 201 surface of bottom selection transistor；
(7) tunnel oxide is filled, top channel layer is formed, and p-type doping is carried out to top channel layer to form drain electrode
206；
(8) removal grid is reserved layer 102 and is replaced with metal layer, is used as grid layer.
However it needs to form bottom in the raceway groove hole bottoms CH selective epitaxial growth monocrystalline silicon using above-mentioned manufacturing method
Selection transistor (BSG).Present inventor is to reduce cost and technology difficulty, is improved the manufacturing method, is carried
Go out following implementation.
Embodiment 1
Fig. 2 is the figure for the structure for indicating the three-dimensional storage involved by embodiment of the present invention 1.
As shown in Fig. 2, be formed on substrate 101a by grid reserve layer 102 and interlayer insulating film 103 it is alternately laminated and
At NO stack.Grid is reserved layer 102 and is for example made of silicon nitride, and interlayer insulating film 103 is for example made of silica.Grid is pre-
It stays layer 102 that can remove in the subsequent process, and replaces with metal and be used as grid layer.Along perpendicular to the direction of substrate 101a
(stacking direction) is formed at least one raceway groove hole CH.Grid reserves layer 102 and the material of interlayer insulating film 103 is without being limited thereto,
Can also be other insulating materials.
In the CH of raceway groove hole, from side wall to axle center be sequentially formed with barrier layer 202, electric charge capture layer 203, tunnel layer 204, with
And channel layer 205.It is formed with drain electrode 206 at the top of the CH of raceway groove hole.204 structure of barrier layer 202, electric charge capture layer 203 and tunnel layer
At charge storage layer.The charge storage layer is in direct contact with substrate 101a.Channel layer 205 is, for example, polysilicon layer.Drain electrode 206
It can such as be formed by carrying out p-type doping to the channel layer 205 at the top of the CH of raceway groove hole.Hereafter also by the structure in the CH of raceway groove hole
Referred to as storage string.
Present embodiment the difference is that, substrate 101a does not use monocrystalline substrate, but p-substrate.Such as it can
To be p-type Si substrates, p-type Ge substrate, p-type SiGe substrate etc..In addition, to the portion positioned at the raceway groove hole bottoms CH of channel layer 205
Divide and carried out p-type doping, obtains p-type doped region 2051.The p-type doped region 2051 is connected with substrate 101a.
The manufacturing method of the three-dimensional storage of present embodiment is illustrated below with Fig. 3 to Fig. 6.
First, it as shown in figure 3, providing the substrate 101a of p-type, and is formed on substrate 101a and 102 (example of layer is reserved by grid
Such as the first insulating layer or sacrificial layer) and interlayer insulating film 103 (such as second insulating layer) it is alternately laminated made of NO stack.P-type
Substrate 101a can for example be formed by doping in situ, can also be by carrying out p-type ion implanting or thermal diffusion to substrate
To be formed.Grid is reserved layer 102 and is for example made of silicon nitride, and interlayer insulating film 103 is for example made of silica.Grid reserves layer
102 and the formation process of interlayer insulating film 103 can use thin film deposition processes, including but not limited to chemical vapour deposition technique
(CVD), one or more combinations in physical vaporous deposition (PVD), atomic layer deposition method (ALD) and electroplating technology.
Then, as shown in figure 4, etching the NO heaps for reserving layer 102 and interlayer insulating film 103 in grid by dry/wet
It is stacked on to form at least one raceway groove hole CH (2, but an only example are shown in figure).
Then, it as shown in figure 5, in the CH of raceway groove hole, is sequentially formed along from the direction in side wall to the axle center of raceway groove hole CH
Barrier layer 202, electric charge capture layer 203, tunnel layer 204 and channel layer 205.Electric charge capture layer 203 plays substantive database
Effect, tunnel layer 204 play the energy potential barrier layer of charge F-N tunnellings, and barrier layer 202, which is risen, to prevent from being stored in electric charge capture layer
Charge in 203 is moved to the effect of grid.Barrier layer 202, electric charge capture layer 203 and tunnel layer 204 constitute charge storage
Layer.Electric charge capture layer 203 can capture the nitride layer of charge, and tunnel layer 204 can be formed by silicon oxide layer.Ditch
Channel layer 205 can for example be formed by polysilicon layer.In some embodiments, tunnel oxide, shape are filled into channel layer 205
At separation layer 207.
Then, as shown in fig. 6, carrying out p-type doping to the part positioned at the bottom of raceway groove hole CH of channel layer 205 to be formed
P-type doped region 2051.In present embodiment, thermal expansion is carried out by the part positioned at the bottom of raceway groove hole CH to channel layer 205
It dissipates to inject boron, to obtain p-type doped region 2051.Certainly the present invention is not limited to which, such as can also increase to raceway groove
The channel layer 205 of the hole bottoms CH carries out the step of p-type ion implanting.Hereafter the step of, is identical as previous technique, such as can be after
Continue and form drain electrode etc. at top, which is not described herein again.
According to the present embodiment, using p-substrate, and p-type doped region 2051 is further formed to channel layer, makes itself and p
Type substrate is connected.P-type doped region 2051 can constitute bottom instead of selective epitaxial growth in the monocrystalline silicon of the raceway groove hole bottoms CH
Portion's selection transistor.Therefore, it is possible to be omitted in the technique of raceway groove hole bottom selective epitaxial growth monocrystalline silicon, so as to simplify work
Skill simultaneously reduces cost.
Embodiment 2
Fig. 7 to Fig. 9 is section of the three-dimensional storage in different manufacturing processes indicated involved by embodiment of the present invention 2
Figure.
In the embodiment 1, raceway groove hole is formed by etching, therefore after etching, the surface of substrate 101a is as shown in Figure 4
Become out-of-flatness.Since the selective epitaxial growth monocrystalline silicon on substrate 101a, this out-of-flatness can be to not rear by the present invention
Continuous technique impacts, such as is difficult to control the film forming thickness of channel layer, and individual can be generated between each storage unit
Deviation.Also, the presence stacked due to NO, it is difficult to eliminate the out-of-flatness of this substrate surface.
For this purpose, in present embodiment, NO heap prestacks are being formed, to form raceway groove on substrate 101a in advance as shown in Figure 7
The position of hole CH forms raceway groove hole etching barrier layer 104.Raceway groove hole etching barrier layer 104 can select to have raceway groove hole etching liquid
There are the material of tolerance, such as aluminium oxide.The already known processes such as photoetching may be used in the formation of raceway groove hole etching barrier layer 104.
It as an example, such as can be with as shown in fig. 7, being initially formed pre- by insulating layer 103 between from level to level and one layer of grid
It stays layer 102 to be laminated laminated body (first part's laminated body), and forms raceway groove hole (first part's raceway groove in the laminated body
Hole) and then form in the raceway groove hole above-mentioned raceway groove hole etching barrier layer 104.
It is reserved there is illustrated the insulating layer 103 between from level to level and one layer of grid in the thickness range of layer 102 and forms raceway groove
The structure of hole etching barrier layer 104.But this is only an example, can select the number of plies of first part's laminated body as needed
With the thickness of raceway groove hole etching barrier layer 104.
Then, the top of structure shown in Fig. 7 forms NO and stacks (second part laminated body) in a manner of same with Fig. 3,
And raceway groove hole (second part raceway groove hole) etching is carried out, obtain structure shown in Fig. 8.Due to raceway groove hole etching barrier layer 104
In the presence of the surface that etching proceeds to raceway groove hole etching barrier layer 104 stops, to protect the substrate 101a of lower section will not be because carving
It loses and is damaged.Raceway groove hole etching barrier layer 104 is removed using wet etching later, exposes the substrate 101a of bottom.Later
Step is identical as Fig. 5 and Fig. 6, and which is not described herein again.
The three-dimensional storage obtained using present embodiment is as shown in figure 9, on the basis of embodiment 1, substrate 101a
Surface it is flat, be conducive to subsequent technique, and the individual difference between storage unit can be eliminated, electric property is more excellent.
Figure 10 shows the structure of three-dimensional storage involved by the variation of the present invention.The variation and embodiment 1 and
Embodiment 2 the difference is that, substrate 101b uses p-type substrate, other structures and embodiment 1 and embodiment party
Formula 2 is identical.The variation is suitable for being arranged below core memory area the structure, i.e. PUC (Periphery of peripheral circuit
Under Core).In other words, peripheral circuit can be further set in the lower section of substrate 101b, i.e. far from the side of storage string
Layer, further can also be arranged interconnection layer between peripheral circuit layer and substrate 101b, the two is connected.This is because monocrystalline
Silicon can not be formed directly on metal layer, and polysilicon does not have this limitation, such as can directly form polycrystalline on the metal layer
Silicon layer can be used as the substrate in core memory area after being adulterated through p-type.
The preferred embodiment of the present invention has been described above in detail.It should be appreciated that the present invention is not departing from its broad sense essence
Various embodiments and deformation may be used in the case of god and range.Those skilled in the art are not necessarily to creative work
It according to the present invention can conceive and make many modifications and variations.Therefore, all those skilled in the art are under this invention's idea
On the basis of existing technology by the available technical solution of logical analysis, reasoning, or a limited experiment, should all belong to
In the protection domain determined by claims of the present invention.
Label declaration
101 substrates
101a substrates
101b substrates
102 grids reserve layer
103 interlayer insulating films
104 raceway groove hole etching barrier layers
201 bottom selection transistors
202 barrier layers
203 electric charge capture layers
204 tunnel layers
205 channel layers
2051 p-type doped regions
206 drain electrodes
207 separation layers
CH raceway grooves hole
Claims (15)
1. a kind of three-dimensional storage, which is characterized in that including substrate, form edge over the substrate and the substrate transverse
The alternately stacked conductive layer and insulating layer in direction, along and the substrate transverse direction through the alternately stacked conductive layer and
The raceway groove hole of insulating layer, and the storage string that is formed in the raceway groove hole；The storage string includes along the side in the raceway groove hole
The charge storage layer and channel layer that the direction in wall to axle center sequentially forms,
There is the channel layer p-type doped region, the p-type doped region to be in direct contact with the substrate,
The substrate is p-substrate.
2. three-dimensional storage as described in claim 1, which is characterized in that
The substrate is p-type substrate.
3. three-dimensional storage as claimed in claim 2, which is characterized in that in the p-type substrate far from the storage
The side of string is formed with peripheral circuit layer.
4. three-dimensional storage as claimed in claim 3, which is characterized in that in the peripheral circuit layer and the p-type
Interconnection layer is formed between substrate.
5. three-dimensional storage as described in claim 1, which is characterized in that
The p-type doped region is for constituting bottom selection transistor.
6. three-dimensional storage as described in claim 1, which is characterized in that the charge storage layer directly connects with the substrate
It touches.
7. three-dimensional storage as claimed in claim 6, which is characterized in that the charge storage layer includes along the raceway groove hole
Electric charge barrier layer, electric charge capture layer and the tunnel insulation layer that the direction in side wall to axle center sequentially forms, the electric charge barrier layer with
The substrate is in direct contact.
8. a kind of manufacturing method of three-dimensional storage, which is characterized in that including：
Substrate is provided, the substrate is p-substrate；
Formed over the substrate by the first insulating layer and second insulating layer it is alternately laminated made of laminated body；
It is formed along at least one raceway groove hole for running through the laminated body with the direction of the substrate transverse；
Charge storage layer and channel layer are sequentially formed in the raceway groove hole；
P-type doped region is formed in the channel layer, which is in direct contact with the substrate.
9. the manufacturing method of three-dimensional storage as claimed in claim 8, which is characterized in that
The p-type doped region is formed to the channel layer implanted dopant by thermal diffusion.
10. the manufacturing method of three-dimensional storage as claimed in claim 8, which is characterized in that
By carrying out p-type ion implanting to the channel layer to form the p-type doped region.
11. the manufacturing method of three-dimensional storage as claimed in claim 8, which is characterized in that
The step of forming the raceway groove hole further include：The position for being used to form raceway groove hole over the substrate forms etch stopper
Layer；
After forming raceway groove pore structure on the etching barrier layer, the etching barrier layer is removed.
12. the manufacturing method of three-dimensional storage as claimed in claim 11, which is characterized in that
The step of forming the raceway groove hole further include：First part's laminated body is formed, is formed in first part's laminated body
First part's raceway groove hole forms etching barrier layer in first part's raceway groove hole, obtains the stacking with etching barrier layer
Structure；
Second part laminated body, first part's raceway groove in the second part laminated body are formed in the stepped construction
The top in hole forms second part raceway groove hole, and the etching barrier layer is made to expose；
The etching barrier layer is removed, first part's raceway groove hole and second part raceway groove hole is made to constitute the raceway groove
Hole.
13. the manufacturing method of three-dimensional storage as claimed in claim 8, which is characterized in that
The substrate is p-type substrate.
14. the manufacturing method of three-dimensional storage as claimed in claim 8, which is characterized in that
The p-type doped region is for constituting bottom selection transistor.
15. the manufacturing method of three-dimensional storage as claimed in claim 11, which is characterized in that
The etching barrier layer is alumina layer.
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| CN109712990A (en) * | 2019-01-02 | 2019-05-03 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
| CN110379814A (en) * | 2019-06-19 | 2019-10-25 | 长江存储科技有限责任公司 | The production method of three-dimensional storage part and three-dimensional storage part |
| CN111180463A (en) * | 2020-01-03 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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| CN108550579B (en) | 2019-08-30 |
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