CN108540124A - A kind of level shifting circuit - Google Patents

Abstract

A level conversion circuit belongs to the technical field of electronic circuits. It includes a level conversion unit, a first timing control unit and a second timing control unit. On the one hand, the input signal is connected to the input terminal of the first timing control unit, and on the other hand, it is connected to the input terminal of the second timing control unit after inversion; two The timing control unit is used to control the timing of the input signal, and its output terminals are respectively connected to the two input terminals of the level conversion unit; the level conversion unit is used to obtain the first output signal and the second output signal for converting the low-voltage signal into a high-voltage signal . The level conversion circuit provided by the present invention improves the drive capability of the circuit, has the advantages of high conversion rate and simple structure, and at the same time ensures the stability of the level conversion output, and realizes the high-voltage level of high-speed operation without degrading reliability convert.

Description

A level conversion circuit

technical field

The invention belongs to the technical field of electronic circuits, and relates to a level conversion circuit, in particular to a high-voltage level conversion circuit suitable for high-speed operation.

Background technique

The level conversion circuit includes a high-voltage level conversion circuit and a low-voltage level conversion circuit, wherein the high-voltage level conversion circuit converts the low-voltage control signal into a high-voltage control signal to realize the control of the low-voltage logic on the high-voltage power output pole. Generally, according to the polarity of the output high-voltage control signal, the level shifting circuit can be divided into a negative voltage level shifting circuit and a positive voltage level shifting circuit. A typical level conversion circuit receives an input signal through a pair of transistors. However, when the input signal level drops significantly, the driving capability of the driver transistor will deteriorate, and the delay of the circuit will increase. In addition, extreme voltage drops can further cause undesired periodic changes in the output signal, and may even cause the conversion circuit to fail because the input transistor cannot be turned on by the extremely low input signal voltage. Moreover, the conversion speed of the traditional level conversion circuit is relatively slow due to the use of too many high breakdown voltage tubes.

Contents of the invention

In view of the above disadvantages, the present invention provides a level conversion circuit, which can solve the shortcomings of insufficient drive capability and slow conversion speed in traditional level conversion circuits, and realize high-speed operation without degraded reliability.

Technical scheme of the present invention is:

A level conversion circuit, comprising a level conversion unit 110, a first timing control unit 100 and a second timing control unit 120,

The level conversion unit 110 includes an inverter INV1, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a Three PMOS transistors MP3, fourth PMOS transistors MP4, fifth PMOS transistors MP5, sixth PMOS transistors MP6, seventh PMOS transistors MP7, eighth PMOS transistors MP8, first capacitor C1 and second capacitor C2,

The source of the third PMOS transistor MP3 is used as the first input end of the level conversion unit 110 to connect to the output end of the first timing control unit 100, and its gate is connected to the gate of the fourth PMOS transistor MP4 and grounded to VSS, Its drain is connected to the gates of the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 and grounded to VSS after passing through the first capacitor C1;

The source of the fourth PMOS transistor MP4 is used as the second input end of the level conversion unit 110 and connected to the output end of the second timing control unit 120, and its drain is connected to the third NMOS transistor MN3 and the fifth NMOS transistor MN5. The gate is grounded to VSS after passing through the second capacitor C2;

The source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, and its drain is connected to the gates of the sixth PMOS transistor MP6, the eighth PMOS transistor MP8 and the eighth NMOS transistor MN8 as a first node;

The source of the fourth NMOS transistor NM4 is connected to the drain of the sixth NMOS transistor MN6, and the drain is connected to the gates of the fifth PMOS transistor MP5, the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 as a second node;

The drain of the sixth PMOS transistor MP6 is connected to the second node, and the drain of the fifth PMOS transistor MP5 is connected to the first node;

The drain of the seventh NMOS transistor MN7 is connected to the drain of the seventh PMOS transistor MP7 and serves as the first output end of the level conversion circuit, and the drain of the eighth NMOS transistor MN8 is connected to the drain of the eighth PMOS transistor MP8 and serves as the second output terminal of the level conversion circuit;

The sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are grounded; the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7 and the eighth PMOS transistor The source of MP8 is connected to the high power supply voltage VDDH;

The input terminal of the level conversion circuit is connected to the input terminal of the first timing control unit 100 and the input terminal of the inverter INV1, and the output terminal of the inverter INV1 is connected to the second timing control unit 120 input terminal.

Specifically, the first timing control unit 100 includes a first NMOS transistor MN1 and a first PMOS transistor MP1, the gates of the first NMOS transistor MN1 and the first PMOS transistor MP1 are interconnected and serve as the first timing control unit 100 The drains are also interconnected and serve as the output of the first timing control unit 100, the source of the first PMOS transistor MP1 is connected to the low power supply voltage VDD, and the source of the first NMOS transistor MN1 is grounded to VSS;

The second timing control unit 120 includes a second NMOS transistor MN2 and a second PMOS transistor MP2, the gates of the second NMOS transistor MN2 and the second PMOS transistor MP2 are interconnected and serve as the input end of the second timing control unit 120 , the drains of which are also interconnected and serve as the output terminal of the second timing control unit 120, the source of the second PMOS transistor MP2 is connected to the low power supply voltage VDD, and the source of the second NMOS transistor MN2 is grounded to VSS.

Specifically, the power rail of the inverter INV1 is from the low power supply voltage VDD to the ground level VSS.

Specifically, a ninth PMOS transistor MP9 is also provided between the drain of the fifth PMOS transistor MP5 and the first node, the source of the ninth PMOS transistor MP9 is connected to the drain of the fifth PMOS transistor MP5, and the drain of the ninth PMOS transistor MP9 is connected to the drain of the fifth PMOS transistor MP5. The pole is connected to the first node, and its gate is connected to the drain of the fourth PMOS transistor MP4;

A tenth PMOS transistor MP10 is also arranged between the drain of the sixth PMOS transistor MP6 and the second node, the source of the tenth PMOS transistor MP10 is connected to the drain of the sixth PMOS transistor MP6, and the drain is connected to the The gate of the second node is connected to the drain of the third PMOS transistor MP3.

Specifically, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the first PMOS transistor MP1, the second PMOS transistor The tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 are low breakdown voltage tubes, and the seventh NMOS tube MN7, the eighth NMOS tube MN8, the fifth PMOS tube MP5, the sixth PMOS tube MP6, and the seventh PMOS tube The transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are high breakdown voltage transistors.

The beneficial effects of the present invention are as follows: the drive capability of the circuit is improved, the advantages of high conversion rate and simple structure are ensured, and at the same time, the stability of the level conversion output is ensured, and the high-voltage level conversion of high-speed operation is realized without degraded reliability .

Description of drawings

FIG. 1 is a schematic structural diagram of a level conversion circuit proposed in Embodiment 1 of the present invention.

FIG. 2 is an operation timing diagram of a level conversion circuit proposed in Embodiment 1 of the present invention.

FIG. 3 is a schematic structural diagram of a level conversion circuit proposed in Embodiment 2 of the present invention.

Detailed ways

The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

The level conversion circuit proposed by the present invention is used to convert a low-voltage control signal into a high-voltage control signal, including a level conversion unit 110 and a first timing control unit 100 and a second timing control unit 120 coupled to the level conversion unit, The devices used in the present invention include high breakdown voltage PMOS transistors, low breakdown voltage PMOS transistors, high breakdown voltage NMOS transistors and low breakdown voltage NMOS transistors.

Embodiment one

As shown in FIG. 3 , the level conversion unit 110 includes an inverter INV1, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor The tube MN8, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the first capacitor C1 and the second capacitor C2, the The source of the three PMOS transistor MP3 is used as the first input end of the level conversion unit 110 to connect to the output end of the first timing control unit 100, its gate is connected to the gate of the fourth PMOS transistor MP4 and grounded to VSS, and its drain is connected to the first timing control unit 100. The gates of the four NMOS transistors MN4 and the sixth NMOS transistor MN6 are grounded to VSS after passing through the first capacitor C1; the source of the fourth PMOS transistor MP4 is connected to the second timing control unit 120 as the second input terminal of the level conversion unit 110 The output terminal, the drain of which is connected to the gates of the third NMOS transistor MN3 and the fifth NMOS transistor MN5 and grounded to VSS after passing through the second capacitor C2; the source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, which The drain is connected to the gates of the sixth PMOS transistor MP6, the eighth PMOS transistor MP8 and the eighth NMOS transistor MN8 as the first node; the source of the fourth NMOS transistor NM4 is connected to the drain of the sixth NMOS transistor MN6, and the drain Connect the gates of the fifth PMOS transistor MP5, the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 as the second node; the drain of the sixth PMOS transistor MP6 is connected to the second node, and the drain of the fifth PMOS transistor MP5 is connected to the second node. One node; the drain of the seventh NMOS transistor MN7 is connected to the drain of the seventh PMOS transistor MP7 and used as the first output terminal of the level conversion circuit to output the first output signal po, and the drain of the eighth NMOS transistor MN8 is connected to the eighth PMOS The drain of the transistor MP8 is used as the second output terminal of the level conversion circuit to output the second output signal no; the sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are grounded ; The sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to the high power supply voltage VDDH. The input end of the level conversion circuit is connected to the input end of the first timing control unit 100 and the input end of the inverter INV1 , and the output end of the inverter INV1 is connected to the input end of the second timing control unit 120 .

The first input terminal and the second input terminal of the level conversion unit 110 are used to receive the output signals of the first timing control unit 100 and the second timing control unit 120 . The input signal pi is connected to the input terminal of the first timing control unit 100 , and is inverted by the inverter INV1 in the level conversion unit 110 to become an inverted input signal ni connected to the input terminal of the second timing control unit 120 . The first timing control unit 100 and the second timing control unit 120 are used to control the timing of the input signal pi and the inverted input signal ni, as shown in FIG. 3 , the first timing control unit 100 in this embodiment includes a first NMOS transistor MN1 The gates of the first PMOS transistor MP1, the first NMOS transistor MN1 and the first PMOS transistor MP1 are interconnected and used as the input terminal of the first timing control unit 100, and the drains thereof are also interconnected and used as the first timing control unit 100 The output terminal of the first PMOS transistor MP1 is connected to the low power supply voltage VDD, the source of the first NMOS transistor MN1 is grounded to VSS; the second timing control unit 120 includes the second NMOS transistor MN2 and the second PMOS transistor MP2, the second The gates of the NMOS transistor MN2 and the second PMOS transistor MP2 are interconnected and used as the input end of the second timing control unit 120, and the drains thereof are also interconnected and used as the output end of the second timing control unit 120, and the gate of the second PMOS transistor MP2 The source is connected to the low power supply voltage VDD, and the source of the second NMOS transistor MN2 is grounded to VSS.

Wherein the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the first PMOS transistor MP1, the second PMOS transistor MP2, the The third PMOS transistor MP3 and the fourth PMOS transistor MP4 are low breakdown voltage transistors, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7 and the eighth PMOS transistor Tube MP8 is a high breakdown voltage tube.

The low power supply voltage VDD is a low-level operating voltage for the entire system, the high power supply voltage VDDH is a high-level operating voltage for the entire system, and the ground potential VSS is the ground potential of the entire system. In this embodiment, the driving capability of the input electrode of the level conversion unit 110 is enhanced by the third PMOS transistor MP3 and the fourth PMOS transistor MP4 of the low breakdown voltage PMOS transistor.

FIG. 2 is a timing signal diagram in this embodiment. Case (1): When the levels of the input signal pi and the inverted input signal ni are VSS and VDD respectively and the VDDH level is VDD, the first output signal po and the second output signal no output by the level conversion unit 110 are respectively VDD and VSS. Case (2): When the levels of the input signal pi and the inverted input signal ni are VDD and VSS respectively and the VDDH level is VDD, the first output signal po and the second output signal no output by the level conversion unit 110 are respectively VSS and VDD. Case (3) When the levels of the input signal pi and the inverted input signal ni are VDD and VSS respectively and the VDDH level is a high voltage voltage, the first output signal po and the second output signal no output by the level conversion unit 110 are VSS and VDDH.

In actual use, the voltage value of the high power supply voltage VDDH is generally greater than the voltage value of the low power supply voltage VDD, and the purpose of converting from low voltage to high voltage is achieved by converting the input low power supply voltage VDD into high power supply voltage VDDH; and VDDH is equal to The case of VDD is to shield the output when the external voltage VDDH fluctuates, and at this time the output voltage of the level conversion circuit is not an effective output.

The working principle of this embodiment is: when the levels of the input signal pi and the inverting input type ni are VDD and VSS respectively, the third PMOS transistor MP3 is turned off, the fourth PMOS transistor MP4 is turned on, and the second capacitor C2 stabilizes After voltage, the node h2, which is the connection point between the second capacitor C2 and the drain of the fourth PMOS transistor MP4, becomes high level, that is, the low power supply voltage VDD, and then the third NMOS transistor MN3 and the fifth NMOS transistor MN5 are turned on, so that the sixth The gate voltage of the PMOS transistor MP6 is the ground potential VSS, the sixth PMOS transistor MP6 is turned on, and the connection point between the first capacitor C1 and the drain of the third PMOS transistor MP3, that is, the level of the node h1 ensures that the fourth NMOS transistor is accelerated through coupling feedback. The cutoff of MN4 and the sixth NMOS transistor MN6 turns on the eighth PMOS transistor MP8, and finally the first output signal po is low level VSS, and the second output signal no is high power supply voltage VDDH. The nodes h1 and h2 protect the output NMOS transistors by controlling the gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 to prevent damage to the low breakdown MOS transistors by high voltage. The first timing control unit 100 and the second timing control unit 120 are used to provide an additional strengthening path. The level conversion unit 110 improves the reliability by ensuring the voltage stability of the nodes h1 and h2. The sixth PMOS transistor MP6 and the eighth PMOS transistor The tube MP8, the fifth PMOS tube MP5, and the seventh PMOS tube MP7 form a positive feedback coupling connection, which improves the driving capability and ensures the stability of the level conversion output.

Embodiment two

As shown in Fig. 1, in this embodiment, a ninth PMOS transistor MP9 is also provided between the drain of the fifth PMOS transistor MP5 and the first node, and the source of the ninth PMOS transistor MP9 is connected to the drain of the fifth PMOS transistor MP5. Its drain is connected to the first node, and its gate is connected to the drain of the fourth PMOS transistor MP4; a tenth PMOS transistor MP10 and a tenth PMOS transistor MP10 are also arranged between the drain of the sixth PMOS transistor MP6 and the second node. The source is connected to the drain of the sixth PMOS transistor MP6, the drain is connected to the second node, and the gate is connected to the drain of the third PMOS transistor MP3.

Wherein the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the first PMOS transistor MP1, the second PMOS transistor MP2, the The third PMOS transistor MP3 and the fourth PMOS transistor MP4 are low breakdown voltage transistors, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor The transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are high breakdown voltage transistors.

Compared with Embodiment 1, Embodiment 2, by adding the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 to form a positive feedback structure, makes the switching speed faster, but Embodiment 1 has a simpler structure than Embodiment 2. Circuit configuration.

The NMOS transistor and the PMOS transistor used in the present invention can be one of LDMOS, VDMOS and IGBT, the first capacitor C1 and the second capacitor C2 can be MOS connected capacitors, and the MOSs can be NMOS or PMOS transistors.

To sum up, the level conversion circuit provided by the present invention uses an inverter to invert the input signal pi to obtain an inverted input signal ni, and then the first timing control unit 100 and the second timing control unit 120 respectively control the input signal pi and inverting the timing of the input signal ni, then the first timing control unit 100 and the second timing control unit 120 are coupled to the two input ends of the level conversion unit 110, and the level conversion unit 110 is used to complete the conversion from low level to Compared with the traditional level conversion circuit, the high-level conversion improves the driving ability and reliability of the circuit, and has the advantages of high conversion rate. The timing control unit has a simpler structure, and at the same time ensures the stability of the level conversion output. High-voltage level shifting that enables high-speed operation without degrading reliability.

It is to be understood that the invention is not limited to the precise configuration and components shown above. Various modifications and optimizations can be made to the step sequence, details and operations of the above methods and structures without departing from the protection scope of the claims.

Claims (5)

1. a kind of level shifting circuit, which is characterized in that including level conversion unit (110), the first timing control unit (100) With the second timing control unit (120),

The level conversion unit (110) includes phase inverter (INV1), third NMOS tube (MN3), the 4th NMOS tube (MN4), Five NMOS tubes (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the first capacitance (C1) and the second capacitance (C2),

When the source electrode of third PMOS tube (MP3) connects described first as the first input end of the level conversion unit (110) The output end of sequence control unit (100), grid connect the grid of the 4th PMOS tube (MP4) and ground connection (VSS), drain electrode connection The grid of 4th NMOS tube (MN4) and the 6th NMOS tube (MN6) is simultaneously grounded (VSS) afterwards by the first capacitance (C1)；

When the source electrode of 4th PMOS tube (MP4) connects described second as the second input terminal of the level conversion unit (110) The grid of the output end of sequence control unit (120), drain electrode connection third NMOS tube (MN3) and the 5th NMOS tube (MN5) simultaneously leads to It crosses the second capacitance (C2) and is grounded (VSS) afterwards；

The source electrode of third NMOS tube (MN3) connects the drain electrode of the 5th NMOS tube (MN5), the 6th PMOS tube (MP6) of connection that drains, The grid of 8th PMOS tube (MP8) and the 8th NMOS tube (MN8) and as first node；

The source electrode of 4th NMOS tube (NM4) connects the drain electrode of the 6th NMOS tube (MN6), the 5th PMOS tube (MP5) of connection that drains, The grid of 7th PMOS tube (MP7) and the 7th NMOS tube (MN7) and as second node；

The drain electrode of 6th PMOS tube (MP6) connects the second node, and the drain electrode of the 5th PMOS tube (MP5) connects the first segment Point；

The drain electrode of 7th NMOS tube (MN7) connects the drain electrode of the 7th PMOS tube (MP7) and as the of the level shifting circuit The drain electrode of one output end, the 8th NMOS tube (MN8) connects the drain electrode of the 8th PMOS tube (MP8) and as the level shifting circuit Second output terminal；

5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7) and the 8th NMOS tube (MN8) source electrode connect Ground；5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7) are connected with the source electrode of the 8th PMOS tube (MP8) High power supply voltage (VDDH)；

The input terminal of the level shifting circuit connects the input terminal of first timing control unit (100) and the phase inverter (INV1) input terminal, the output end of the phase inverter (INV1) connect the input terminal of second timing control unit (120).

2. level shifting circuit according to claim 1, which is characterized in that

First timing control unit (100) includes the first NMOS tube (MN1) and the first PMOS tube (MP1), the first NMOS tube (MN1) and the gate interconnection of the first PMOS tube (MP1) and as the input terminal of first timing control unit (100), leakage Pole also interconnects and as the output end of the first timing control monomer (100), and the source electrode of the first PMOS tube (MP1) connects low electricity Source voltage (VDD), the source electrode ground connection (VSS) of the first NMOS tube (MN1)；

Second timing control unit (120) includes the second NMOS tube (MN2) and the second PMOS tube (MP2), the second NMOS tube (MN2) and the gate interconnection of the second PMOS tube (MP2) and as the input terminal of second timing control unit (120), leakage Pole also interconnects and as the output end of second timing control unit (120), and the source electrode of the second PMOS tube (MP2) connects low electricity Source voltage (VDD), the source electrode ground connection (VSS) of the second NMOS tube (MN2).

3. level shifting circuit according to claim 1, which is characterized in that the power rail of the phase inverter (INV1) is low Supply voltage (VDD) arrives ground level (VSS).

4. level shifting circuit according to claim 2 or 3, which is characterized in that the drain electrode of the 5th PMOS tube (MP5) The 9th PMOS tube (MP9) is additionally provided between the first node, the source electrode of the 9th PMOS tube (MP9) connects the 5th PMOS tube (MP5) drain electrode, drain electrode connect the first node, and grid connects the drain electrode of the 4th PMOS tube (MP4)；

It is additionally provided with the tenth PMOS tube (MP10) between the drain electrode and the second node of 6th PMOS tube (MP6), the tenth The source electrode of PMOS tube (MP10) connects the drain electrode of the 6th PMOS tube (MP6), and drain electrode connects the second node, grid connection The drain electrode of third PMOS tube (MP3).

5. level shifting circuit according to claim 4, which is characterized in that first NMOS tube (MN1), the 2nd NMOS Manage (MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3) and the 4th PMOS tube (MP4) are low breakdown voltage pipe, institute State the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9) and the tenth PMOS tube (MP10) are high-breakdown-voltage pipe.