CN108540116A - A kind of transmission gate circuit of isolation high input voltage - Google Patents
A kind of transmission gate circuit of isolation high input voltage Download PDFInfo
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- CN108540116A CN108540116A CN201810509010.6A CN201810509010A CN108540116A CN 108540116 A CN108540116 A CN 108540116A CN 201810509010 A CN201810509010 A CN 201810509010A CN 108540116 A CN108540116 A CN 108540116A
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- pmos tube
- transmission gate
- gate circuit
- circuit
- pull
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 68
- 238000002955 isolation Methods 0.000 title claims abstract description 17
- 230000000694 effects Effects 0.000 abstract description 7
- 238000000926 separation method Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The present invention provides a kind of transmission gate circuit of isolation high input voltage simple in structure, reliability is high, belongs to electronic circuit technology field.Transmission gate circuit includes M2 and N grades of NMOS tube M1, PMOS tube pull-up circuits, the input VIN connections of the drain/source and transmission gate circuit of NMOS tube M1；The source/drain of NMOS tube M1 is connect with the source electrode of PMOS tube M2, while being connect with the output VOUT of transmission gate circuit, and the grid of NMOS tube M1 and PMOS tube M2 lead to opposite voltage control signal；The N grades of pull-up circuit is connected in series between input VIN and the drain electrode of PMOS tube M2, for when transmission gate circuit is off, keep the drain voltage of PMOS tube M2 identical with voltage VDD, N is the positive integer more than 1 in the case where realizing same separation effect, often add level-one pull-up circuit, then can effectively reduce the size of PMOS tube in pull-up circuit.
Description
Technical field
The present invention relates to a kind of transmission gate circuit, more particularly to a kind of transmission gate circuit of isolation high input voltage belongs to electricity
Sub-circuit technical field.
Background technology
In traditional circuit, PMOS tube and NMOS tube can form transmission gate together, as shown in Figure 1.In figure CLK andFor the opposite signal of voltage, i.e., when CLK is high voltage,For low-voltage, vice versa.When CLK is low-voltage,
Transmission gate conducting；When CLK is high voltage, transmission gate disconnects.The high voltage of CLK is generally equivalent to the supply voltage of chip, such as
For 5V.
In actual application, often there is the phenomenon that input VIN high pressures, such as 8V, transmission gate traditional at this time can not
Realize break function.Because after inputting the voltage on VIN higher than PMOS tube voltage domain voltage, even if transmission gate, which is in, disconnects shape
State, but PMOS tube therein is closed constantly, and VIN still can influence the value of output VOUT by transmission gate.Transmission gate is just at this time
Lose the effect of the pass as switch.
In view of the above technical problems, the solution of prior art routine is to increase the voltage domain of PMOS tube so that defeated
Enter the voltage that the voltage value on VIN is not higher than PMOS tube voltage domain.In this way when transmission gate is off, transmission gate can be with
Normal turn-off, the high voltage inputted on VIN will not influence the voltage signal on output VOUT by transmission gate.But this method
There are still limitations：Raising the voltage domain of PMOS tube can make the complexity of circuit increase, and can not only increase circuit cost, but also
Also resulting in the reliability of circuit reduces.
Invention content
In view of the above problems, the present invention provides a kind of transmission gate electricity of isolation high input voltage simple in structure, reliability is high
Road.
A kind of transmission gate circuit of isolation high input voltage of the present invention, the transmission gate circuit includes NMOS tube M1 and PMOS
Pipe M2, the drain/source of NMOS tube M1 are connect with the input VIN with transmission gate circuit；The source/drain and PMOS of NMOS tube M1
The source electrode of pipe M2 connects, while being connect with the output VOUT of transmission gate circuit, the grid control letter of NMOS tube M1 and PMOS tube M2
Number opposite in phase；
The transmission gate circuit further includes N grades of pull-up circuits, the N grades of pull-up circuit be connected in series in input VIN with
Between the drain electrode of PMOS tube M2, drain voltage and voltage for when transmission gate circuit is off, making PMOS tube M2
VDD is identical, and N is the positive integer more than 1.
Preferably, every grade of pull-up circuit is made of the first PMOS tube and the second PMOS tube；
The source electrode of first PMOS tube meets voltage VDD, and the drain electrode of the first PMOS tube is connect with the source electrode of the second PMOS tube, and makees
For a connecting pin of this grade of pull-up circuit, the drain electrode of the second PMOS tube is another connecting pin of this grade of pull-up circuit, described
The grid control signal opposite in phase of first PMOS tube and the second PMOS tube, the second PMOS tube and the grid control of NMOS tube M1 are believed
Number opposite in phase.
Preferably, when N is equal to 2, a1/a2＞ 0.5, a1Indicate the channel width of the first PMOS tube and the ratio of length,
a2Indicate the channel width of the second PMOS tube and the ratio of length.
Preferably, when N is equal to 3, a1/a2＞ 0.025, a1Indicate the channel width of the first PMOS tube and the ratio of length
Value, a2Indicate the channel width of the second PMOS tube and the ratio of length.
Preferably, the voltage of the input VIN is less than 10V, it is further preferred that the input VIN voltage is 5-8V.
The beneficial effects of the present invention are present invention adds multistage pull-up circuit, at the transmission gate circuit for making the present invention
When off-state, transmission gate circuit can be with normal turn-off, and the high voltage inputted on VIN will not influence output by transmission gate
Voltage signal on VOUT increases so the improved transmission gate circuit of the present invention is pressed with good barrier properties to the height of input
Add reliability, and the configuration of the present invention is simple, it is at low cost.In the case where realizing same separation effect, often add level-one pull-up
Circuit then can effectively reduce the size of PMOS tube in pull-up circuit.
Description of the drawings
Fig. 1 is the electronic schematic diagram of existing transmission gate circuit；
Fig. 2 is the electrical principle signal for pulling up the transmission gate circuit of PMOS in the specific embodiment of the invention with two-stage
Figure；
Fig. 3 is the equivalent circuit of Fig. 2；
Fig. 4 is the electrical principle signal for pulling up the transmission gate circuit of PMOS in the specific embodiment of the invention with three-level
Figure；
Fig. 5 is that high input voltage VIN emulation experiments are isolated in existing transmission gate circuit；
Fig. 6 is the transmission gate circuit isolation high input voltage VIN for pulling up PMOS in the specific embodiment of the invention with two-stage
Emulation experiment；
Fig. 7 is the transmission gate circuit isolation high input voltage VIN for pulling up PMOS in the specific embodiment of the invention with three-level
Emulation experiment.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of not making creative work it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
Embodiment is described with reference to Fig. 1, the transmission gate circuit of the isolation high input voltage described in present embodiment, the biography
Defeated gate circuit includes M2 and N grades of NMOS tube M1, PMOS tube pull-up circuits,
The drain/source of NMOS tube M1 is connect with the input VIN with transmission gate circuit；The source/drain of NMOS tube M1 with
The source electrode of PMOS tube M2 connects, while being connect with the output VOUT of transmission gate circuit, the grid control of NMOS tube M1 and PMOS tube M2
Signal phase processed is opposite；
The N grade pull-up circuits of present embodiment are connected in series between input VIN and the drain electrode of PMOS tube M2, for when biography
When defeated gate circuit is off, keep the drain voltage of PMOS tube M2 identical with voltage VDD, N is the positive integer more than 1, this
Embodiment is pressed with good barrier properties to the height of input, and reliability increases；
In preferred embodiment, every grade of pull-up circuit is made of the first PMOS tube and the second PMOS tube；
Every grade of pull-up circuit is made of the first PMOS tube and the second PMOS tube；
The source electrode of first PMOS tube meets voltage VDD, and the drain electrode of the first PMOS tube is connect with the source electrode of the second PMOS tube, and makees
For a connecting pin of this grade of pull-up circuit, the drain electrode of the second PMOS tube is another connecting pin of this grade of pull-up circuit, described
The grid control signal opposite in phase of first PMOS tube and the second PMOS tube, the second PMOS tube and the grid control of NMOS tube M1 are believed
Number opposite in phase.
When N is equal to 2, as shown in Fig. 2, present embodiment is to pull up the transmission gate circuit of PMOS, the first order with two-stage
Pull-up circuit includes PMOS tube M5 and PMOS tube M6, and second level pull-up circuit includes PMOS tube M3 and PMOS tube M4；
The source electrode of PMOS tube M5 and the source electrode of PMOS tube M3 meet voltage VDD simultaneously；
The drain electrode of PMOS tube M6 meets the input VIN of transmission gate circuit, the drain electrode of PMOS tube M5 and the source electrode of PMOS tube M6 and
The drain electrode of PMOS tube M4 connects simultaneously；The drain electrode of PMOS tube M3 and the drain electrode of the source electrode and PMOS tube M2 of PMOS tube M4 connect simultaneously
It connects；
The grid of the grid control signal opposite in phase of PMOS tube M5 and PMOS tube M6, PMOS tube M3 and PMOS tube M4 control
Signal phase is opposite.
The grid of PMOS tube M5, the grid of PMOS tube M3 are identical with the grid control signal phase of NMOS tube M1.
The operation principle of transmission gate circuit that PMOS is pulled up with two-stage is：PMOS tube in Fig. 2 is operated in vdd voltage
Domain, such as VDD are 5V, and when transmission gate circuit is off, PMOS tube M3 and PMOS tube M5 conductings have on stronger
Drawing ability, remaining metal-oxide-semiconductor are in closed state.It is high voltage, such as 8V when inputting VIN, when being more than vdd voltage threshold value,
PMOS tube M6 and PMOS tube M4 are in weak conducting state, and designing PMOS tube M3 and PMOS tube M5 at this time has stronger pull-up energy
Power may make A point current potentials close to VDD in this way, then PMOS tube M2 is equivalent to off-state at this time, influence very little of the A points to VOUT,
It can be ignored.
The principle of Fig. 2 can be equivalent to shown in Fig. 3.PMOS tube M3, PMOS tube M4, PMOS tube M5 and PMOS tube M6 are respectively etc.
Effect be resistance R3, R4, R5 and R6, then the voltage of A points be
Because the driving capability of PMOS tube M5 is much larger than PMOS tube M6, the driving capability of PMOS tube M3 is much larger than PMOS tube M4, is equivalent to
Resistance R5 is much larger than resistance R6, and resistance R3 is much larger than resistance R4, then VA is approximately equal to VDD, the grid of the voltage and NMOS tube M1
Voltage is almost the same, can make PMOS tube M2 close, so PMOS tube M2 at this time be equivalent between A points and VOUT it is disconnected
It opens, A points almost do not influence VOUT.
In order to make PMOS tube M5 and PMOS tube M3 have very strong pull-up ability and A point current potentials close to VDD, design at this time
The size W/L of PMOS tube M5 and PMOS tube M3 is larger, has stronger pull-up ability, the driving energy of PMOS tube M6 and PMOS tube M4
Power is weaker, can enable the channel width of PMOS tube M3 and PMOS tube M5 and the ratio of length：Breadth length ratio (W/L)5/(W/L)6>0.5, it is wide
Length is than (W/L)3/(W/L)4>0.5, (W/L)5Indicate the ratio of the channel width and length of PMOS tube M5, (W/L)6Indicate PMOS
The channel width of pipe M6 and the ratio of length, (W/L)3Indicate the ratio of the channel width and length of PMOS tube M3, (W/L)4It indicates
The channel width of PMOS tube M4 and the ratio of length.
When N is equal to 3, as shown in figure 4, present embodiment is to pull up the transmission gate circuit of PMOS, this implementation with three-level
Mode increases level-one pull-up circuit, including PMOS tube M7 and PMOS tube M8 on the basis of Fig. 2；Make metal-oxide-semiconductor M7, metal-oxide-semiconductor M5 and
Metal-oxide-semiconductor M3 has stronger pull-up ability, i.e.,：(W/L)7/(W/L)8>0.025, (W/L)5/(W/L)6>0.025, (W/L)3/(W/
L)4>0.025, compared to the transmission gate circuit of two-stage pull-up function, three-level pulls up the size of the PMOS tube of the transmission gate circuit of PMOS
It is reduced to PMOS tube M3 or PMOS tube M5 sizesLeft and right, you can realize the high_voltage isolation effect as Fig. 2.
More multigroup PMOS can also be added in present embodiment, form the transmission gate with multistage pull-up PMOS.With more
In the transmission gate of grade pull-up PMOS, pull-up PMOS tube need to only use smaller size, so that it may carry two-stage pull-up to reach
The same high_voltage isolation effect of the transmission gate of PMOS.
The circuit simulation comparison of present embodiment in typical case, when simulating, verifying, in the output VOUT of transmission gate circuit
A very weak 2.5V voltages are terminated, are highly susceptible to interfere and change.Abscissa in Fig. 5 to Fig. 7 is transmission gate circuit
Input VIN voltage, ordinate be transmission gate circuit output VOUT voltage.The voltage domain of transmission gate circuit is 5V in figure.
As can be seen that after high-voltage signal is added in the ends transmission gate circuit input VIN in Fig. 5, existing transmission gate circuit is in output VOUT
End will produce prodigious interference, and the output situation in Fig. 6 and Fig. 7 is essentially identical, this is because with two-stage pull-up PMOS tube
The size of the pull-up PMOS tube of transmission gate circuit is 20 times of three-level pull-up PMOS transmission gate circuits.From the experimental results, it
Reach same high_voltage isolation effect, the transmission gate circuit with three-level pull-up PMOS tube can use smaller pull-up PMOS
Pipe effectively reduces the size of pull-up PMOS tube.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from the spirit of the present invention as defined in the appended claims
And range.It should be understood that can be by combining different appurtenances different from mode described in original claim
Profit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can use
In other described embodiments.
Claims (5)
1. a kind of transmission gate circuit of isolation high input voltage, the transmission gate circuit includes NMOS tube M1 and PMOS tube M2, NMOS
The input VIN connections of the drain/source and transmission gate circuit of pipe M1；The source electrode of the source/drain and PMOS tube M2 of NMOS tube M1
Connection, while being connect with the output VOUT of transmission gate circuit, the grid control signal opposite in phase of NMOS tube M1 and PMOS tube M2；
It is characterized in that, the transmission gate circuit further includes N grades of pull-up circuits, the N grades of pull-up circuit is connected in series in input
Between VIN and the drain electrode of PMOS tube M2, for when transmission gate circuit is off, make PMOS tube M2 drain voltage and
Voltage VDD is identical, and N is the positive integer more than 1.
2. the transmission gate circuit of isolation high input voltage according to claim 1, which is characterized in that every grade of pull-up circuit is by the
One PMOS tube and the second PMOS tube composition；
The source electrode of first PMOS tube meets voltage VDD, and the drain electrode of the first PMOS tube is connect with the source electrode of the second PMOS tube, and as this
One connecting pin of grade pull-up circuit, the drain electrode of the second PMOS tube are another connecting pin of this grade of pull-up circuit, described first
The grid control signal opposite in phase of PMOS tube and the second PMOS tube leads to opposite voltage control signal, the second PMOS tube and NMOS
The grid control signal opposite in phase of pipe M1.
3. the transmission gate circuit of isolation high input voltage according to claim 2, which is characterized in that when N is equal to 2, a1/a2
＞ 0.5, a1Indicate the channel width of the first PMOS tube and the ratio of length, a2Indicate the channel width and length of the second PMOS tube
Ratio.
4. the transmission gate circuit of isolation high input voltage according to claim 2, which is characterized in that when N is equal to 3, a1/a2
＞ 0.025, a1Indicate the channel width of the first PMOS tube and the ratio of length, a2Indicate the channel width and length of the second PMOS tube
The ratio of degree.
5. the transmission gate circuit of isolation high input voltage according to claim 3 or 4, which is characterized in that the input VIN's
Voltage is less than 10V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810509010.6A CN108540116A (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit of isolation high input voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810509010.6A CN108540116A (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit of isolation high input voltage |
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| Publication Number | Publication Date |
|---|---|
| CN108540116A true CN108540116A (en) | 2018-09-14 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810509010.6A Pending CN108540116A (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit of isolation high input voltage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112689959A (en) * | 2018-09-20 | 2021-04-20 | 华为技术有限公司 | Transmission gate circuit, matrix switch and electronic equipment |
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| JPH09246502A (en) * | 1996-03-07 | 1997-09-19 | Kawasaki Steel Corp | Gate array integrated circuit |
| CN102761325A (en) * | 2011-04-27 | 2012-10-31 | 中国科学院电子学研究所 | Selector circuit with fixed output state |
| CN103312309A (en) * | 2013-05-14 | 2013-09-18 | 无锡华润矽科微电子有限公司 | Analog switch control circuit structure |
| CN106330172A (en) * | 2015-06-18 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Transmission gate and subsequent pull-down circuit structure for high-voltage-threshold device |
| CN107257238A (en) * | 2017-06-30 | 2017-10-17 | 深圳贝特莱电子科技股份有限公司 | A kind of two-way bootstrapping dynamic switch circuit of high tension apparatus work at lower voltages |
| CN107306128A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | Transmission gate circuit |
-
2018
- 2018-05-24 CN CN201810509010.6A patent/CN108540116A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09246502A (en) * | 1996-03-07 | 1997-09-19 | Kawasaki Steel Corp | Gate array integrated circuit |
| CN102761325A (en) * | 2011-04-27 | 2012-10-31 | 中国科学院电子学研究所 | Selector circuit with fixed output state |
| CN103312309A (en) * | 2013-05-14 | 2013-09-18 | 无锡华润矽科微电子有限公司 | Analog switch control circuit structure |
| CN106330172A (en) * | 2015-06-18 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Transmission gate and subsequent pull-down circuit structure for high-voltage-threshold device |
| CN107306128A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | Transmission gate circuit |
| CN107257238A (en) * | 2017-06-30 | 2017-10-17 | 深圳贝特莱电子科技股份有限公司 | A kind of two-way bootstrapping dynamic switch circuit of high tension apparatus work at lower voltages |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112689959A (en) * | 2018-09-20 | 2021-04-20 | 华为技术有限公司 | Transmission gate circuit, matrix switch and electronic equipment |
| CN112689959B (en) * | 2018-09-20 | 2023-10-20 | 华为技术有限公司 | Transmission gate circuit, matrix switch and electronic equipment |
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Application publication date: 20180914 |