CN108536210B - A Smooth Temperature Compensated Bandgap Reference Source Circuit - Google Patents

Abstract

A smooth temperature compensation bandgap reference source circuit belongs to the technical field of analog integrated circuits. Including a start-up module, a bias module, a high-order compensation module and a bandgap reference core module, the start-up module is used to make the bandgap reference source circuit out of the zero state during the circuit initialization phase, and shut down after the bandgap reference source circuit works normally; The bias module is used to generate the first bias voltage and the second bias voltage for the high-order compensation module and the bandgap reference core module; the bandgap reference core module is used to generate the reference voltage, and the high-order compensation module is used to generate high-order compensation current to improve the temperature characteristics of the reference voltage. The bandgap reference source proposed in the present invention realizes continuous temperature compensation in the entire temperature range, reduces the temperature drift of the reference voltage in the entire temperature range, and realizes high-order compensation in the entire temperature range, so that the reference voltage is in a wide range high accuracy over a wide temperature range.

Description

A Smooth Temperature Compensation Bandgap Reference Source Circuit

technical field

The invention belongs to the technical field of analog integrated circuits, and in particular relates to a smooth temperature compensation bandgap reference source circuit.

Background technique

The voltage reference source is a very important module in all electronic systems, and its characteristics are directly related to the safety, reliability and performance indicators of the system. Therefore, the high-precision voltage reference source plays an important role in many applications, covering pure analog circuits, Mixed digital circuits and pure digital circuits, such as A/D converters, DRAMs, power conversion and flash memory circuits.

For DC-DC converters, the performance of the voltage reference source is directly related to the accuracy and stability of the converter output, so it is particularly important for the design of high-performance converters. As the accuracy of the reference voltage becomes higher and higher, the traditional first-order temperature-compensated reference source can no longer meet the application requirements.

Contents of the invention

Aiming at the deficiencies in the accuracy and stability of the traditional temperature compensation reference source, the present invention proposes a smooth temperature compensation bandgap reference source circuit, adopts a smooth temperature compensation strategy, and the proposed high-order compensation module can be used in the entire temperature range The continuous temperature compensation is realized within, which reduces the temperature drift of the output voltage in the whole temperature range, and realizes the high-order compensation in the whole temperature range, so that the reference voltage has high precision in a wide temperature range.

Technical scheme of the present invention is:

A smooth temperature-compensated bandgap reference source circuit, including a start-up module and a bias module, the start-up module is used to make the bandgap reference source circuit out of the zero state in the circuit initialization stage, and start the bandgap reference source circuit in the Shut down after normal operation; the bias module is used to generate the first bias voltage V1 and the second bias voltage V2; the bandgap reference source circuit also includes a high-order compensation module and a bandgap reference core module;

The bandgap reference core module includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first A PNP transistor QP1, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9 and the tenth PMOS tube MP10,

The gate of the first PMOS transistor MP1 is connected to the gates of the third PMOS transistor MP3, the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, and the ninth PMOS transistor MP9 and is connected to the first bias voltage V1, and its drain is connected to The source of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3, the fifth PMOS transistor MP5, the seventh PMOS transistor MP7 and the ninth PMOS transistor MP9 and connected to the power supply voltage VCC;

The gate of the second PMOS transistor MP2 is connected to the gates of the fourth PMOS transistor MP4, the sixth PMOS transistor MP6, the eighth PMOS transistor MP8, and the tenth PMOS transistor MP10 and is connected to the second bias voltage V2, and its drain is connected to The gate and drain of the first NMOS transistor MN1 and the gates of the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6;

The source of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and its drain is connected to the gate of the third NMOS transistor MN3 and the gate and drain of the second NMOS transistor MN2, and grounded after passing through the first capacitor C1 GND;

The source of the third NMOS transistor MN3 is connected to the emitter of the third NPN transistor Q3, the collector of the first PNP transistor QP1, and the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, and the seventh NMOS transistor. The source of the tube MN7 is grounded to GND, and its drain is connected to the emitters of the first NPN transistor Q1 and the second NPN transistor Q2;

The base of the second triode Q2 is connected to the drain of the tenth PMOS transistor MP10 and the emitter of the first PNP transistor QP1 and is used as the output terminal of the bandgap reference source circuit to output the reference voltage V _REF , and its collector is connected to The drain of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8;

The first resistor R1 and the second resistor R2 are connected in series and in parallel between the output terminal of the bandgap reference source circuit and the collector of the third NPN transistor, and the series point is connected to the base of the first NPN transistor Q1 and the third transistor Q1. The output terminal of the above-mentioned high-order compensation module, the base of the first NPN transistor Q1 is connected to its collector;

The source of the sixth PMOS transistor MP6 is connected to the collector of the first NPN transistor Q1 and the drain of the fifth PMOS transistor MP5, and its drain is connected to the drain of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the seventh NMOS transistor. The gate of the tube MN7;

The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5; the drain of the ninth PMOS transistor MP9 is connected to the source of the tenth PMOS transistor MP10;

The drain of the sixth NMOS transistor MN6 is connected to the drain of the eighth PMOS transistor MP8 and the base of the first PNP transistor QP1 and grounded after passing through the second capacitor C2, and its source is connected to the drain of the seventh NMOS transistor MN7;

The high-order compensation module includes a third resistor R3, a fourth resistor R4, a fourth NPN transistor Q4, a fifth NPN transistor Q5, a sixth NPN transistor Q6, a seventh NPN transistor Q7, and an eighth NMOS transistor MN8 , the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the tenth Three PMOS transistors MP13, fourteenth PMOS transistors MP14, fifteenth PMOS transistors MP15, sixteenth PMOS transistors MP16, seventeenth PMOS transistors MP17, eighteenth PMOS transistors MP18 and nineteenth PMOS transistors MP19,

The base of the fourth NPN transistor Q4 is connected to the gates of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 and to the reference voltage V _REF , and its collector is connected to the gate and drain of the eleventh PMOS transistor MP11 And the gate of the twelfth PMOS transistor MP12, the emitter of which is grounded to GND after passing through the third resistor R3;

The gate-drain of the eighth NMOS transistor MN8 is short-circuited and connected to the drain of the twelfth PMOS transistor MP12 and the gate of the ninth NMOS transistor MN9, and its source is connected to the emitter of the seventh NPN transistor Q7 and the ninth NMOS transistor MN9 , the sources of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 are grounded to GND;

The gate of the thirteenth PMOS transistor MP13 is connected to the first bias voltage V1, its drain is connected to the base and collector of the fifth NPN transistor Q5 and the base of the sixth NPN transistor Q6, and its source is connected to The sources of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the seventeenth PMOS transistor MP17 and the eighteenth PMOS transistor MP18 are connected to the power supply voltage VCC;

The emitter of the fifth NPN transistor Q5 is connected to the base and collector of the seventh NPN transistor Q7;

The emitter of the sixth NPN transistor Q6 is grounded to GND after passing through the fourth resistor R4, and its collector is connected to the gate and drain of the fourteenth PMOS transistor MP14 and the gate of the fifteenth PMOS transistor MP15;

The gate of the sixteenth PMOS transistor MP16 is connected to the second bias voltage V2, its source is connected to the drain of the fifteenth PMOS transistor MP15, and its drain is connected to the drain of the ninth NMOS transistor MN9, the tenth NMOS transistor the source of MN10, the gate of the thirteenth NMOS transistor MN13, and the gate and drain of the twelfth NMOS transistor MN12;

The drain of the eleventh NMOS transistor MN11 is connected to the drain of the tenth NMOS transistor MN10, the gate of the eighteenth PMOS transistor MP18, and the gate and drain of the seventeenth PMOS transistor MP17, and its source is connected to the thirteenth NMOS transistor. The drain of the tube MN13;

The gate of the nineteenth PMOS transistor MP19 is connected to the second bias voltage V2, its source is connected to the drain of the eighteenth PMOS transistor MP18, and its drain is used as the output terminal of the high-order compensation module to output the compensation current I _COMP .

The beneficial effects of the present invention are: through the current comparison mode and the automatic current selector, the negative temperature characteristic compensation voltage is introduced at low temperature, and the positive temperature characteristic compensation voltage is introduced at high temperature, so that the reference circuit has higher temperature characteristics and wider The temperature range, so as to meet the demand for high-precision reference source with a wide temperature range, improve the performance and reliability of the system.

Description of drawings

FIG. 1 is an equivalent structure diagram of a smooth temperature compensation bandgap reference circuit proposed by the present invention.

Fig. 2 is a core circuit diagram of the smooth temperature compensation bandgap reference proposed by the present invention.

FIG. 3 is a high-order compensation circuit diagram of the smooth temperature compensation bandgap reference proposed by the present invention.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment, the present invention will be further elaborated:

As shown in Figure 1 is a structure diagram of a high-precision bandgap reference circuit with smooth temperature compensation proposed by the present invention, including a start-up module, a bias module, a high-order compensation module and a bandgap reference core module, wherein the start-up module is used for In the circuit initialization stage, the bandgap reference source circuit is separated from the zero state, and the bandgap reference source circuit is turned off after normal operation; the bias module is used to generate bias current, and the first bias voltage V1 and the second bias voltage V2 are bias The gate voltage when the current mirror is set; the specific working process is that the startup module makes the bias module generate part of the bias current during the circuit initialization stage, and the circuit leaves the zero state; when the circuit is in the normal working stage, the startup module branch is turned off to avoid Affect the normal operation of the circuit; on the one hand, the bias current generated by the bias module is mirrored by the current mirror to generate the first bias voltage V1 and the second bias voltage V2 to provide the bias voltage for the entire reference circuit; on the other hand, in the high-order compensation circuit The high-order compensation current is generated in the center; the bandgap reference core module is used to generate the reference voltage V _REF ; the high-order compensation module generates a high-order compensation current I _COMP to improve the temperature characteristic of the reference voltage V _REF . The working process of the present invention will be analyzed in detail below in conjunction with specific circuits.

As shown in Figure 2 is the specific circuit diagram of the bandgap reference core module of the present invention, the bias module provides the first bias voltage V1 and the second bias voltage V2 for the bandgap reference core module, the first NPN transistor Q1, the second The second NPN transistor Q2 and the third NPN transistor Q3 adopt the same type of transistors, the first NPN transistor Q1 and the second NPN transistor Q2 flow the same current, and in order to obtain the ideal bandgap voltage, the first The emitter area (M=8) of the NPN type transistor Q1 is set to 8 times of the emitter area (M=1) of the second NPN type transistor Q2, because the emitters of the first NPN type transistor Q1 and the second NPN type transistor Q2 The voltages are equal, so that the difference between the base-emitter voltages of the second NPN transistor Q2 and the first NPN transistor Q1 is △V _BE , that is, the base voltage of the second NPN transistor Q2 is higher than that of the first NPN transistor Q1 The base voltage is higher than V _T ln8, where V _T is a thermal voltage, and a current with a positive temperature coefficient is generated on the first resistor R1, and the base-emitter voltage V _{BE of the third NPN transistor Q3, Q3} is a The voltage has a negative temperature coefficient, so select appropriate resistance values of the first resistor R1 and the second resistor R2 to obtain a bandgap reference source that has little relationship with temperature.

The positive feedback loop in Figure 2 consists of the first resistor R1, the first NPN transistor Q1, the sixth PMOS transistor MP6, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the seventh NMOS transistor MN7, the sixth NMOS transistor MN6 and The first PNP transistor QP1 is formed, and the negative feedback loop is composed of the second NPN transistor Q2, the eighth PMOS transistor MP8 and the first PNP transistor QP1. Then the positive feedback gain A _{V, PF} and the negative feedback gain A _{V, NF} are respectively:

A _v,NF ＝g _m,Q2 R _C

R_C为运算放大器输出电阻，I_C,Q3为第三NPN型三极管Q3的集电极电流，g_m,Q1和g_m,Q2分别是第一NPN型三极管Q1和第二NPN型三极管Q2的跨导。由于第一NPN型三极管Q1和第二NPN型三极管Q2的跨导相等，则有负反馈环的增益大于正反馈环的增益，那么整个电路系统在输出基准电压V_REF偏离正常时能够通过环路调整稳定。因此整体环路增益为：The transconductance of the third NPN transistor Q3

R _C is the output resistance of the operational amplifier, I _{C, Q3} is the collector current of the third NPN transistor Q3, g _{m, Q1} and g _{m, Q2} are the spans of the first NPN transistor Q1 and the second NPN transistor Q2 respectively guide. Since the transconductance of the first NPN transistor Q1 and the second NPN transistor Q2 are equal, the gain of the negative feedback loop is greater than the gain of the positive feedback loop, so the entire circuit system can pass through the loop when the output reference voltage V _REF deviates from normal Adjusted for stability. The overall loop gain is therefore:

Figure 3 shows the specific circuit diagram of the high-order compensation module. The high-order compensation current generation part includes the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the Seventeenth PMOS tube MP17, eighteenth PMOS tube MP18, nineteenth PMOS tube MP19, ninth NMOS tube MN9, tenth NMOS tube MN10, eleventh NMOS tube MN11, twelfth NMOS tube MN12, thirteenth NMOS The tube MN13, the fourth resistor R4, the fifth NPN transistor Q5, the sixth NPN transistor Q6 and the seventh NPN transistor Q7, the voltage drop on the fourth resistor R4 is the base-emitter of the NPN transistor Q7 The voltage V _BE,Q7 generates a current with negative temperature characteristics. After being mirrored by the current mirror composed of the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15, the current flowing through the fifteenth PMOS transistor MP15 is negative temperature. Characteristic current I _CTAT .

The voltage applied to the third resistor R3 is the difference between a reference voltage V _REF and the base-emitter voltage V _BE,Q4 of the fourth NPN transistor Q4, that is, the positive temperature voltage, so the third resistor R3 will generate a positive temperature After the current is mirrored by two groups of current mirrors composed of the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9, the current flowing through the ninth NMOS transistor MN9 is positive temperature Characteristic current I _PTAT .

At low temperature, the negative temperature current _ICTAT is greater than the positive temperature current _IPTAT , the tenth NMOS transistor MN10 is turned off, the twelfth NMOS transistor MN12 is turned on, and the current mirror formed by the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 The mirror image makes the output compensation current I _COMP proportional to the difference between the negative temperature current I _CTAT and the positive temperature current I _PTAT ; at high temperature, the positive temperature current I _PTAT is greater than the negative temperature current I _CTAT , the twelfth NMOS tube MN12 is turned off, and the Ten NMOS transistors MN10 and MN10 are turned on, and the output compensation current I _COMP is proportional to the difference between the positive temperature current I _PTAT and the negative temperature current I _CTAT .

From this, the expression of the compensation current I _COMP can be obtained as:

From the above analysis, the expression of the reference voltage V _REF can be obtained as:

V _REF = V _refBGR + V _h,COMP

Where V _refBGR is the traditional bandgap reference voltage, V _{h, COMP} is the high-order compensation voltage

The high-order compensation voltage V _{h can be obtained from the analysis of the high-order compensation module, and the expression of COMP} is:

Where Tr is the critical point of positive and negative temperature compensation, K1 is the ratio of the width to length of the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13, and K2 is the ratio of the seventeenth PMOS transistor MP17 to the eighteenth PMOS transistor MP18. The aspect ratio, when T<Tr, the high-order compensation voltage V _h,COMP exhibits a negative temperature characteristic, and as the temperature increases, the negative temperature characteristic becomes stronger; when T>Tr, the high-order The compensation voltage V _h,COMP exhibits positive temperature characteristics, and the positive temperature characteristics become stronger as the temperature increases. The negative _temperature characteristic of V _BE of the traditional bandgap reference voltage is weak at low temperature, and the reference voltage exhibits positive temperature. Shown as negative temperature characteristics. Due to the nonlinear negative temperature characteristic of the base-emitter voltage V _BE of the triode, the negative temperature characteristic increases with the increase of temperature, while the positive temperature characteristic of the positive temperature voltage of the traditional bandgap reference voltage hardly changes with temperature Therefore, at low temperature (T<Tr) it is necessary to compensate the voltage with negative temperature characteristics, and at high temperature (T>Tr) to compensate the compensation voltage with positive temperature characteristics, so as to obtain a high-precision reference voltage. The bandgap reference proposed by the present invention The source compensates the voltage with negative temperature characteristics at low temperature and compensates the voltage with positive temperature characteristics at high temperature. In the whole process, the automatic and continuous conversion of compensation temperature is realized, and the compensation current with different temperature characteristics is smoothly switched, avoiding the output reference voltage V _REF The effect of jumping. In addition, in the high and low temperature region, the positive temperature compensation current and the negative temperature compensation current introduced respectively can further reduce the base-emitter voltage V _{BE of the third NPN transistor Q3, and the influence of the high-order nonlinearity of the temperature of Q3} , thereby further Improve the performance of the overall circuit.

In summary, a smooth temperature compensation bandgap reference source circuit proposed by the present invention adopts a smooth temperature compensation strategy, so that the compensation network (that is, the high-order temperature compensation circuit) can operate within the entire temperature range (-55-125 °C in the present invention). °C) to achieve continuous temperature compensation, reducing the temperature drift of the output reference voltage in the entire temperature range, and realizing high-order compensation in the entire temperature range, so that the reference voltage has high precision in a wide temperature range.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (1)

1. A smooth temperature-compensated bandgap reference source circuit, comprising a start-up module and a bias module, the start-up module is used to make the bandgap reference source circuit break away from the zero state in the circuit initialization stage, and in the bandgap reference The source circuit is turned off after normal operation; the bias module is used to generate a first bias voltage (V1) and a second bias voltage (V2); It is characterized in that the bandgap reference source circuit also includes a high-order compensation module and a bandgap reference core module; The bandgap reference core module includes a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), a first NPN transistor (Q1), a second NPN transistor (Q2), the third NPN transistor (Q3), the first PNP transistor (QP1), the first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3), the fourth NMOS transistor (MN4), fifth NMOS transistor (MN5), sixth NMOS transistor (MN6), seventh NMOS transistor (MN7), first PMOS transistor (MP1), second PMOS transistor (MP2), third PMOS transistor (MP3 ), the fourth PMOS transistor (MP4), the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), the seventh PMOS transistor (MP7), the eighth PMOS transistor (MP8), the ninth PMOS transistor (MP9) and The tenth PMOS tube (MP10), The gate of the first PMOS transistor (MP1) is connected to the gates of the third PMOS transistor (MP3), the fifth PMOS transistor (MP5), the seventh PMOS transistor (MP7) and the ninth PMOS transistor (MP9) and connected to the first PMOS transistor (MP9). A bias voltage (V1), its drain is connected to the source of the second PMOS transistor (MP2), and its source is connected to the third PMOS transistor (MP3), the fifth PMOS transistor (MP5), and the seventh PMOS transistor (MP7) and the source of the ninth PMOS transistor (MP9) and connected to the power supply voltage (VCC); The gate of the second PMOS transistor (MP2) is connected to the gates of the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6), the eighth PMOS transistor (MP8) and the tenth PMOS transistor (MP10) and is connected to the first PMOS transistor (MP10). Two bias voltages (V2), the drain of which is connected to the gate and drain of the first NMOS transistor (MN1) and the gates of the fourth NMOS transistor (MN4) and the sixth NMOS transistor (MN6); The source of the fourth PMOS transistor (MP4) is connected to the drain of the third PMOS transistor (MP3), and its drain is connected to the gate of the third NMOS transistor (MN3) and the gate and drain of the second NMOS transistor (MN2) And ground (GND) after passing through the first capacitor (C1); The source of the third NMOS transistor (MN3) is connected to the emitter of the third NPN transistor (Q3), the collector of the first PNP transistor (QP1), the first NMOS transistor (MN1), and the second NMOS transistor (MN2). , the sources of the fifth NMOS transistor (MN5) and the seventh NMOS transistor (MN7) are grounded (GND), and the drains are connected to the emitters of the first NPN transistor (Q1) and the second NPN transistor (Q2); The base of the second triode (Q2) is connected to the drain of the tenth PMOS transistor (MP10) and the emitter of the first PNP transistor (QP1) and is used as the output terminal of the bandgap reference source circuit to output the reference voltage ( V _REF ), the collector of which is connected to the drain of the seventh PMOS transistor (MP7) and the source of the eighth PMOS transistor (MP8); The first resistor (R1) and the second resistor (R2) are connected in series and parallel between the output terminal of the bandgap reference source circuit and the collector of the third NPN transistor, and the series point is connected to the first NPN transistor (Q1 ) base and the output end of the high-order compensation module, the base of the first NPN transistor (Q1) is connected to its collector; The source of the sixth PMOS transistor (MP6) is connected to the collector of the first NPN transistor (Q1) and the drain of the fifth PMOS transistor (MP5), and its drain is connected to the drain of the fourth NMOS transistor (MN4) and the drain of the fifth PMOS transistor (MN4). Gates of the fifth NMOS transistor (MN5) and the seventh NMOS transistor (MN7); The source of the fourth NMOS transistor (MN4) is connected to the drain of the fifth NMOS transistor (MN5); the drain of the ninth PMOS transistor (MP9) is connected to the source of the tenth PMOS transistor (MP10); The drain of the sixth NMOS transistor (MN6) is connected to the drain of the eighth PMOS transistor (MP8) and the base of the first PNP transistor (QP1) and grounded after passing through the second capacitor (C2), and its source is connected to the seventh The drain of the NMOS transistor (MN7); The high-order compensation module includes a third resistor (R3), a fourth resistor (R4), a fourth NPN transistor (Q4), a fifth NPN transistor (Q5), a sixth NPN transistor (Q6), a seventh NPN transistor (Q7), eighth NMOS transistor (MN8), ninth NMOS transistor (MN9), tenth NMOS transistor (MN10), eleventh NMOS transistor (MN11), twelfth NMOS transistor (MN12), Thirteenth NMOS tube (MN13), eleventh PMOS tube (MP11), twelfth PMOS tube (MP12), thirteenth PMOS tube (MP13), fourteenth PMOS tube (MP14), fifteenth PMOS tube ( MP15), the sixteenth PMOS tube (MP16), the seventeenth PMOS tube (MP17), the eighteenth PMOS tube (MP18) and the nineteenth PMOS tube (MP19), The base of the fourth NPN transistor (Q4) is connected to the gates of the tenth NMOS transistor (MN10) and the eleventh NMOS transistor (MN11) and connected to the reference voltage (V _REF ), and its collector is connected to the eleventh PMOS The grid and drain of the tube (MP11) and the grid of the twelfth PMOS tube (MP12), the emitter of which passes through the third resistor (R3) and then grounded (GND); The gate-drain of the eighth NMOS transistor (MN8) is short-circuited and connected to the drain of the twelfth PMOS transistor (MP12) and the gate of the ninth NMOS transistor (MN9), and its source is connected to the seventh NPN transistor (Q7). The emitter and the sources of the ninth NMOS transistor (MN9), the twelfth NMOS transistor (MN12) and the thirteenth NMOS transistor (MN13) are grounded (GND); The gate of the thirteenth PMOS transistor (MP13) is connected to the first bias voltage (V1), and its drain is connected to the base and collector of the fifth NPN transistor (Q5) and the sixth NPN transistor (Q6). The base, the source of which is connected to the eleventh PMOS transistor (MP11), the twelfth PMOS transistor (MP12), the fourteenth PMOS transistor (MP14), the fifteenth PMOS transistor (MP15), the seventeenth PMOS transistor ( MP17) and the source of the eighteenth PMOS transistor (MP18) are connected to the power supply voltage (VCC); The emitter of the fifth NPN transistor (Q5) is connected to the base and collector of the seventh NPN transistor (Q7); The emitter of the sixth NPN transistor (Q6) is grounded (GND) after passing through the fourth resistor (R4), and its collector is connected to the gate and drain of the fourteenth PMOS transistor (MP14) and the fifteenth PMOS transistor (MP15 ) grid; The gate of the sixteenth PMOS transistor (MP16) is connected to the second bias voltage (V2), its source is connected to the drain of the fifteenth PMOS transistor (MP15), and its drain is connected to the ninth NMOS transistor (MN9) The drain of the tenth NMOS transistor (MN10), the gate of the thirteenth NMOS transistor (MN13), and the gate and drain of the twelfth NMOS transistor (MN12); The drain of the eleventh NMOS transistor (MN11) is connected to the drain of the tenth NMOS transistor (MN10), the gate of the eighteenth PMOS transistor (MP18), and the gate and drain of the seventeenth PMOS transistor (MP17), Its source is connected to the drain of the thirteenth NMOS transistor (MN13); The gate of the nineteenth PMOS transistor (MP19) is connected to the second bias voltage (V2), its source is connected to the drain of the eighteenth PMOS transistor (MP18), and its drain is used as the high-order compensation module The output terminal outputs the compensation current (I _COMP ).

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