CN108494533A - A kind of multichannel communication multiple telecommunication device error rate test device and method of portable long distance - Google Patents

Abstract

The invention discloses a kind of multichannel communication multiple telecommunication device error rate test device and method of portable long distance, which includes：HSSI High-Speed Serial Interface expansion board, parallel interface expansion board, clock generator, acquisition controller, USB extended lines and remote terminal；The connection type of measured device and the device includes：Long-range connection is connected with short range；The pseudo random sequence code seed that various modes are generated by the present apparatus is used as mode code, pattern comparison is carried out with the tested sequence that measured device generates, the sequence consistent with mode code is found after comparison by one section of sequence, mode code generates its subsequent corresponding sequence according to consistent sequence, it is carried out by bit comparison with tested sequence, to realize error detection.The present invention can be used in various severe test environments, and device has the function of multi-path serial and parallel channel, and can realize remote error rate test；And measuring accuracy is high, device good portability, use cost is low.

Description

A portable long-distance multi-channel communication device bit error rate testing device and method

technical field

The invention relates to the technical field of communication device detection, in particular to a portable long-distance multi-channel communication device bit error rate test device and method.

Background technique

Digital communication systems are more and more widely used in production, life and other aspects, and bit error (BER) performance is one of the most basic measurement indicators of any digital communication system performance. Measuring bit error metrics is usually done with a bit error rate test analyzer. Especially with the enhancement of the anti-interference ability of digital system ASIC chips, digital communication systems are also used in harsh environments such as medical system detectors with strong radiation environments, particle accelerators for high-energy physics research, and communication systems in space exploration, etc. field. Therefore, it provides long-distance test capability when performing BER test. At present, commercial BER analyzers are mainly manufactured by companies such as Agilent, Tektronix, and Anritsu. The BER analyzers introduced by them are multifunctional and powerful with eye diagram analysis capabilities, but the instruments are bulky and expensive. For example, the lowest price of Tektronix's BSA series bit error rate analyzer is more than 100,000 US dollars. Another example is Anritsu's high-performance integrated BER analyzer MP2100A, which weighs nearly seven kilograms and is inconvenient to carry, and its price is also more than 100,000 US dollars. Even the Tektronix BA series bit error rate tester with a maximum rate of only 1.6Gbps without network function costs more than $50,000. Therefore, although commercial BER test systems have strong test capabilities and high precision, they are bulky and inconvenient to carry, which affects test installations in harsh environments.

The current FPGA already has specialized communication interfaces including clock data recovery and enhanced phase-locked loop circuits. In addition, the performance and powerful communication capabilities are also sufficient for high-speed communication and computing. Kintex-7 is a new generation of high-performance field programmable gate array with 16 channels of up to 11.5Gbps transmission rate GTX, and its Xilinx report pointed out that this chip can withstand radiation TID test (TID is a kind given in the ATLAS report Standard test method) reaches a total dose of 1Mrad. Therefore, Kintex-7 is suitable for long-term work in a radiation environment.

Contents of the invention

The technical problem to be solved by the present invention is to provide a portable long-distance multi-channel communication device bit error rate testing device and method for the defects in the prior art.

The technical solution adopted by the present invention to solve its technical problems is:

The invention provides a portable long-distance multi-channel communication device bit error rate testing device, which comprises: a high-speed serial interface expansion board, a parallel interface expansion board, a clock generator, an acquisition controller, a USB extension cable and a remote terminal; in:

The acquisition controller is provided with an LPC interface, an HPC interface, a first RJ45 interface and a serial reference clock interface; the clock generator is provided with a first USB interface and multiple clock signal output interfaces; the remote terminal is provided with a second USB interface and the second RJ45 interface; both the high-speed serial interface expansion board and the parallel interface expansion board are provided with an FMC interface and a serial reference clock interface;

The high-speed serial interface expansion board is connected to the HPC interface of the acquisition controller through the first FMC interface, and the parallel interface expansion board is connected to the LPC interface of the acquisition controller through the second FMC interface;

The clock generator is respectively connected to the high-speed serial interface expansion board and the serial reference clock interface of the acquisition controller through the clock signal output interface; the first USB interface on the clock generator is connected to the second USB interface on the remote terminal through a USB extension cable connected; the first RJ45 interface on the acquisition controller is connected to the second RJ45 interface on the remote terminal through a network cable;

The connection methods between the device under test and the device include: remote connection and short-range connection; the device under test realizes remote connection with the acquisition controller through optical fiber; the device under test and the high-speed serial interface expansion board, parallel interface expansion board or acquisition controller direct proximity connection;

The pseudo-random sequence code seeds of multiple modes generated by this device are used as the mode code, and the mode is compared with the measured sequence generated by the device under test. After a sequence comparison, a sequence consistent with the mode code is found, and the mode code is based on the consistent sequence. Generate its follow-up corresponding sequence, and compare it bit by bit with the measured sequence, so as to realize error detection.

Further, the device of the present invention also includes an SFP+ optical fiber module and an SFP/SFP+ connector, and the SFP/SFP+ connector is arranged on the acquisition controller; the device under test is connected to the SFP+ optical fiber module through an optical fiber, and the SFP+ optical fiber module is inserted into the SFP/SFP+ The connector realizes the remote connection between the device under test and the acquisition controller.

Further, the short-range connection of the present invention includes three ways:

The high-speed serial interface expansion board is provided with a first SMA high-speed SEDES port, and the device under test is connected to the first SMA high-speed SEDES port through a coaxial cable;

The device under test is connected to the parallel interface expansion board through the IDE line;

The acquisition controller is provided with a second SMA high-speed SEDES port, and the device under test is connected to the second SMA high-speed SEDES port through a coaxial cable.

Further, the acquisition controller of the present invention is a KC705Kintex-7 development board using an FPGA chip.

Further, the remote terminal of the present invention is a notebook computer or a PC computer.

Further, the acquisition controller of the present invention includes an interconnected pseudo-random sequencer generation module, a TEMAC network module, a GTX module, a FIFO module and an error detection module; the pseudo-random sequence code pattern generated by the pseudo-random sequencer generation module includes PRBS7, PRBS15, PRBS23, PRBS31.

Further, the device of the present invention also includes a serializer and a deserializer; the output of the pseudo-random sequencer is connected to the device under test through the serializer; the output of the device under test is connected to the error detection module through the deserializer Connected; the transmission rate of serializer and deserializer includes 3.125Gbps, 4.8Gbps, 5.0Gbps, 5.12Gbps, 6.25Gbps, 8Gbps, 10Gbps.

Further, the parallel interface expansion board of the present invention is provided with multiple columns of IDE interfaces.

The invention provides a portable long-distance multi-channel communication device bit error rate testing method, comprising the following steps:

Select the connection mode of the device according to the test environment: the normal environment is the area where the operator can move normally; the harsher environment is the area that is harmful to the human body but has no effect on the device hardware; the harsh environment is the area that affects the normal operation of the device hardware;

If it is a normal environment, use the short-range connection method to directly connect the device under test located in the normal environment to the high-speed serial interface expansion board, parallel interface expansion board or acquisition controller, and the operator will perform short-distance testing;

If it is a harsh environment, use a short-range connection method to directly connect the device under test in a harsh environment to a high-speed serial interface expansion board, a parallel interface expansion board or an acquisition controller, and connect the acquisition controller to the remote controller through a network cable. Terminal, the operator conducts remote testing;

If it is a harsh environment, use the remote connection method to connect the device under test located in the harsh environment to the SFP+ optical fiber module through an optical fiber, insert the SFP+ optical fiber module into the SFP/SFP+ connector of the remote acquisition controller, and the operator performs Remote testing.

Further, the test content of the test device in the method of the present invention includes: loopback test, optical fiber transmission bit error rate test, and chip test.

The beneficial effects produced by the present invention are: the portable long-distance multi-channel communication device bit error rate testing device and method of the present invention, based on a high-performance acquisition controller with a high-speed serial transmitter, has designed a multi-channel serial With the function of parallel channel, and can realize the long-distance bit error rate testing device, the present invention is suitable for carrying out long-distance bit error detection to devices such as optical and electrical transmitters/receivers, serializers and deserializers in communication, and is low-cost and portable .

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

Fig. 1 is the overall layout diagram of the device of the embodiment of the present invention;

Fig. 2 is the working principle diagram of the device of the embodiment of the present invention;

Fig. 3 is a schematic diagram of a high-speed serial interface expansion board according to an embodiment of the present invention;

4 is a schematic diagram of a parallel interface expansion board according to an embodiment of the present invention;

Fig. 5 is a schematic diagram of line connection according to an embodiment of the present invention;

FIG. 6 is a reference clock frequency and a corresponding transmission rate during serial transmission according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a photoelectric conversion panel according to an embodiment of the present invention;

Fig. 8 is a schematic diagram of the LOCx2 test of the embodiment of the present invention;

In the figure: 1-high-speed serial interface expansion board, 2-first FMC interface, 3-first SMA high-speed SEDES port, 4-serial reference clock access port, 5-parallel interface expansion board, 6-second FMC Interface, 7-first IDE interface, 8-second IDE interface, 9-acquisition controller, 10-clock generator, 11-remote terminal, 12-LPC interface, 13-HPC interface, 14-SFP/SFP+ connector , 15-the first RJ45 interface, 16-the first USB interface, 17-the second USB interface, 18-the second RJ45 interface, 19-USB extension cable, 20-the second SMA high-speed SEDES port, 21-photoelectric conversion board, 22-SFP connection socket, 23-SMA socket group, 24-SFP+ fiber optic module.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in Figure 1, the portable long-distance multi-channel communication device BER testing device of the embodiment of the present invention comprises a high-speed serial interface expansion board, a parallel interface expansion board, an SFP+ optical fiber module (Finisar FTLX8571D3BCL), an SFP/SFP+ connection device, clock generator (Si5338), acquisition controller, notebook computer; the device under test is connected to the high-speed serial interface expansion board, parallel interface expansion board or SFP+ optical fiber module through a copper axis cable or optical fiber; the two expansion boards are connected through The FMC interface is connected to the HPC port and the LPC interface of the acquisition controller, and the SFP+ optical fiber module is connected to the optical fiber module socket of the acquisition controller. The clock generator generates the working clock and is connected to the high-speed serial interface expansion board and the serial clock input interface of the acquisition controller through the copper axis cable; computer communication.

This device uses multi-mode pseudo-random sequence (PRBS) as source information, uses digital logic calculation method to generate four pseudo-random sequences of 7, 15, 23, and 31, and realizes the parallel data output capability of up to 640MHz and up to 68 lines.

Through the research on the configuration method of the high-performance FPGA chip Kintex-7 high-speed transmitter, this device has customized and designed 7 channels with serial transmission rates of 3.125Gbps, 4.8Gbps, 5.0Gbps, 5.12Gbps, 6.25Gbps, 8Gbps, and 10Gbps. Serializer and deserializer; and includes support for 1 fiber optic transmission link. Four of them are output through the self-designed high-speed serial expansion board. The binary files generated by the seven rates can be manually downloaded to the acquisition controller through the iMPACT tool to run as needed.

The device can decode the four pseudo-random sequence codes of PRBS7, PRBS15, PRBS23 and PRBS31 to realize the real-time error detection function.

The device realizes error detection of multi-mode and multi-bit width PRBS by means of state mode matching and other methods. The specific method is to use the pseudo-random sequence code seed of the corresponding pattern generated by the machine at the same time as the pattern code, and compare the patterns of the measured sequence. After a sequence, the sequence time consistent with the pattern code will be found, and then the pattern code will be locked according to The sequence code generation formula synchronously generates the corresponding sequence and compares the measured sequence bit by bit. Thus, error detection is realized.

In this device, the acquisition controller uses the KC705Kintex-7 development board. The acquisition controller function is divided into a pseudo-random sequencer generation module, a TEMAC network module, a GTX module, a FIFO module, and an error detection module.

The pseudo-random sequencer generation module refers to the use of digital logic calculation methods to generate four PRBSs of 7, 15, 23, and 31, and realizes the parallel data output capability of up to 640MHz and up to 68 lines. Taking PRBS7 sequence generation as an example, its generation formula is x0⊕x1=x7. The generation of its sequence can be realized by the following method. From the characteristics of its PRBS7 sequence, it is cycled by 127 bits. Since there are only 127 bits, you can list all 127 bits, and then use the shift operation to generate 40 bits of parallel data. . For PRBS15, PRBS23, and PRBS31, the sequence initialization seed is provided, and then the relevant sequence is generated through the formula of its sequence generation. And generate up to 68 lines of parallel data under the parallel clock recovered by the 640MHz high-speed transmitter. In a specific implementation, a maximum of 68 lines of a certain sequence is selected for output through a four-to-one multiplexer.

High-speed serial interface expansion board, including 10 SMA female sockets and 400-pin FMC interfaces, 8 of which are 4 pairs of differential serial data input sockets, which can guarantee LVDS standard serial data transmission at a rate of up to 10Gbps, and the other 2 are 1 pair Differential is the serial reference clock input socket, which can connect up to 320MHz clock LVDS standard signal through copper axis cable; the parallel interface expansion board leads 68 parallel lines from KC705LPC except power supply, ground and clock signal lines, up to 640MHz LVDS25 signal.

SFP+ fiber optic module, adopts Finisar FTLX8571D3BCL fiber optic module to support 850nm wavelength multimode fiber, and supports 10Gbps transmission rate.

Clock generator using the Si5338EVB RV1.0 evaluation board. Supports clock generation for LVDS signaling standards up to 700MHz.

Laptop, with Core i3 or above CPU, 500GB or above hard disk, 4GB memory, with USB2.0 or above interface, RJ45 network cable interface, and a monitor above 14 inches.

In the device of the present invention, the USB extender adopts a USB transfer network cable with a power supply and an RJ45 port signal amplifier to support the configuration distance of Si5338 up to 100 meters.

The normal environment refers to the area where people can live normally and is also the area where the device laptop is placed; the harsher environment area refers to the area that is not directly irradiated by the radiation source or the area that is harmful to the human body but has no effect on the hardware circuit of the device; the harsh environment area refers to For example, the area directly irradiated by the radiation source or the area that affects the normal operation of the hardware circuit of the device, but the device under test needs to be used in the test environment.

In another specific embodiment of the present invention, the device includes a 68mm*121mm high-speed serial interface expansion board (including an FMC interface male port connected to the HPC, 4 pairs of high-speed SEDES SMA ports and a MGTREFCLK0_118 serial reference clock input port), 68mm*55mm parallel interface expansion board (including FMC interface male port connected to LPC, 40-pin No. 1 IDE port and 40-pin No. 2 IDE port), Si5338 clock generator (including two pairs of LVDS signal output used in this device The CLK0A/CLK0B and CLK1A/CLK1B SMA ports and the No. 1 USB interface provided by the transmission and power supply), the acquisition controller is the KC705 development board (mainly including Kintex-7FPGA, a pair of SMA high-speed SEDES ports, a pair of SMA_MGT_REFCLK 117bank serial reference Clock input port (J10P, J10N), SFP port (SFP/SFP+ connector, FMC LPC female port, FMC HPC female port and No. 1 RJ45 port) and laptop (including No. 2 RJ45 port and No. 2 USB port).

The device under test is connected to any pair of 4 pairs of high-speed SEDES SMA ports of the high-speed serial interface expansion board or a pair of SMA high-speed SEDES ports of the acquisition controller or connected to the 40 tubes of the parallel interface expansion board through an IDE cable through a copper axis cable. Pin No. 1 IDE port or 40-pin No. 2 IDE port; the high-speed serial interface expansion board is connected to the FMC HPC female port on the collector through the FMC interface male port of the HPC, and the parallel interface expansion board is connected to the FMC HPC female port through the two expansion boards. Connect the FMC interface male port of LPC to the FMC LPC female port on the collector;

The device under test can also be connected to the SFP+ optical fiber module through an optical fiber and then inserted into the SFP port of the acquisition controller to realize photoelectric conversion and then enter the Kintex-7FPGA for detection. The Si5338 clock generator generates the working clock required for serial transmission and outputs it to CLK0A and CLK0B through a copper cable to connect to the MGTREFCLK0_118 serial reference clock port of the high-speed serial interface expansion board and to the J10P of the acquisition controller through the output of CLK1A and CLK1B On the serial reference clock input interface of J10N, the No. 2 USB port of the notebook computer can reach 100 meters through the USB extender and use the network cable to communicate with the No. 1 USB port on the Si5338 clock generator to configure the reference clock and extend it through USB. The controller ensures the goal of passing the network remote bit error rate test; the acquisition controller realizes the network functions of acquisition, detection, control and generation of the MAC protocol, and is connected to the No. 2 RJ45 network port on the notebook computer through the network cable on the No. 1 RJ45 network port. communication. Run the program written by Labveiw on the laptop to analyze the uploaded network packets for real-time recording and display.

Three test experiments were carried out as follows:

1. Loopback test experiment

Connect the sending end of the 4 pairs of high-speed SEDES SMA ports on the high-speed serial interface expansion board to the paired receiving end (P port, N port) through a copper cable, and configure the clock generator to generate 320MHz reference clock signals CLK0A and The CLK0B output is connected to the MGTREFCLK0_118 serial reference clock port of the high-speed serial interface expansion board, and the No. 1 RJ45 15 on the acquisition controller is connected to the No. 2 RJ45 on the notebook computer through a network cable; The FPGA firmware is downloaded to the acquisition controller. By running the monitoring program written by Labview on the laptop, test the bit error rate during normal operation. Run time 20 minutes. Then press the SW4 button on the KC705 development board to inject errors, inject one bit into all serial channels at a time, observe the changes in error counts, and check the log records when this round of testing is over. Then change the frequency of the reference clock signal generated by the clock generator and the corresponding transmission rate FPGA firmware and download it to the acquisition controller, and then repeat the above steps until all 7 rates are measured. The optical fiber serial channel and the SMA high-speed SEDES port channel onboard the KC705 also use the above method for loopback testing. The SFP+ fiber optic module in the fiber optic serial The optical output is connected to the optical input port to form a loop. Repeated testing of 7 transmission rates and six high-speed serial channels are all running normally.

2. Bit error rate test of AVAGO AFBR-57D7APZ SFP+ optical fiber module

AVAGO AFBR-57D7APZ SFP+ fiber optic module supports multimode fiber to generate 850nm wavelength, up to 8.5Gbps, use this device to test its bit error rate index. The connection is shown in Figure 7, the AVAGO AFBR-57D7APZ SFP+ fiber optic module is inserted into the photoelectric conversion board, the 1-meter multimode fiber is connected to the optical output and input ports of the AVAGO AFBR-57D7APZ SFP+ fiber optic module, and J13 of the SMA socket group of the photoelectric conversion board The receiving port is connected to the J11 sending port of the acquisition controller, and at the same time, the J14 sending port of the SMA socket group of the photoelectric conversion board is connected to the J12 receiving port of the acquisition controller. Using 8Gbps rate, PRBS31 mode, according to Figure 6 and Figure 5, the Si5338 clock generator is configured as CLK1A/CLK1B output 125MHz clock, download 8Gbps rate firmware to the FPGA of the acquisition controller, and run for 20 minutes. Due to the network connection between the acquisition controller and Si5338 and the notebook computer, other parts of the device except the notebook computer used for monitoring and recording data can be in a harsh environment, and the tested AVAGO AFBR-57D7APZ SFP+ optical fiber module It can be tested for bit error rate under harsh conditions, such as strong x-ray environment.

3. LOCx2 chip test

LOCx2 is a 2-channel data transmission chip that integrates linear coding and transmission and is specially designed for working in strong radiation environments. The transmission rate of each channel is 5.12Gbps. The schematic diagram of the LOCx2 test is shown in Figure 8. The LOCx2 board is connected to the clock and other signals according to the working needs of the chip. The parallel expansion board of the device is connected to the parallel input port of the LOCx2 board through the 40-line IDE line. The optical fiber is connected to the SFP RX of the SFP fiber module inserted in the SFP port on the KC705 development board of the device, and the other signal is connected to the SMA RX of a pair of SMA high-speed SEDES ports of the KC705 of the device through a cable. Configure the Si5338 generator to generate a 320MHz reference clock output from the CLK1 port and connect it to the reference clock input port J10 of the high-speed serial transmitter bank117 of the KC705 development board of the device through a cable; download the serial rate with the LOCx2 decoder at 5.12Gbps And the parallel port outputs two 8-bit wide PRBS7 pseudo-random sequence firmwares of 640MHz to KC705, and then runs for 1 hour to observe and record the bit error rate in real time and test the bit error rate. LOCx2 is a chip for working in a strong radiation environment. It can be placed under neutron source radiation or x-ray for bit error rate testing. In this way, it is convenient for the test personnel to conduct the test safely away from the radiation area.

It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should belong to the protection scope of the appended claims of the present invention.

Claims (10)

1. a kind of multichannel communication multiple telecommunication device error rate test device of portable long distance, which is characterized in that the device includes：At a high speed Serial line interface expansion board (1), parallel interface expansion board (5), clock generator (10), acquisition controller (9), USB extended lines (19) and remote terminal (11)；Wherein：

LPC interfaces (12), HPC interfaces (13), the first RJ45 interfaces (15) and serial reference are provided on acquisition controller (9) Clock interface；The first USB interface (16) and multiple clock signal output interfaces are provided on clock generator (10)；Remote terminal (11) secondary USB interface (17) and the 2nd RJ45 interfaces (18) are provided on；HSSI High-Speed Serial Interface expansion board (1) and parallel interface Expansion board is both provided with FMC interfaces and serial reference clock interface on (5)；

HSSI High-Speed Serial Interface expansion board (1) is connected by the first FMC interfaces (2) with the HPC interfaces (13) of acquisition controller (9), Parallel interface expansion board (5) is connected by the 2nd FMC interfaces (6) with the LPC interfaces (12) of acquisition controller (9)；

Clock generator (10) by clock signal output interface respectively with HSSI High-Speed Serial Interface expansion board (1), acquisition controller (9) serial reference clock interface is connected；The first USB interface (16) on clock generator (10) passes through USB extended lines (19) It is connected with the secondary USB interface (17) on remote terminal (11)；The first RJ45 interfaces (15) on acquisition controller (9) pass through net Line is connected with the 2nd RJ45 interfaces (18) on remote terminal (11)；

The connection type of measured device and the device includes：Long-range connection is connected with short range；Measured device passes through optical fiber and acquisition Controller (9) realizes long-range connection；Measured device and HSSI High-Speed Serial Interface expansion board (1), parallel interface expansion board (5) or acquisition Controller (9) directly short range connection；

The pseudo random sequence code seed that various modes are generated by the present apparatus is used as mode code, is sequenced with what measured device generated Row carry out pattern comparison, finds the sequence consistent with mode code, mode code is according to consistent sequence after the comparison by one section of sequence Row generate its subsequent corresponding sequence, are carried out by bit comparison with tested sequence, to realize error detection.

2. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that The device further includes SFP+ optic modules (24) and SFP/SFP+ connectors (14), and SFP/SFP+ connectors (14) setting is acquiring On controller (9)；Measured device is connected to SFP+ optic modules (24) by optical fiber, and SFP+ optic modules (24) are inserted into SFP/ SFP+ connectors (14) realize the long-range connection of measured device and acquisition controller (9).

3. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that Short range connection includes three kinds of modes：

The first ports SMA high speed SEDES (3) are provided in HSSI High-Speed Serial Interface expansion board (1), measured device passes through coaxial cable It is connect with the first ports SMA high speed SEDES (3)；

Measured device is connect by IDE lines with parallel interface expansion board (5)；

The 2nd ports SMA high speed SEDES (20) are provided on acquisition controller (9), measured device passes through coaxial cable and second The ports SMA high speed SEDES (20) connect.

4. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that Acquisition controller (9) is the KC705Kintex-7 development boards using fpga chip.

5. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that Remote terminal (11) is laptop or PC computers.

6. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that Acquisition controller (9) includes the pseudo-random sequence device generation module being connected with each other, TEMAC network modules, GTX modules, FIFO moulds Block and error detection modules；Pseudo-random sequence device generation module generate pseudo-random sequence pattern include PRBS7, PRBS15、PRBS23、PRBS31。

7. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 6, which is characterized in that The device further includes serializer and deserializer；The output end of pseudo-random sequence device is connected by serializer with measured device；Quilt The output end for surveying device is connected by deserializer with error detection modules；The transmission rate of serializer and deserializer includes 3.125Gbps、4.8Gbps、5.0Gbps、5.12Gbps、6.25Gbps、8Gbps、10Gbps。

8. the multichannel communication multiple telecommunication device error rate test device of portable long distance according to claim 1, which is characterized in that Parallel interface expansion board is provided with multiple row ide interface on (5).

9. a kind of test method of the multichannel communication multiple telecommunication device error rate test device of portable long distance using claim 1, It is characterized in that including the following steps：

According to the connection type of test environment selection device：Conventional environment is the region of operating personnel's energy normal activity；It is relatively severe Environment is to have injury to human body, but on region of the device hardware without influence；Adverse circumstances are to influence device hardware to work normally Region；

If conventional environment, by the way of short range connection, by the measured device and HSSI High-Speed Serial Interface in conventional environment Expansion board, parallel interface expansion board or acquisition controller are directly connected to, and operating personnel carry out short range test；

It, will be positioned at compared with the measured device and high speed serialization in adverse circumstances by the way of short range connection if compared with adverse circumstances Interface expansion board, parallel interface expansion board or acquisition controller are directly connected to, and acquisition controller and long-range end are connected by cable End, operating personnel carry out remote testing；

If adverse circumstances, by the way of remotely connecting, the measured device in adverse circumstances is connected to by optical fiber SFP+ optic modules are inserted into the SFP/SFP+ connectors of long-range acquisition controller, operator by SFP+ optic modules Member carries out remote testing.

10. the multichannel communication multiple telecommunication device test method for bit error rate of portable long distance according to claim 9, feature exist In the test content carried out to test device in this method includes：Loopback test, the test of optical fiber transmission error rates, chip testing.