CN108475680A - The preparation method of field-effect transistor and field-effect transistor - Google Patents
The preparation method of field-effect transistor and field-effect transistor Download PDFInfo
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Abstract
The preparation method of a kind of field-effect transistor (10) and field-effect transistor is provided.Field-effect transistor includes substrate (110), and substrate includes first surface (110a)；Grid (120), grid is embedded at substrate from first surface, and the end face of grid is concordant with first surface；Gate dielectric layer (130) covers first surface and the grid end face concordant with first surface；The surface for deviating from substrate in gate dielectric layer is arranged in graphene layer (140)；The surface for deviating from gate dielectric layer in graphene layer is arranged in source electrode (150)；And drain electrode (160), the surface that gate dielectric layer is deviated from graphene layer is set, and gap is equipped between source electrode.
Description
The present invention relates to technical field of semiconductors more particularly to the preparation methods of a kind of field effect transistor and field effect transistor.
Field effect transistor (Field Effect Transistor, it FET) is one of primary element mostly important in current integrated circuit, structure is mainly made of source electrode (S), drain electrode (D), channel layer (CH), grid (G) and substrate.Graphene is the two-dimensional material being made of carbon atom, is received significant attention due to the unique physicochemical properties such as mobility with higher.However, graphene field effect transistor (Graphene Field Effect Transistor as graphene radio circuit basic unit, G-FET desired high-performance) is not obtained at present, reason first is that graphene is a kind of material that chemical property is stable, nonpolarity, hydrophobic, its surface is difficult to obtain the dielectric of better quality, this is also G-FET self-alignment structure one of reason relatively difficult to achieve.In the prior art, graphene layer is arranged adjacent to a substrate, and the surface that graphene layer deviates from substrate is arranged in seed layer, and gate dielectric layer is arranged on the seed layer, and the seed layer is arranged on the graphene layer to promote gate dielectric layer preferably to grow.However, when the seed layer is organic matter, since the dielectric constant of organic matter is smaller, the seed layer influences whether the size of gate capacitance, and then influences gate electric field to the regulating and controlling effect of channel layer.When the seed layer be inorganic matter (such as, aluminum oxide nanoparticle) when, although the dielectric constant of inorganic matter is bigger than the dielectric constant of organic matter, but, when the subsequent gate dielectric layer of formation on the seed layer, the interface formed between seed layer and gate dielectric layer can have many boundary defects, and then influence the performance of G-FET.In conclusion the performance of G-FET is bad in the prior art.
Summary of the invention
In a first aspect, the present invention provides a kind of field effect transistor, the field effect transistor includes:
Substrate, the substrate include first surface；
Grid, the grid are embedded in the substrate from the first surface, and an end face of the grid is concordant with the first surface；
Gate dielectric layer covers the first surface and the grid end face concordant with the first surface；
The surface that the gate dielectric layer deviates from the substrate is arranged in graphene layer；
The surface that the graphene layer deviates from the gate dielectric layer is arranged in source electrode；And
Drain electrode is arranged in the surface that the graphene layer deviates from the gate dielectric layer, and is equipped with gap between the source electrode.
In the first embodiment, the grid includes first end face, second end face and third end face, the end face concordant with the first surface is defined as the first end face, the second end face is oppositely arranged with the third end face, the second end face and the third end face are intersected with the first end face respectively, and the second end face is coplanar with end face of the source side to the drain electrode, the third end face is coplanar in face of the end face of the source electrode with the drain electrode.
Further, the material of the substrate include in the electrically insulating materials such as quartz, mica, aluminium oxide or transparent plastic any one or it is a variety of.
Further, the material of the grid include in the materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni any one or it is a variety of.
Further, the gate dielectric layer includes HfO2、ZrO2、Al2O3、SiO2、Si3N4In equal materials any one or it is a variety of.
Further, the graphene layer includes any one in single-layer graphene, bilayer graphene or multi-layer graphene.
Further, any one the perhaps a variety of or source electrode and the drain electrode of the source electrode and the drain electrode including Pt, Au, Al, Ni, Cu, Ag, Ti, Sc, Y etc. in metal materials can also be Multi-layer graphite or tin indium oxide.
In the second embodiment, it is more than the insulating substrate for presetting light transmittance that the substrate, which is to the light transmittance of ultraviolet light,.
In the third embodiment, the graphene layer includes any one in single-layer graphene, bilayer graphene or multi-layer graphene.
In the 4th kind of embodiment, the thickness of the grid is greater than 10nm.
Compared to the prior art, gate dielectric layer is formed directly on the first surface in field effect transistor of the invention, can obtain the gate dielectric layer of high quality.The surface that gate dielectric layer deviates from the substrate is arranged in the graphene layer, therefore, eliminates and is difficult to the technical issues of forming gate dielectric layer when gate dielectric layer is arranged in graphene layer surface in the prior art.And graphene layer is set on gate dielectric layer of the invention and has lacked one layer of seed layer compared to the prior art, therefore, field effect transistor of the invention is thinner.Further, due to the present invention
Field effect transistor in graphene layer be set up directly on gate dielectric layer, there is no seed layer between graphene layer and gate dielectric layer, the technical issues of size of seed layer influence gate capacitance and seed layer and gate dielectric layer brought by introduction seed layer form boundary defect in the prior art is resolved, to improve the performance of field effect transistor of the present invention.
Further, the substrate, high-frequency loss caused by can inhibiting because of substrate are embedded in from the middle part of the first surface due to the grid in field effect transistor of the invention.
Furthermore, since the second end face of the grid is coplanar with end face of the source side to the drain electrode, the third end face of the grid is coplanar in face of the end face of the source electrode with the drain electrode, therefore, there is no insulating medium sidewall is not present between insulating medium sidewall and the grid and the drain electrode between the grid and the source electrode, to inhibit channel portion parasitic resistance effect that may be present in the field effect transistor.Further, since the second end face of the grid is coplanar with end face of the source side to the drain electrode, the third end face of the grid is coplanar in face of the end face of the source electrode with the drain electrode, the grid and the source electrode do not overlap, without overlapping between the grid and the drain electrode, therefore, the parasitic capacitance between the grid and the source electrode is smaller, and the parasitic capacitance between the grid and the drain electrode is smaller.
Further, the present invention in field effect transistor in the grid, the source electrode and the drain electrode can be made thicker, without obviously increase parasitic capacitance and.And thicker grid, source electrode and thicker drain electrode can reduce the resistance of these electrodes itself, the dead resistance that can also inhibit these electrodes to generate.
Second aspect, the present invention provides a kind of preparation method of field effect transistor, the preparation method of the field effect transistor includes:
Step S110, provides a substrate, and the substrate includes the first surface and second surface being oppositely arranged；
Step S120 forms grid, and the grid is embedded in the substrate from the first surface, and an end face of the grid is concordant with the first surface；
Step S130, forms gate dielectric layer, and the gate dielectric layer covers the first surface and the grid end face concordant with the first surface；
Step S140, forms graphene layer, and the surface that the gate dielectric layer deviates from the substrate is arranged in the graphene layer；
Step S150 forms source electrode and drain electrode, and the surface that the graphene layer deviates from the gate dielectric layer is arranged in the source electrode and the drain electrode, and gap is equipped between the source electrode and the drain electrode.
In the first embodiment, the step S120 includes:
Step S121 is coated with the first photoresist layer in the first surface；
Step S122 patterns first photoresist layer, to remove the first photoresist layer of part for covering the first surface；
Step S123 carries out plasma etching to the first surface using remaining first photoresist layer as exposure mask, to form groove on the first surface；
Step S124, forms the first metal layer, and the first metal layer covers first photoresist layer and the filling groove, wherein the thickness of the first metal layer is greater than or equal to the depth of the groove；
Step S125, remove remaining first photoresist layer, and the first metal layer part that will be above the groove removes, so that the end face for being located at the first metal layer of the groove is concordant with the first surface, in the groove and the first metal layer that end face is concordant with the first surface is the grid.
In the second embodiment, the step S140 includes:
Step S141 provides a substrate；
Step S142 forms graphene layer on a surface of the substrate；
The substrate for being formed with the graphene layer is transferred to the surface that the gate dielectric layer deviates from the first surface, the graphene layer is transferred on the surface of the gate dielectric layer, and remove the substrate by step S143.
In the third embodiment, the grid includes first end face, second end face and third end face, the end face concordant with the first surface is defined as first end face, the second end face is oppositely arranged with the third end face, the second end face and the third end face are intersected with the first end face respectively, and the second end face is coplanar with end face of the source side to the drain electrode, the third end face is coplanar in face of the end face of the source electrode with the drain electrode.
In conjunction with the third embodiment, in the 4th kind of embodiment, the substrate includes third surface and the 4th surface, the third surface is oppositely arranged with the 4th surface, the third surface and the 4th surface are intersected with the first surface respectively, and the third surface is arranged compared to the 4th surface adjacent to the second end face, the step S150 includes:
Step S151 is coated with the second photoresist layer away from the surface of the gate dielectric layer in the graphene layer；
Step S152, pattern second photoresist layer, to retain first part, second part and Part III, the first part is set between the second part and the Part III, and the first gap is formed between the first part and the second part, shape between the first part and the Part III
At the second gap, first gap and second gap are for appearing part graphene layer, and the first part is coplanar with the second end face in face of the end face of the second part, the first part is coplanar with the third end face in face of the end face of the Part III, end face and the third surface co-planar of the second part away from the first part, end face and fourth surface co-planar of the Part III away from the first part；
Step S153 forms second metal layer, and the second metal layer covers the first part, the second part, the Part III, and covers the graphene layer manifested by first gap and second gap；
Step S154, remove the first part, the second part and the Part III, it is the source electrode by second metal layer of first gap setting on the graphene layer, is the drain electrode by second metal layer of second gap setting on the graphene layer.
Compared to the prior art, the gate dielectric layer is formed directly on the first surface by the preparation method of field effect transistor of the invention, therefore, can obtain the gate dielectric layer of high quality.The graphene layer is arranged in the gate dielectric layer and deviates from the surface of the substrate, therefore has got around and be difficult to the technical issues of forming the gate dielectric layer of high quality when gate dielectric layer is arranged in graphene layer surface in the prior art.And graphene layer is set on gate dielectric layer of the invention and has lacked one layer of seed layer compared to the prior art, therefore, field effect transistor of the invention is thinner.Further, since graphene layer is set up directly on gate dielectric layer in field effect transistor of the invention, there is no seed layer between graphene layer and gate dielectric layer, the technical issues of size of seed layer influence gate capacitance and seed layer and gate dielectric layer brought by introduction seed layer form boundary defect in the prior art is resolved, to improve the performance of the field effect transistor of preparation.
Since the second end face of the grid is coplanar with end face of the source side to the drain electrode, the third end face of the grid is coplanar in face of the end face of the source electrode with the drain electrode, therefore, there is no insulating medium sidewall is not present between insulating medium sidewall and the grid and the drain electrode between the grid and the source electrode, to inhibit channel portion parasitic resistance effect that may be present in the field effect transistor.Further, since the second end face of the grid is coplanar with end face of the source side to the drain electrode, the third end face of the grid is coplanar in face of the end face of the source electrode with the drain electrode, the grid and the source electrode do not overlap, without overlapping between the grid and the drain electrode, therefore, the parasitic capacitance between the grid and the source electrode is smaller, and the parasitic capacitance between the grid and the drain electrode is smaller.
Further, the preparation method of the field effect transistor in the present invention can be by the grid, the source
Pole and the drain electrode can be made thicker, without obviously increasing parasitic capacitance.And thicker grid, source electrode and thicker drain electrode can reduce the resistance of these electrodes itself, the dead resistance that can also inhibit these electrodes to generate.
Further, the preparation method of field effect transistor of the invention is transferred on the gate dielectric layer again after preparing the graphene layer on a substrate, it has got around in the more difficult problem for forming gate dielectric layer in the surface of graphene layer, to improve the performance of prepared field effect transistor.
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, the drawings to be used in the description of the embodiments or prior art will be briefly described below, apparently, drawings in the following description are only some embodiments of the invention, for those of ordinary skill in the art, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic diagram of the section structure of the field effect transistor of a better embodiment of the invention；
Fig. 2 is the flow chart of the preparation method of the field effect transistor of a better embodiment of the invention；
Fig. 3~Figure 17 is the schematic diagram of each preparation step in the preparation method of the field effect transistor of a better embodiment of the invention.
Following will be combined with the drawings in the embodiments of the present invention, and technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is the schematic diagram of the section structure of the field effect transistor of a better embodiment of the invention.The field effect transistor 10 includes:
Substrate 110, the substrate 110 include first surface 110a；The substrate 110 further includes the second surface 110b being oppositely arranged with the first surface 110a；
Grid 120, the grid 120 are embedded in the substrate 110 from the first surface 110a, and an end face of the grid 120 is concordant with the first surface 110a；
Gate dielectric layer 130 covers the first surface 110a and the grid 120 and the first surface
110a concordant end face；
The surface that the gate dielectric layer 130 deviates from the substrate 110 is arranged in graphene layer 140；
The surface that the graphene layer 140 deviates from the gate dielectric layer 130 is arranged in source electrode 150；And
Drain electrode 160 is arranged in the surface that the graphene layer 140 deviates from the gate dielectric layer 130, and is equipped with gap between the source electrode 150.
Compared to the prior art, gate dielectric layer 130 is formed directly on the first surface 110a in field effect transistor 10 of the invention, can obtain the gate dielectric layer 130 of high quality.The surface that gate dielectric layer 130 deviates from the substrate 110 is arranged in the graphene layer 140, therefore, eliminates and is difficult to the technical issues of forming gate dielectric layer when gate dielectric layer is arranged in graphene layer surface in the prior art.And graphene layer 140 is set on gate dielectric layer 130 of the invention and has lacked one layer of seed layer compared to the prior art, therefore, field effect transistor 10 of the invention is thinner.Further, since graphene layer 140 is set up directly on gate dielectric layer 130 in field effect transistor 10 of the invention, there is no seed layer between graphene layer 140 and gate dielectric layer 130, the technical issues of size of seed layer influence gate capacitance and seed layer and gate dielectric layer brought by introduction seed layer form boundary defect in the prior art is resolved, to improve the performance of field effect transistor 10 of the present invention.
Further, it is embedded in the substrate 110 due to the grid 120 in field effect transistor 10 of the invention from the first surface 110a, high-frequency loss caused by can inhibiting because of substrate 110.The grid 120 includes first end face 121, second end face 122 and third end face 123, the end face concordant with the first surface 110a is defined as the first end face 121, the second end face 122 is oppositely arranged with the third end face 123, the second end face 122 and the third end face 123 are intersected with the first end face 121 respectively, and the second end face 122 is coplanar in face of the end face of the drain electrode 160 with the source electrode 150, the third end face 123 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160.Correspondingly, the substrate 110 further includes third surface 110c and the 4th surface 110d, the third surface 110c and the 4th surface 110d are oppositely arranged, the third surface 110c and the 4th surface 110d intersect with the first surface 110a respectively, and the third surface 110c is arranged compared to the 4th surface 110d adjacent to the second end face 122.
Since the second end face 122 of the grid 120 is coplanar in face of the end face of the drain electrode 160 with the source electrode 150, the third end face 123 of the grid 120 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160, therefore, there is no insulating medium sidewalls and described between the grid 120 and the source electrode 150
Insulating medium sidewall is not present between grid 120 and the drain electrode 160, to inhibit channel portion parasitic resistance effect that may be present in the field effect transistor 10.Further, since the second end face 122 of the grid 120 is coplanar in face of the end face of the drain electrode 160 with the source electrode 150, the third end face 123 of the grid 120 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160, the grid 120 and the source electrode 150 do not overlap, without overlapping between the grid 120 and the drain electrode 160, therefore, the parasitic capacitance C between the grid 120 and the source electrode 150GSSmaller, between the grid 120 and the drain electrode 160 parasitic capacitance CSDIt is smaller.
Further, the grid 120 in the field effect transistor 10 in the present invention, the source electrode 150 and the drain electrode 160 can be made thicker, without obviously increasing parasitic capacitance CGSAnd CSD.And thicker grid 120, source electrode 150 and thicker drain electrode 160 can reduce the resistance of these electrodes itself, the dead resistance that can also inhibit these electrodes to generate.
In the present embodiment, it is more than the insulating substrate for presetting light transmittance that the substrate 110, which is to the light transmittance of ultraviolet light,.The material of the substrate 110 include in the electrically insulating materials such as quartz, mica, aluminium oxide or transparent plastic any one or it is a variety of.The substrate 110 is the high-frequency loss that insulator substrate can reduce the substrate 110.
The material of the grid 120 include in the materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni any one or it is a variety of.The thickness of the grid 120 is greater than 10nm.
The gate dielectric layer 130 includes HfO2、ZrO2、Al2O3、SiO2、Si3N4In equal materials any one or it is a variety of.
The graphene layer 140 includes any one in single-layer graphene, bilayer graphene or multi-layer graphene.
The source electrode 150 and the drain electrode 160 are preferably formed simultaneously in the same process, the source electrode 150 and the drain electrode 160 including Pt, Au, Al, Ni, Cu, Ag, Ti, Sc, Y etc. in metal materials any one or it is a variety of.In another embodiment, the source electrode 150 and the drain electrode 160 can also be Multi-layer graphite or tin indium oxide (Indium Tin Oxide, ITO).
The preparation method of field effect transistor is introduced below with reference to Fig. 1 and previously described field effect transistor 10.Referring to Fig. 2, Fig. 2 is the flow chart of the preparation method of the field effect transistor of a better embodiment of the invention.The preparation method of the field effect transistor 10 includes the following steps.
Step S110, provides a substrate 110, and the substrate 110 includes the first surface 110a being oppositely arranged
And second surface 110b.Also referring to Fig. 3, in the present embodiment, it is more than the insulating substrate for presetting light transmittance that the substrate 110, which is to the light transmittance of ultraviolet light,.The material of the substrate 110 include in the electrically insulating materials such as quartz, mica, aluminium oxide or transparent plastic any one or it is a variety of.The substrate 110 is the high-frequency loss that insulator substrate can reduce the substrate 110.
Step S120 forms grid 120, and the grid 120 is embedded in the substrate 110 from the first surface 110a, and an end face of the grid 120 is concordant with the first surface 110a.The material of the grid 120 include in the materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni any one or it is a variety of.The thickness of the grid 120 is greater than 10nm.
The grid 120 includes first end face 121, second end face 122 and third end face 123, the end face concordant with the first surface 110a is defined as the first end face 121, the second end face 122 is oppositely arranged with the third end face 123, the second end face 122 and the third end face 123 are intersected with the first end face 121 respectively, and the second end face 122 is coplanar in face of the end face of the drain electrode 160 with the source electrode 150, the third end face 123 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160.
In the present embodiment, the step S120 includes the following steps.
Step S121 is coated with the first photoresist layer 181 in the first surface 110a, referring to Figure 4 together.
Step S122 patterns first photoresist layer 181, to remove the first photoresist layer of part 181 for covering the first surface 110a, also referring to Fig. 5.
Step S123 is that exposure mask carries out plasma etching to the first surface 110a with remaining first photoresist layer 181, to form groove 111 on the first surface 110a.Referring to Figure 6 together, carrying out the reaction gas of plasma etching to the first surface 110a can be the fluorine base gas such as carbon tetrafluoride or sulfur hexafluoride.
Step S124, forms the first metal layer 182, and the first metal layer 182 covers first photoresist layer 181 and the filling groove 111, wherein the thickness of the first metal layer 182 is greater than or equal to the depth of the groove 111.Referring to Figure 7 together, the first metal layer 182 can be formed by the method for thermal evaporation, electron beam evaporation or sputtering.
Step S125, remove remaining first photoresist layer 181, and 182 part of the first metal layer that will be above the groove 111 removes, so that the end face for being located at the first metal layer 182 of the groove 111 is concordant with the first surface 110a, be located at the groove 111 it is interior and with end face and first table
Face 110a concordant the first metal layer 182 is the grid 120.Also referring to Fig. 8, in the present embodiment, remaining first photoresist layer 181 can be removed with acetone and other organic solvent, it, can be by the way of chemically mechanical polishing when will be above 182 part of the first metal layer removal of the groove 111.It can be seen that the preparation method of field effect transistor of the invention is compatible with existing CMOS technology.And grid 120 of the invention is embedded in the substrate 110, high-frequency loss caused by can inhibiting because of substrate 10 from the middle part of the first surface 110a.
Step S130, forms gate dielectric layer 130, and the gate dielectric layer 130 covers the first surface 110a and the grid 130 end face concordant with the first surface 110a.Also referring to Fig. 9, the gate dielectric layer 130 includes HfO2、ZrO2、Al2O3、SiO2、Si3N4In equal materials any one or it is a variety of.When forming the gate dielectric layer 130, the gate dielectric layer 130 can be formed using the methods of chemical vapor deposition, atomic layer deposition or physical vapour deposition (PVD).
Step S140, forms graphene layer 140, and the surface that the gate dielectric layer 130 deviates from the substrate 110 is arranged in the graphene layer 140.The graphene layer 140 includes any one in single-layer graphene, bilayer graphene or multi-layer graphene.
In the present embodiment, the step S140 includes the following steps.
Step S141 provides a substrate 183.Also referring to Figure 10, the material of the substrate 183 can be polymethyl methacrylate (Poly methyl methacrylate, PMMA).
Step S142 forms graphene layer 140, also referring to Figure 11 on a surface of the substrate 183.
Step S143, the substrate for being formed with the graphene 184 is transferred to the surface that the gate dielectric layer 130 deviates from the first surface 110a, the graphene layer 140 is transferred on the surface of the gate dielectric layer 130, and removes the substrate 183, also referring to Figure 12.
Step S150 forms source electrode 150 and drain electrode 160, and the surface that the graphene layer 140 deviates from the gate dielectric layer 130 is arranged in the source electrode 150 and the drain electrode 160, and is equipped with gap between the source electrode 150 and the drain electrode 160.
The substrate 110 includes third surface 110c and the 4th surface 110d, the third surface 110c is oppositely arranged with the 4th surface 110d, the third surface 110c and the 4th surface 110d intersect with the first surface 110a respectively, and the third surface 110c is arranged compared to the 4th surface 110d adjacent to the second end face 122.The step S150 includes the following steps.
Step S151 is coated with the second photoresist layer 184 away from the surface of the gate dielectric layer 130 in the graphene layer 140, also referring to Figure 13.
Step S152, pattern second photoresist layer 184, to retain first part 184a, second part 184b and Part III 184c, the first part 184a is set between the second part 184b and the Part III 184c, and the first gap 184d is formed between the first part 184a and the second part 184b, the second gap 184e is formed between the first part 184a and the Part III 184c, the first gap 184d and the second gap 184e is for appearing part graphene layer 140, and the first part 184a is coplanar with the second end face 122 in face of the end face of the second part 184b, the first part 184a faces the end of the Part III 184c Face is coplanar with the third end face 123, and the second part 184b is coplanar with the third surface 110c away from the end face of the first part 184a, and the Part III 184c is coplanar with the 4th surface 110d away from the end face of the first part 184a.
The substrate 110 is to the light transmittance of ultraviolet light more than the insulating substrate of default light transmittance, and second photoresist layer 184 is ultraviolet light photosensitive photoresist layer.That is, the partial disappearance for the second photoresist layer 184 being mapped to by ultraviolet lighting, is not retained by the part of the second photoresist layer 184 of ultraviolet light.In the present embodiment, the step S152 includes the following steps.
Step S152a, light source 186 and mask plate 187 are provided, the light source 186 and the mask plate 187 are arranged adjacent to the second surface 110b, and the mask plate 186 is set between the light source 186 and the second surface 110b, the light source 186 is for issuing ultraviolet light, the mask plate 187 includes the first transmittance section 187a, second transmittance section 187b and third transmittance section 187c, the first transmittance section 187a corresponds to the setting of grid 120 and the length of the first transmittance section 187a is greater than 120 length of grid, the second transmittance section 187b and third transmittance section 187c is respectively arranged at the opposite both ends the first transmittance section 187a, and the second transmittance section 187b is saturating compared to the third Light portion 187c is arranged adjacent to the third surface 110c, the second transmittance section 187b is coplanar with the third surface 110c away from the end face of the first part 184a, the third transmittance section 187c is coplanar with the 4th surface 110d away from the end face of the first transmittance section 187a, and the first transmittance section 187a is greater than or equal to the first light transmittance to the light transmittance of the ultraviolet light, the second transmittance section 187b and third transmittance section 187c is less than or equal to the second light transmittance to the light transmittance of the ultraviolet light, and first light transmittance is greater than second light transmittance.For example, first light transmittance is 95% even higher, and second light transmittance is 5% even more small.At this time, it is believed that the ultraviolet light that the light source 186 issues can penetrate the first transmittance section 187a, and
The ultraviolet light that the light source 186 issues can hardly penetrate the second transmittance section 187b and third transmittance section 187c, also referring to Figure 14.
Step S152b is that the ultraviolet light that exposure mask is issued using the light source 186 is exposed second photoresist layer 184 with the mask plate 187, to form the first part 184a, the second part 184b and the Part III 184c.Also referring to Figure 15, since the ultraviolet light that the light source 186 issues can hardly penetrate the second transmittance section 187b and third transmittance section 187c, therefore, the part of the corresponding second transmittance section 187b and third transmittance section 187c of second photoresist layer 184 is retained to be respectively formed the second part 184b and Part III 184c.And the grid 120 can not penetrate ultraviolet light, therefore, the second photoresist layer 184 of the corresponding grid 120 is retained, to form the first part 184a.
Step S153, form second metal layer 185, the second metal layer 185 covers the first part 184a, the second part 184b and the Part III 184c, and the graphene layer 140 manifested is covered by the first gap 184d and the second gap 184e, also referring to Figure 16.
Step S154, remove the first part 184a, the second part 184b and the Part III 184c, it is the source electrode 150 that the second metal layer 185 on the graphene layer 140, which is arranged in, by the first gap 184d, it is the drain electrode 160 that the second metal layer 185 on the graphene layer 140, which is arranged in, by the second gap 184e, also referring to Figure 17.
Compared to the prior art, the gate dielectric layer 130 is formed directly on the first surface 110 by the preparation method of field effect transistor of the invention, therefore, can obtain the gate dielectric layer 130 of high quality.The graphene layer 140 is arranged in the gate dielectric layer 130 and deviates from the surface of the substrate 110, therefore has got around and be difficult to the technical issues of forming the gate dielectric layer of high quality when gate dielectric layer is arranged in graphene layer surface in the prior art.And graphene layer 140 is set on gate dielectric layer 130 of the invention and has lacked one layer of seed layer compared to the prior art, therefore, field effect transistor 10 of the invention is thinner.Further, since graphene layer 140 is set up directly on further in field effect transistor 10 of the invention, since graphene layer 140 is set up directly on gate dielectric layer 130 in field effect transistor 10 of the invention, there is no seed layer between graphene layer 140 and gate dielectric layer 130, the technical issues of size of seed layer influence gate capacitance and seed layer and gate dielectric layer brought by introduction seed layer form boundary defect in the prior art is resolved, to improve the performance of the field effect transistor 10 of preparation.
Since the second end face 122 of the grid 120 and the source electrode 150 are in face of the end of the drain electrode 160
Face is coplanar, the third end face 123 of the grid 120 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160, therefore, there is no insulating medium sidewall is not present between insulating medium sidewall and the grid 120 and the drain electrode 160 between the grid 120 and the source electrode 150, to inhibit channel portion parasitic resistance effect that may be present in the field effect transistor 10.Further, since the second end face 122 of the grid 120 is coplanar in face of the end face of the drain electrode 160 with the source electrode 150, the third end face 123 of the grid 120 is coplanar in face of the end face of the source electrode 150 with the drain electrode 160, the grid 120 and the source electrode 150 do not overlap, without overlapping between the grid 120 and the drain electrode 160, therefore, the parasitic capacitance C between the grid 120 and the source electrode 150GSSmaller, between the grid 120 and the drain electrode 160 parasitic capacitance CSDIt is smaller.
Further, the grid 120, the source electrode 150 and the drain electrode 160 can be made thicker by the preparation method of the field effect transistor in the present invention, without obviously increasing parasitic capacitance CGSAnd CSD.And thicker grid 120, source electrode 150 and thicker drain electrode 160 can reduce the resistance of these electrodes itself, the dead resistance that can also inhibit these electrodes to generate.
Further, the preparation method of field effect transistor of the invention is transferred on the gate dielectric layer 130 again after preparing the graphene layer 140 on a substrate, it has got around in the more difficult problem for forming gate dielectric layer 130 in the surface of graphene layer 140, to improve the performance for the field effect transistor prepared.
Technical term used in the embodiment of the present invention is merely to illustrate specific embodiment and is not intended to be limiting the present invention.Herein, singular " one ", "the" and " described " for simultaneously including plural form, unless clearly being explained separately in context.Further, refer to that there are the feature, entirety, step, operation, element and/or components for " include " and or " include " used in the description, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, operation, element and/or component.
The equivalent form (if present) of counter structure, material, movement and all devices or step and function element is intended to include any structure, material or the movement that the element being distinctly claimed in conjunction with other is used to execute the function in the following claims.Description of the invention for embodiment and the purpose of description are presented, but be not intended to exhaustion or will be limited in disclosed form by invention.Without departing from the scope and spirit of the invention, a variety of modification and variation are obvious for those of ordinary skill in the art.Embodiment described in the present invention can preferably disclose the principle of the present invention and practical application, and those of ordinary skill in the art is made to can be appreciated that the present invention.
Flow chart described in the present invention is only one embodiment, without deviating from the spirit of the present invention to the step in this diagram or the present invention can there are many modifications to change.For example, can execution these steps in different order, either can increase, delete or modify certain steps.Those of ordinary skill in the art are understood that realize all or part of the process of above-described embodiment, and equivalent changes made in accordance with the claims of the present invention, still belong to the scope covered by the invention.
Claims (11)
- A kind of field effect transistor, which is characterized in that the field effect transistor includes:Substrate, the substrate include first surface；Grid, the grid are embedded in the substrate from the first surface, and an end face of the grid is concordant with the first surface；Gate dielectric layer covers the first surface and the grid end face concordant with the first surface；The surface that the gate dielectric layer deviates from the substrate is arranged in graphene layer；The surface that the graphene layer deviates from the gate dielectric layer is arranged in source electrode；AndDrain electrode is arranged in the surface that the graphene layer deviates from the gate dielectric layer, and is equipped with gap between the source electrode.
- Field effect transistor as described in claim 1, it is characterized in that, the grid includes first end face, second end face and third end face, the end face concordant with the first surface is defined as the first end face, the second end face is oppositely arranged with the third end face, the second end face and the third end face are intersected with the first end face respectively, and the second end face is coplanar with end face of the source side to the drain electrode, the third end face is coplanar in face of the end face of the source electrode with the drain electrode.
- Field effect transistor as described in claim 1, which is characterized in that it is more than the insulating substrate for presetting light transmittance that the substrate, which is to the light transmittance of ultraviolet light,.
- Field effect transistor as described in claim 1, which is characterized in that the graphene layer includes any one in single-layer graphene, bilayer graphene or multi-layer graphene.
- Field effect transistor as described in claim 1, which is characterized in that the thickness of the grid is greater than 10nm.
- A kind of preparation method of field effect transistor, which is characterized in that the preparation of the field effect transistor Method includes:Step S110, provides a substrate, and the substrate includes the first surface and second surface being oppositely arranged；Step S120 forms grid, and the grid is embedded in the substrate from the first surface, and an end face of the grid is concordant with the first surface；Step S130, forms gate dielectric layer, and the gate dielectric layer covers the first surface and the grid end face concordant with the first surface；Step S140, forms graphene layer, and the surface that the gate dielectric layer deviates from the substrate is arranged in the graphene layer；Step S150 forms source electrode and drain electrode, and the surface that the graphene layer deviates from the gate dielectric layer is arranged in the source electrode and the drain electrode, and gap is equipped between the source electrode and the drain electrode.
- The preparation method of field effect transistor as claimed in claim 6, which is characterized in that the step S120 includes:Step S121 is coated with the first photoresist layer in the first surface；Step S122 patterns first photoresist layer, to remove the first photoresist layer of part for covering the first surface；Step S123 carries out plasma etching to the first surface using remaining first photoresist layer as exposure mask, to form groove on the first surface；Step S124, forms the first metal layer, and the first metal layer covers first photoresist layer and the filling groove, wherein the thickness of the first metal layer is greater than or equal to the depth of the groove；Step S125, remove remaining first photoresist layer, and the first metal layer part that will be above the groove removes, so that the end face for being located at the first metal layer of the groove is concordant with the first surface, in the groove and the first metal layer that end face is concordant with the first surface is the grid.
- The preparation method of field effect transistor as claimed in claim 6, which is characterized in that the step S140 includes:Step S141 provides a substrate；Step S142 forms graphene layer on a surface of the substrate；The substrate for being formed with the graphene layer is transferred to the gate dielectric layer away from described by step S143 The graphene layer is transferred on the surface of the gate dielectric layer by the surface of first surface, and removes the substrate.
- The preparation method of field effect transistor as claimed in claim 6, it is characterized in that, the grid includes first end face, second end face and third end face, the end face concordant with the first surface is defined as first end face, the second end face is oppositely arranged with the third end face, the second end face and the third end face are intersected with the first end face respectively, and the second end face is coplanar with end face of the source side to the drain electrode, the third end face is coplanar in face of the end face of the source electrode with the drain electrode.
- The preparation method of field effect transistor as claimed in claim 9, it is characterized in that, the substrate includes third surface and the 4th surface, the third surface is oppositely arranged with the 4th surface, the third surface and the 4th surface are intersected with the first surface respectively, and the third surface is arranged compared to the 4th surface adjacent to the second end face, the step S150 includes:Step S151 is coated with the second photoresist layer away from the surface of the gate dielectric layer in the graphene layer；Step S152, pattern second photoresist layer, to retain first part, second part and Part III, the first part is set between the second part and the Part III, and the first gap is formed between the first part and the second part, the second gap is formed between the first part and the Part III, first gap and second gap are for appearing part graphene layer, and the first part is coplanar with the second end face in face of the end face of the second part, the first part is coplanar with the third end face in face of the end face of the Part III, end face and the third surface co-planar of the second part away from the first part, end face and fourth surface co-planar of the Part III away from the first part；Step S153 forms second metal layer, and the second metal layer covers the first part, the second part, the Part III, and covers the graphene layer manifested by first gap and second gap；Step S154, remove the first part, the second part and the Part III, it is the source electrode by second metal layer of first gap setting on the graphene layer, is the drain electrode by second metal layer of second gap setting on the graphene layer.
- The preparation method of field effect transistor as claimed in claim 10, which is characterized in that it is more than the insulating substrate for presetting light transmittance that the substrate, which is to the light transmittance of ultraviolet light, and second photoresist layer is ultraviolet light photosensitive photoresist layer, and the step S152 includes:Step S152a, light source and mask plate are provided, the light source and the mask plate are arranged adjacent to the second surface, and the mask plate is set between the light source and the second surface, the light source is for issuing ultraviolet light, the mask plate includes the second transmittance section of the first transmittance section and third transmittance section, the length that first transmittance section corresponds to grid setting and first transmittance section is greater than the length of the grid, second transmittance section and the third transmittance section are respectively arranged at the opposite both ends in first transmittance section, and second transmittance section is arranged compared to the third transmittance section adjacent to the third surface, end face and the third surface co-planar of second transmittance section away from the first transmittance section, end face and fourth surface co-planar of the third transmittance section away from first transmittance section, and described first Transmittance section is greater than or equal to the first light transmittance, second transmittance section and the third transmittance section to the light transmittance of the ultraviolet light and is less than or equal to the second light transmittance to the light transmittance of the ultraviolet light, and first light transmittance is greater than second light transmittance；Step S152b is exposed second photoresist layer using the ultraviolet light that the mask plate is issued as exposure mask using the light source, to form the first part, the second part and the Part III.
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