CN108470709A - The manufacturing method of insulation structure of shallow groove - Google Patents
The manufacturing method of insulation structure of shallow groove Download PDFInfo
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- CN108470709A CN108470709A CN201810271392.3A CN201810271392A CN108470709A CN 108470709 A CN108470709 A CN 108470709A CN 201810271392 A CN201810271392 A CN 201810271392A CN 108470709 A CN108470709 A CN 108470709A
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- groove
- shallow
- shallow trench
- layer
- trench isolation
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000009413 insulation Methods 0.000 title claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 66
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000227 grinding Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000011068 loading method Methods 0.000 description 17
- 230000006872 improvement Effects 0.000 description 15
- 238000011049 filling Methods 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 9
- 230000007547 defect Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of manufacturing methods of insulation structure of shallow groove, including step：Step 1: forming shallow trench isolation layer in semi-conductive substrate；Step 2: lithographic definition goes out the forming region of active area；Step 3: being performed etching to shallow trench isolation layer groove is formed in the forming region of active area；Step 4: deposition is formed the fully filled semiconductor material layer of groove；Step 5: carry out semiconductor material layer chemical mechanical grinding and the semiconductor material layer by being filled in after grinding in groove form active area.The present invention can improve the consistency of the thickness of shallow trench isolation layer, improve the flatness after trench fill, eliminate the saucer-like configuration that CMP process is formed.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of insulation structure of shallow groove
(STI) manufacturing method.
Background technology
Insulation structure of shallow groove (STI) is existing shallow trench isolation as shown in Figure 1A to Fig. 1 E for isolating active area
Device junction composition in each step of the manufacturing method of structure；The manufacturing method of existing insulation structure of shallow groove includes following step
Suddenly：
Step 1: as shown in Figure 1A, semi-conductive substrate such as silicon substrate 101 is provided, the surface of semiconductor substrate 101 according to
Secondary formation cushion oxide layer (Pad Oxide) 102 and pad nitride layer (Pad SiN) 103.It manufactures and leads in semiconductor integrated circuit
In domain, the disk that semiconductor substrate is usually made of the semi-conducting material of crystal structure forms, therefore also referred to as wafer (wafer).
Step 2: as shown in Figure 1B, lithographic definition goes out the forming region of shallow trench 104, later successively to pad nitride layer
103 and cushion oxide layer 102 perform etching the opening to form shallow trench 104, later with pad nitride layer 103 and cushion oxide layer
102 perform etching to form shallow trench 104 for mask to the semiconductor substrate 101 of bottom.Shallow trench 104 of same size or not
Together, the shallow trench 104 of two kinds of width is shown in Figure 1B, wherein wider shallow trench 104 is individually used for label 104a marks.Figure
Show that the width of shallow trench 104 is d1 in 1B, and the width of shallow trench 104a is d2, d2 is more than d1.
Due to of different size, the etching load (loading) in the etching technics of the shallow trench of different in width of shallow trench
Also different, the etch rate in the regions shallow trench 104a of wider width can be larger so that the depth of each shallow trench of formation differs
It causes, the corresponding depth of shallow trench 104a can bigger；The depth of shallow trench is inconsistent namely depth loading is bad.
Step 3: as shown in Figure 1 C, forming shallow trench isolation layer 105, shallow trench isolation layer 105 can be by each shallow trench 104
It is filled up completely, and the outside of each shallow trench 104 can be extended to.It is found that the top surface of shallow trench isolation layer 105 shown in Fig. 1 C
Flatness it is poor, there is larger height to rise and fall, as shown in virtual coil 201, the top surface of shallow trench isolation layer 105 it is flat
Smooth property is poor namely coating (overburden) loading is bad.
Step 4: as shown in figure iD, being carried out to shallow trench isolation layer 105 using chemical mechanical grinding (CMP) technique flat
Change, the shallow trench isolation layer 105 after planarization outside each shallow trench 104 is all removed, and the shallow trench inside each shallow trench 104 is exhausted
Edge layer 105 is ground to equal with the surface of shallow trench 104.In actual process, since overburdenloading is bad so that
The grinding effect of each position is not consistent, and the i.e. pattern loading of consistency that can influence the pattern after CMP is poor.The void of Fig. 1 D
It is found that the shallow trench isolation layer 105 in the region of larger shallow trench 104a can form a disk like defect shown in coil 202
(dishing defect)。
Step 5: as referring to figure 1E, removal pad nitride layer 103.
From the foregoing, it will be observed that in existing method, general shallow trench isolation layer 105 is mostly first to produce shallow trench using lithography
After 104, then carry out the insulating materials i.e. filling of shallow trench isolation layer 105.The depth of usual shallow trench 104 exists moreMore than,
This makes the shallow trench 104 corresponding depth loading performances of the i.e. different in width of size line width after etching bad；Further then
The overburden loading that surface after the filling of insulating materials 105 is formed are also bad, finally influence chemical mechanical grinding
Pattern loading.Common insulating materials is usually silica on the market, and the lapping liquid characteristic of the material be easy it is poor
Local pattern and be easy to cause poor disk like defect.Above-mentioned three kinds of loading are bad and disk like defect ask condition under,
The control of the step height (STIstep height wafer to wafer) of insulation structure of shallow groove between wafer can also be compared
It is poor, it is necessary to utilize Advanced process control (auto-process control, APC) operation in batches, this measure is time-consuming to cause board
Production efficiency is poor.
Invention content
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of insulation structure of shallow groove, can improve shallow ridges
The consistency of the thickness of layer slot insulator improves the flatness after trench fill, eliminates the saucer-like configuration that CMP process is formed.
In order to solve the above technical problems, the manufacturing method of insulation structure of shallow groove provided by the invention includes the following steps：
Step 1: forming shallow trench isolation layer in semi-conductive substrate.
Step 2: lithographic definition goes out the forming region of active area.
Step 3: performing etching and being formed in the forming region of the active area described shallow to the shallow trench isolation layer
Trench dielectric layer be removed after groove, the depth of the groove is less than the thickness of the shallow trench isolation layer.
Step 4: deposition forms semiconductor material layer, the groove is filled up completely and is extended by the semiconductor material layer
The surface of the shallow trench isolation layer outside to the groove.
Step 5: carry out chemical mechanical grinding by outside the groove semiconductor material layer removal and by the ditch
The semiconductor material layer in slot region is ground to equal with the surface of shallow trench isolation layer, is ground by the chemical machinery
The semiconductor material layer composition active area being filled in after mill in the groove, the side of the active area is by the shallow trench
Insulator separation.
A further improvement is that semiconductor substrate described in step 1 is silicon substrate.
A further improvement is that further including in the semiconductor substrate before forming the shallow trench isolation layer in step 1
Surface forms the step of cushion oxide layer, and the shallow trench isolation layer is formed in the liner oxidation layer surface.
A further improvement is that the thickness of the shallow trench isolation layer isMore than.
A further improvement is that the material of the shallow trench isolation layer is silicon dioxide layer.
A further improvement is that the shallow trench isolation layer uses chemical vapor deposition (CVD) process deposits.
A further improvement is that the shallow trench isolation layer uses high density plasma CVD (HDPCVD)
Technique or plasma enhanced chemical vapor deposition (PECVD) process deposits.
A further improvement is that the quantity of the active area defined in step 2 is more than one.
A further improvement is that each active area is of same size or different.
A further improvement is that the depth of the corresponding groove of each active area is controlled using APC.
A further improvement is that semiconductor material layer described in step 4 is polysilicon layer.
A further improvement is that being used to form MOS transistor in the active area.
A further improvement is that the MOS transistor has planar gate structure, covered by the planar gate described active
It is formed with channel region in area and lateral channel is used to form by the surface for the channel region that the planar gate covers.
A further improvement is that the planar gate includes the gate dielectric layer being sequentially overlapped and gate electrode material.
A further improvement is that the gate dielectric layer includes gate oxide；The material of the gate electrode material includes
Polysilicon and metal.
It is not that use is direct in the prior art that the present invention, which forms insulation structure of shallow groove and is isolated in the method for active area,
The method that first etching shallow trench refills shallow trench isolation layer on a semiconductor substrate；But it uses first in semiconductor substrate surface
Shallow trench isolation layer is formed, etching forms groove and in the trench filling semiconductor material in shallow trench isolation layer again later
Layer, forms active area by the semiconductor material layer being filled in groove namely the present invention is initially formed using shallow trench isolation layer
The technique of (STI first)；Compare the also prior art of the invention it is found that the shallow trench isolation layer of the present invention does not need ditch to be filled
Slot, therefore the consistency of the thickness of shallow trench isolation layer is preferable.
The groove of the present invention is for filling semiconductor material layer and to form the groove of active area, and the depth of active area is usual
It is used to be isolated the depth of the shallow trench isolation layer of active area less than side, therefore in the prior art for filling shallow trench isolation
The shallow trench of layer is compared, and the depth of groove of the invention is lower, and the reduction of the depth of groove is to each in same semi-conductive substrate
The raising of the depth uniformity of groove is beneficial, so the depth loading for the groove that the present invention eventually forms is preferable.
In addition, the reduction that the depth-to-width ratio of shallower groove also obtains, therefore the filling for being conducive to groove uses semiconductor material
The technique of bed of material filling groove is more prone to, and the flatness for finally depositing the top surface of the semiconductor material layer of formation is also preferable
I.e. overburden loading are better than the prior art.
Preferable overburden loading can also improve the consistency i.e. pattern of the pattern after subsequent CMP
Loading is preferable；In addition, the CMP of the present invention is grinding to semi-conducting material such as to the grinding of polysilicon, semi-conducting material
Lapping liquid is different with the lapping liquid of shallow trench isolation layer, finally so that the grinding rate of semi-conducting material of the present invention is slower, more has
Conducive to the process of lapping of CMP control and preferable local pattern can be reached, finally can also form less disk like defect, finally
The control of STI step height wafer to wafer can be made preferable, the number of batch job can be reduced, reduce manufacture
Cost.
In addition, the present invention does not need pad nitride layer, therefore deposition pad nitride layer can be reduced and remove pad nitride layer
Step can further reduce manufacturing cost.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Figure 1A-Fig. 1 E are the device junction compositions in each step of the manufacturing method of existing insulation structure of shallow groove；
Fig. 2 is the flow chart of the manufacturing method of insulation structure of shallow groove of the embodiment of the present invention；
Fig. 3 A- Fig. 3 D are the device junction compositions in each step of present invention method.
Specific implementation mode
As shown in Fig. 2, being the flow chart of the manufacturing method of insulation structure of shallow groove of the embodiment of the present invention；Such as Fig. 3 A to Fig. 3 D
It is shown, it is the device junction composition in each step of present invention method, the manufacture of insulation structure of shallow groove of the embodiment of the present invention
Method includes the following steps：
Step 1: as shown in Figure 3A, forming shallow trench isolation layer 3 in semi-conductive substrate 1.
Further include on 1 surface of the semiconductor substrate before forming the shallow trench isolation layer 3 in the embodiment of the present invention
The step of forming cushion oxide layer 2, the shallow trench isolation layer 3 is formed in 2 surface of the cushion oxide layer.
Preferably, the semiconductor substrate 1 is silicon substrate.The thickness of the shallow trench isolation layer 3 isMore than.Institute
The material for stating shallow trench isolation layer 3 is silicon dioxide layer.The shallow trench isolation layer 3 is using CVD process deposits as used
HDPCVD techniques or pecvd process deposition.
Step 2: as shown in Figure 3B, lithographic definition goes out the forming region of active area.
In the embodiment of the present invention, the quantity of the active area of definition is more than one.
Each active area it is of same size or different.The active area of two kinds of width is shown in Fig. 3 B, it is subsequently wider
The corresponding groove of active area is individually indicated with label 4a.
Step 3: as shown in Figure 3B, being performed etching to the shallow trench isolation layer 3 and in the forming region of the active area
Middle to form the groove 4 after the shallow trench isolation layer 3 is removed, the depth of the groove 4 is less than the shallow trench isolation layer 3
Thickness.
Since the width of each active area has multiple, therefore corresponding groove 4 also just has multiple width, width in Fig. 3 B
Wider groove is individually indicated with label 4a.The load of the etching technics of the groove of different in width is different, the depth finally etched
There is certain difference, the depth of the corresponding groove of each active area 4 is controlled using APC.Due to the embodiment of the present invention
The depth of the groove 4 is less than the depth of each shallow trench 104 shown in the corresponding Figure 1B of the prior art, therefore the embodiment of the present invention
The etching technics of groove of the groove 4 can be simpler, groove 4 it is deep-controlled more preferably, depth loading is more preferably.
Step 4: as shown in Figure 3 C, deposition forms semiconductor material layer 5, the semiconductor material layer 5 is by the groove 4
It is filled up completely and extends to the surface of the shallow trench isolation layer 3 outside the groove 4.It is described partly to lead in the embodiment of the present invention
Body material layer 5 is polysilicon layer.
Step 5: as shown in Figure 3D, carrying out chemical mechanical grinding and removing the semiconductor material layer 5 outside the groove 4
It removes and the semiconductor material layer 5 in 4 region of the groove is ground to the surface phase with the shallow trench isolation layer 3
It is flat, active area is formed by the semiconductor material layer 5 being filled in after the chemical mechanical grinding in the groove 4, it is described to have
The side of source region is isolated by the shallow trench isolation layer 3.
It is used to form MOS transistor in the active area.The MOS transistor has planar gate structure, by the plane
It is formed with channel region in the active area of grid covering and is used to form by the surface for the channel region that the planar gate covers
Lateral channel.The planar gate includes the gate dielectric layer being sequentially overlapped and gate electrode material.The gate dielectric layer includes grid
Oxide layer；The material of the gate electrode material includes polysilicon and metal.
It is not to use the prior art that the embodiment of the present invention, which forms insulation structure of shallow groove and is isolated in the method for active area,
In the direct first etching shallow trench method that refills shallow trench isolation layer 3 on semiconductor substrate 1；But it uses first in semiconductor
1 surface of substrate forms shallow trench isolation layer 3, and etching forms groove 4 and filled out in groove 4 in shallow trench isolation layer 3 again later
Semiconductor material layer 5 is filled, active area is formed by the semiconductor material layer 5 being filled in groove 4 namely the embodiment of the present invention uses
The technique that shallow trench isolation layer 3 is initially formed (STI first)；Compare the also prior art of the embodiment of the present invention it is found that the present invention is real
The shallow trench isolation layer 3 for applying example does not need groove 4 to be filled, therefore the consistency of the thickness of shallow trench isolation layer 3 is preferable.
The groove 4 of the embodiment of the present invention is for filling semiconductor material layer 5 and to form the groove 4 of active area, active area
Depth be usually less than the depth of shallow trench isolation layer 3 of the side for active area to be isolated, therefore in the prior art for filling out
The shallow trench for filling shallow trench isolation layer 3 is compared, and the depth of the groove 4 of the embodiment of the present invention is lower, the reduction pair of the depth of groove 4
Raising with the depth uniformity of each groove 4 in semi-conductive substrate 1 is beneficial, so what the embodiment of the present invention eventually formed
The depth loading of groove 4 is preferable.
In addition, the reduction that the depth-to-width ratio of shallower groove 4 also obtains, therefore the filling for being conducive to groove 4 uses semiconductor
The technique that material layer 5 fills groove 4 is more prone to, and finally deposits the flatness of the top surface of the semiconductor material layer 5 of formation
Also preferably i.e. overburden loading are better than the prior art.
Preferable overburden loading can also improve the consistency i.e. pattern of the pattern after subsequent CMP
Loading is preferable；In addition, the CMP of the embodiment of the present invention is grinding such as to the grinding of polysilicon, semiconductor to semi-conducting material
The lapping liquid of material is different with the lapping liquid of shallow trench isolation layer 3, finally so that the grinding of semi-conducting material of the embodiment of the present invention
Rate is slower, is more advantageous to the control of the process of lapping of CMP and can reach preferable local pattern, finally can also be formed less
Disk like defect can finally make the control of STI step height wafer to wafer preferable, can reduce batch job
Number reduces manufacturing cost.
In addition, the embodiment of the present invention does not need pad nitride layer, therefore deposition pad nitride layer and removal liner nitrogen can be reduced
The step of changing layer, can further reduce manufacturing cost.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of insulation structure of shallow groove, which is characterized in that include the following steps：
Step 1: forming shallow trench isolation layer in semi-conductive substrate；
Step 2: lithographic definition goes out the forming region of active area；
Step 3: being performed etching to the shallow trench isolation layer and forming the shallow trench in the forming region of the active area
Insulating layer be removed after groove, the depth of the groove is less than the thickness of the shallow trench isolation layer；
Step 4: deposition forms semiconductor material layer, the groove is filled up completely and extends to institute by the semiconductor material layer
State the surface of the shallow trench isolation layer outside groove；
Step 5: carry out chemical mechanical grinding by outside the groove semiconductor material layer removal and by the trench area
The semiconductor material layer in domain be ground to it is equal with the surface of shallow trench isolation layer, after the chemical mechanical grinding
The semiconductor material layer composition active area being filled in the groove, the side of the active area is by the shallow trench isolation
Layer isolation.
2. the manufacturing method of insulation structure of shallow groove as described in claim 1, it is characterised in that：Semiconductor described in step 1
Substrate is silicon substrate.
3. the manufacturing method of insulation structure of shallow groove as claimed in claim 2, it is characterised in that：It is formed in step 1 described shallow
Further include the steps that forming cushion oxide layer, the shallow trench isolation layer in the semiconductor substrate surface before trench dielectric layer
It is formed in the liner oxidation layer surface.
4. the manufacturing method of insulation structure of shallow groove as described in claim 1, it is characterised in that：The shallow trench isolation layer
Thickness isMore than.
5. the manufacturing method of insulation structure of shallow groove as described in claim 1, it is characterised in that：The shallow trench isolation layer
Material is silicon dioxide layer.
6. the manufacturing method of insulation structure of shallow groove as claimed in claim 5, it is characterised in that：The shallow trench isolation layer is adopted
With CVD process deposits.
7. the manufacturing method of insulation structure of shallow groove as claimed in claim 6, it is characterised in that：The shallow trench isolation layer is adopted
It is deposited with HDPCVD techniques or pecvd process.
8. the manufacturing method of insulation structure of shallow groove as described in claim 1, it is characterised in that：It is described defined in step 2
The quantity of active area is more than one.
9. the manufacturing method of insulation structure of shallow groove as claimed in claim 8, it is characterised in that：The width of each active area
It is identical or different.
10. the manufacturing method of insulation structure of shallow groove as claimed in claim 9, it is characterised in that：Each active area corresponds to
The groove depth using APC control.
11. the manufacturing method of insulation structure of shallow groove as claimed in claim 1 or 2, it is characterised in that：Half described in step 4
Conductor material layer is polysilicon layer.
12. the manufacturing method of insulation structure of shallow groove as claimed in claim 11, it is characterised in that：It is used in the active area
Form MOS transistor.
13. the manufacturing method of insulation structure of shallow groove as claimed in claim 12, it is characterised in that：The MOS transistor tool
There is planar gate structure, the institute for being formed with channel region in the active area that the planar gate covers and being covered by the planar gate
The surface for stating channel region is used to form lateral channel.
14. the manufacturing method of insulation structure of shallow groove as claimed in claim 13, it is characterised in that：The planar gate include according to
The gate dielectric layer and gate electrode material of secondary superposition.
15. the manufacturing method of insulation structure of shallow groove as claimed in claim 14, it is characterised in that：The gate dielectric layer includes
Gate oxide；The material of the gate electrode material includes polysilicon and metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810271392.3A CN108470709A (en) | 2018-03-29 | 2018-03-29 | The manufacturing method of insulation structure of shallow groove |
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| CN201810271392.3A CN108470709A (en) | 2018-03-29 | 2018-03-29 | The manufacturing method of insulation structure of shallow groove |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111584616A (en) * | 2020-05-20 | 2020-08-25 | 合肥晶合集成电路有限公司 | Semiconductor structure and method of forming the same |
| CN112909079A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
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| US20050014294A1 (en) * | 2001-01-08 | 2005-01-20 | Chartered Semiconductor Manufacturing Ltd. | Novel method of body contact for SOI MOSFET |
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