CN108462492B - A SAR_ADC system offset voltage correction circuit and correction method - Google Patents
A SAR_ADC system offset voltage correction circuit and correction method Download PDFInfo
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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Abstract
本发明公开一种SAR_ADC系统失调电压的校正电路及校正方法，该校正电路包括PGA模块、输入控制模块、编码校正控制模块和差分比较器模块；其中，输入控制模块，与所述PGA模块相连接，用于控制校正信号源输入端的信号输出至所述PGA模块；差分比较器模块，用于通过调整第一可调电容和第二可调电容的大小以校正SAR_ADC系统的失调电压，并更新输出端得到的比较判断结果；编码校正控制模块，用于根据所述差分比较器模块输出的比较判断结果，通过调整所述第一可调电容和所述第二可调电容的电容量对应的互补编码信号，直到所述差分比较器模块的输出端在高低电平之间连续翻转两次才停止校正过程。整体电路结构实现简单，校正精度高。
The present invention discloses a correction circuit and correction method for offset voltage of a SAR_ADC system, wherein the correction circuit comprises a PGA module, an input control module, a coding correction control module and a differential comparator module; wherein the input control module is connected to the PGA module and is used to control the signal output of the correction signal source input end to the PGA module; the differential comparator module is used to adjust the size of the first adjustable capacitor and the second adjustable capacitor to correct the offset voltage of the SAR_ADC system, and update the comparison judgment result obtained at the output end; the coding correction control module is used to adjust the complementary coding signal corresponding to the capacitance of the first adjustable capacitor and the second adjustable capacitor according to the comparison judgment result output by the differential comparator module, until the output end of the differential comparator module continuously flips twice between high and low levels before stopping the correction process. The overall circuit structure is simple to implement and has high correction accuracy.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a circuit and a method for correcting offset voltage of an SAR_ADC system.
Background
Successive approximation analog-to-digital converters (successive approximation register analog to digital converters, sar_adc for short) are common analog-to-digital conversion structures for medium to high resolution applications. Conventional sar_adc system as shown in fig. 1, the sar_adc includes a comparator, a DAC module, a hold circuit, and a logic control circuit. The DAC module comprises a capacitor array or a capacitor resistor hybrid array, and the function of the DAC module is to generate corresponding analog voltage to the comparator under the condition of inputting a specific digital code value; the comparator is a differential comparator with the resolution of N+1bit; the logic control circuit generates corresponding N-bit digital code values D0[ N-1:0] to the DAC module according to the comparator; the holding circuit samples the analog input signal to obtain a voltage Vin, which is provided to the comparator.
The basic principle of sar_adc for converting an analog signal into a digitally encoded signal is: and comparing the voltage Vin with the analog voltage V_adc, wherein the analog voltage V_adc is determined according to the digital input signals of the DAC module, and the comparator decides to increase or decrease the digital signals input into the DAC module according to the magnitude of the analog voltage V_adc so as to make the analog voltage V_adc approach to the analog input signals Vin, when the analog voltage V_adc is equal to the value of the analog input signals Vin, the digital signals corresponding to the analog input signals Vin can be obtained, and the logic control module outputs the N-bit digital conversion code value Dout0[ N-1:0] of the SAR_ADC. However, due to the imbalance of the comparator, the imbalance of the ground inside the SAR_ADC chip and the ground of the PCB level, the mismatch of the capacitor, the irrational factor of the MOS transistor switch and the like, the SAR_ADC is imbalance, so that the signal to be measured in a certain range cannot be effectively measured by the ADC, and a corresponding error exists in the digital signal output by the SAR_ADC.
Disclosure of Invention
In order to correct offset voltage of a successive approximation type analog-to-digital converter SAR_ADC system, the invention reforms a traditional SAR_ADC system, and provides a circuit and a method for correcting offset voltage of the SAR_ADC system, which have the following technical scheme:
The utility model provides a correction circuit of SAR_ADC system offset voltage, includes the PGA module, still includes: the device comprises an input control module, a coding correction control module and a differential comparator module;
The input control module is connected with the PGA module and used for controlling the signal output of the input end of the correction signal source to the PGA module when the correction enabling end is a high-level signal, and providing a signal source to be corrected for the differential comparator module;
the differential comparator module comprises a first adjustable capacitor and a second adjustable capacitor, and is used for correcting the offset voltage of the SAR_ADC system by adjusting the sizes of the first adjustable capacitor and the second adjustable capacitor and updating the comparison judgment result obtained by the output end;
the code correction control module is used for obtaining complementary code signals corresponding to the capacitance of the first adjustable capacitor and the second adjustable capacitor through coding according to the comparison judgment result output by the differential comparator module, and stopping the correction process of the offset voltage of the SAR_ADC system until the output end of the differential comparator module continuously turns twice between high and low levels;
wherein the complementary encoded signal is a pair of P-bit binary sets with invariable sum values, P being an integer greater than 1; and the first adjustable capacitor and the second adjustable capacitor are respectively a group of capacitor arrays, and each group of capacitor arrays is used for changing the capacitance of the internal node according to the complementary coding signal so as to correct the offset voltage of the SAR_ADC system.
Further, the correction signal source input may be a single ended input or a differential input.
Further, the correction circuit further comprises a DAC module, wherein a sampling hold circuit is embedded in the DAC module, the input end of the DAC module is connected with the output end of the PGA module, and the DAC module is used for sampling and holding an amplified signal source to be corrected output by the PGA module; the digital coding signal input end of the DAC module is connected with the coding correction control module and is used for converting the digital coding signal output by the coding correction control module into corresponding analog voltage and providing the corresponding analog voltage to the differential comparator module; the output end of the DAC module is connected with the differential input end of the differential comparator module and is used for providing an analog input signal for the differential comparator module to carry out comparison and judgment;
Wherein, the DAC module can be a capacitor array or a resistor-capacitor hybrid array.
Further, the differential comparator module further comprises a pre-amplifier sub-module, a latch comparator sub-module, a reset sub-module and an output latch sub-module;
a preamplifier sub-module for amplifying the output signal of the DAC module to an amplitude that can be effectively identified by the latch comparator sub-module;
The reset submodule is provided with two common connection nodes with the preamplifier submodule and the latch comparator submodule, and is used for controlling the signal reset and discharge processes of the two common connection nodes and outputting a control result to the latch comparator submodule; wherein the two common connection nodes are divided into a first node and a second node;
the latch comparator submodule comprises two inverters which are connected end to end, and the comparison and judgment process is quickened in a positive feedback connection mode;
The output latch submodule is used for updating the comparison judgment result of the differential comparator module according to the output signal of the latch comparator submodule;
one end of the first adjustable capacitor is connected with the first node, one end of the second adjustable capacitor is connected with the second node, and the other ends of the first adjustable capacitor and the second adjustable capacitor are grounded.
A correction method based on the correction circuit, comprising:
When the correction enabling end of the input control module is a high-level signal, a correction signal source enters the input control module from the correction signal source input end of the input control module, and then a maladjustment correction process is started to provide correction signal analog voltage for the DAC module; meanwhile, a digital coding signal output by a built-in register of the coding correction control module is converted into an analog reference voltage through the DAC module, and a reference signal is provided for the differential comparator module;
When the difference value between the correction signal analog voltage and the reference voltage is zero, the coding correction control module adjusts the capacitance of the first adjustable capacitor and the capacitance of the second adjustable capacitor according to the comparison and judgment result of the differential comparator module, offset voltage existing in the whole SAR system is counteracted by introducing correction voltage, and the correction process of the correction circuit is stopped until the output end of the differential comparator module continuously turns twice between high and low levels.
Further, under the condition that no offset voltage exists, the encoding correction control module sets the complementary encoding signal at an intermediate scale value, namely the highest position of the first control correction signal and the second control correction signal corresponding to the complementary encoding signal is high, and the rest positions are zero, and at the moment, the differential comparator module enables the capacitance of the first adjustable capacitor to be equal to the capacitance of the second adjustable capacitor under the level control action of the first control correction signal and the second control correction signal.
Further, the method further comprises the following steps: when negative offset voltage exists, the comparison judgment result of the differential comparator module is low level, the first control correction signal is subtracted by one on the basis of the intermediate scale value, the second control correction signal is added by one on the basis of the intermediate scale value, the first control correction signal correspondingly controls the first adjustable capacitance to be reduced, and the second control correction signal correspondingly controls the second adjustable capacitance to be increased, so that the voltage dropping speed of the first node is faster than the voltage dropping speed of the second node, which is equivalent to introducing a positive differential voltage to offset the originally existing negative offset voltage;
However, if the comparison and judgment result of the differential comparator module is still at the low level after the operational amplifier feedback action of the latch comparator sub-module, the first control correction signal continues to decrease by one, the second control correction signal continues to increase by one, the corresponding first adjustable capacitance continues to decrease, and the second adjustable capacitance continues to increase, so that the capacitance of the first node is smaller than the capacitance of the second node, which is equivalent to introducing a positive differential voltage with larger value to offset the original negative offset voltage;
The coding correction control module adjusts the first control correction signal and the second control correction signal according to the comparison judgment result of the differential comparator module, so that when the comparison judgment result of the differential comparator module continuously turns from high level to low level twice, the correction process is controlled to stop again.
Further, the method further comprises the following steps: when positive offset voltage exists, the comparison judgment result of the differential comparator module is high level, the first control correction signal is increased by one on the basis of the intermediate scale value, the second control correction signal is decreased by one on the basis of the intermediate scale value, the first control correction signal correspondingly controls the first adjustable capacitance to be increased, and the second control correction signal correspondingly controls the second adjustable capacitance to be decreased, so that the voltage dropping speed of the first node is slower than the voltage dropping speed of the second node, which is equivalent to introducing a negative differential voltage to offset the original positive offset voltage;
However, if the comparison and judgment result of the latch comparator sub-module is still at the high level under the feedback action of the operational amplifier, the first control correction signal continues to be increased by one, the second control correction signal continues to be decreased by one, the corresponding first adjustable capacitance continues to be increased, and the second adjustable capacitance continues to be decreased, so that the voltage dropping speed of the first node is further slower than the voltage dropping speed of the second node;
The code correction control module adjusts the first control correction signal and the second control correction signal according to the comparison judgment result of the differential comparator module, so that when the comparison judgment result of the differential comparator module continuously turns from high level to low level twice, the correction process is controlled to stop.
Compared with the prior art, the offset voltage correcting circuit and the offset voltage correcting method for the SAR_ADC system are applicable to various SAR_ADC architecture circuits, and have wide application range, wherein the DAC module comprises a single-ended input structure, a differential input structure and a resistance-capacitance hybrid array;
When the correction signal source is zero, namely the input signal of the correction circuit is zero, the coding correction control module adjusts the sizes of the first adjustable capacitor and the second adjustable capacitor through the coding signal according to the comparison judgment result output by the differential comparator module, so that the capacitance difference of the first adjustable capacitor and the second adjustable capacitor introduces equivalent correction voltage to offset the offset of the SAR_ADC circuit, and the whole correction circuit adopts digital form correction, and has the advantages of high correction precision, low circuit power consumption, simple structure, easy expansion and strong practicability.
Drawings
Fig. 1 is a schematic circuit block diagram of a conventional SAR ADC system;
Fig. 2 is a schematic diagram of a circuit module for correcting offset voltage of a sar_adc system according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a circuit for correcting offset voltage of an SAR_ADC system with a single-ended input structure according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a circuit for correcting offset voltage of a sar_adc system with a dual-end input structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a sub-module within a differential comparator module according to an embodiment of the present invention;
Fig. 6 is a circuit schematic diagram of a differential comparator module according to an embodiment of the invention.
Detailed Description
The following is a further description of embodiments of the invention, taken in conjunction with the accompanying drawings:
As shown in fig. 2, the embodiment of the invention provides a correction circuit for offset voltage of sar_adc system, which comprises a PGA module, an input control module, a code correction control module and a differential comparator module; the input control module is connected with the PGA module and used for controlling the signal source to be corrected to be output to the PGA module when the correction enabling end is a high-level signal so as to provide the signal source to be corrected for the differential comparator module; the differential comparator module comprises a first adjustable capacitor and a second adjustable capacitor, and is used for counteracting offset voltage Voff of the SAR_ADC system by adjusting capacitance of the first adjustable capacitor and capacitance of the second adjustable capacitor; updating the comparison judgment result v_cmp obtained by the output end to enable the high and low level of the output end to be overturned; the coding correction control module is used for obtaining complementary coding signals Dp_cal [ p-1:0] and Dn_cal [ p-1:0] which are corresponding to the capacitance of the first adjustable capacitor and the second adjustable capacitor and are regulated through successive approximation logic coding according to the comparison judgment result v_cmp output by the differential comparator module, and stopping the correction process of the correction circuit until the output end of the differential comparator module continuously turns over twice between high and low levels; wherein if Dp_cal [ P-1:0] increases by a predetermined value, dn_cal [ P-1:0] decreases by an equal predetermined value, and vice versa, the complementary encoded signal is a pair of P-bit binary sets of which the sum value is unchanged, and P is an integer greater than 1. The first adjustable capacitor and the second adjustable capacitor are respectively a group of capacitor arrays, each group of capacitor arrays changes the closing of the internal capacitor series switch according to the complementary coding signal, and further changes the capacitance value of the corresponding node, and the inherent offset voltage of the additional bias voltage compensation system is intentionally introduced. As shown in fig. 3 and 5, the two capacitor arrays are simplified into the first capacitor C1 and the second capacitor C2, so that the simplified circuit schematic is illustrated in cooperation with complementary encoded signals dp_cal [ p-1:0] and dn_cal [ p-1:0 ].
As an embodiment of the single-ended input structure of the correction circuit, as shown in fig. 3, the selector MUX is equivalent to the input control module in fig. 2, and is connected with m GPIO ports as signal input ends, corresponding to the ports P0, P1, P2 and … Pm respectively, and meanwhile, the selector MUX inputs one path as a correction signal source for correction through the correction signal source input end, and correspondingly, a correction enable end for receiving a correction enable signal. When the system is in the SAR_ADC system imbalance correction mode, the correction enabling signal is firstly set high, the correction signal source is controlled to enter the PGA module through the selector MUX, and then sampling conversion work is carried out. The main difference from the prior art is that the N-bit digital conversion code value Dout [ N-1:0] outputted by the code correction control module is forcedly set to 0 in the sar_adc system offset correction mode, and the code correction control module updates a pair of P-bit complementary code signals dn_cal [ P-1:0] and dp_cal [ P-1:0] according to the comparison and judgment result of the differential comparator module, so as to adjust the adjustable capacitance in the differential comparator module as the correction control code value to complete the correction of offset voltage. When the comparison judgment result v_cmp output by the differential comparator module circularly appears twice between 0 and 1, which means that the correction of the offset voltage of the whole SAR_ADC system is finished, and the system offset voltage correction mode can be exited. The offset correction of the whole SAR_ADC system aims to ensure that the digital code value Dout [ N-1:0] after sampling and conversion by the correction circuit is an all-zero binary value corresponding to zero level when the signal of the input end of the correction signal source end is 0.
As an example of the differential input structure of the correction circuit, as shown in fig. 4, the selector MUX is equivalent to the input control module in fig. 2, and 2m GPIO ports are connected to the selector MUX as differential input terminals of signals, and each group of differential input terminals corresponds to vp0 and vn0, vp1 and vn1, vp2 and vn2, …, vpm and vnm ports, respectively, while the correction signal source inputs the differential form signals vcal _p and vcal _n to the selector MUX, wherein the differential form signals vcal _p and vcal _n are both connected to one same analog voltage, that is, the common mode level vcom of the PGA module; correspondingly, the correction enabling terminal is also used for receiving the correction enabling signal. When the system is in the offset correction mode of the SAR_ADC system, firstly, a correction enabling signal is set high, control differential form signals vcal _p and vcal _n respectively enter a positive input end vp and a negative input end vn of the PGA module through a selector MUX, then differential signals obtained through driving amplification are output to differential input ends vop and von of the DAC module for sampling conversion, then the N-bit digital conversion code value Dout [ N-1:0] output by the coding correction control module is combined, and the DAC module generates a pair of differential signals vp_sig and vn_sig which are respectively input to positive and negative input ends of the differential comparator module. The main difference from the prior art is that the N-bit digital conversion code value Dout [ N-1:0] is forcedly set to 011 … 1 in the sar_adc system offset correction mode. The target of the offset correction of the whole SAR_ADC system is to ensure that when the differential input voltage difference of a correction signal source is 0, the highest bit of the corresponding N-bit digital code value Dout [ N-1:0] after sampling and conversion of the correction circuit is 0, and the rest bits are 1.
As shown in fig. 2, the correction circuit further includes a DAC module, in which a sample-and-hold circuit is embedded, and an input terminal of the DAC module is connected to the PGA module, and is used for sampling and holding the amplified correction signal source output by the PGA module, and in a sampling stage of the DAC module, each capacitor or resistance-capacitance switch of n parallel capacitors or n parallel resistor capacitors in the DAC module corresponds to an analog signal to be converted at each free terminal of the DAC module; the free end of the DAC module is connected with the code correction control module and is used for outputting a reference digital signal D [ N-1 ] according to the code correction control module: 0] to an analog reference voltage provided to a differential comparator module; the output end of the DAC module is connected with the differential input end of the differential comparator module and is used for providing an analog input signal for the differential comparator module to perform offset correction.
As shown in connection with fig. 5 and 6, the differential comparator module further includes a pre-amplifier sub-module, a reset sub-module, a latch comparator sub-module, and an output latch sub-module.
And the pre-amplifier sub-module is used for amplifying the output signal of the DAC module to the amplitude which can be effectively identified by the latch comparator sub-module, amplifying the signal of the positive input end vip by the pre-amplifier sub-module to obtain a signal vp1, outputting the signal vp1 to the grid electrode of the second NMOS tube, and amplifying the signal of the negative input end vin to obtain a signal vn1 and outputting the signal vn1 to the grid electrode of the first NMOS tube.
The reset sub-module is connected with the pre-amplifier sub-module and the latch comparator sub-module by a common connection node, and is respectively a first node vn2 and a second node vp2, wherein the grid electrode of the first NMOS tube NM1, the grid electrode of the first PMOS tube PM1 and the grid electrode of the second PMOS tube PM2 are connected, the reset signal V_latch is changed from a low level to a high level, so that the capacitance of the first node vn2 node and the capacitance of the second node vp2 node start to release charges, and the voltage of the first node vn2 node and the voltage of the second node vp2 node start to drop, thereby providing differential voltage signals for the latch comparator sub-module.
The latch comparator submodule comprises two operational amplifier models which are connected end to end, wherein the operational amplifier models are formed by connecting two inverters end to enhance feedback effect; specifically, the two inverters are a first inverter formed by connecting a third PMOS tube PM3 and an eighth NMOS tube NM8, and a second inverter formed by connecting a fourth PMOS tube PM4 and a ninth NMOS tube NM9, wherein the gates of the third PMOS tube PM3 and the eighth NMOS tube NM8 and the drains of the fourth PMOS tube PM4 and the ninth NMOS tube NM9 are connected to a fourth node P3, and the drains of the third PMOS tube PM3 and the eighth NMOS tube NM8 and the gates of the fourth PMOS tube PM4 and the ninth NMOS tube NM9 are connected to a third node N3; the sixth PMOS tube PM6 and the fifth NMOS tube NM5 form an operational amplifier load; the seventh NMOS transistor NM7 and the sixth NMOS transistor NM6 serve as a ground switch of the first inverter; the fifth NMOS transistor NM5 and the fourth NMOS transistor NM4 serve as a ground switch of the second inverter.
The output latch sub-module is used for outputting a comparison judgment signal according to the differential voltage generated by the feedback adjustment of the operational amplifier model in the latch comparator sub-module, and the comparison judgment signal is used as the comparison judgment result of the differential comparator module; specifically, the voltage signal vp3 of the fourth node P3 is input to the output latch submodule through a buffer, the voltage signal vn3 of the third node N3 is input to the output latch submodule through the buffer, and the output latch submodule is a combinational logic structure of a latch, so that when the voltage signal vp3 and the voltage signal vn3 are in different logic levels, the output signal v_cmp of the output latch submodule is turned over in high and low levels.
One end of the second adjustable capacitor C2 is connected to the second node vp2, one end of the first adjustable capacitor C1 is connected to the first node vn2, and the other ends of the first adjustable capacitor C1 and the second adjustable capacitor C2 are both grounded. The complementary coding signals Dn_cal [ P-1:0] and Dp_cal [ P-1:0] output by the coding correction module change the capacitance of the first adjustable capacitor C1 and the second adjustable capacitor C2 by adjusting the switches connected in series on the capacitor arrays corresponding to the respective connection, the P-bit complementary coding signals correspond to the P parallel capacitors respectively, the value of the P-bit complementary coding signals determines the closing condition of the switches connected in series with the P parallel capacitors, and then the P-capacitor parallel value is changed.
Based on the above correction circuit, an embodiment of the present invention provides a method for correcting offset voltage, including:
When the correction enabling end of the input control module is a high-level signal, a correction signal source enters the input control module from the correction signal source input end of the input control module, and then the correction signal source is controlled to be output to the PGA module from the output end of the input control module; and the PGA module amplifies the correction signal source, and the DAC module performs sampling and holding to provide correction signal analog voltage for the differential comparator module. Meanwhile, a digital code signal output by a built-in register of the code correction control module is converted into an analog reference voltage through the DAC module, and a reference signal is provided for the differential comparator module.
When the difference value between the correction signal analog voltage and the reference voltage is zero, the coding correction control module adjusts the capacitance of the first adjustable capacitor and the capacitance of the second adjustable capacitor according to the high-low level state of the comparison judgment output of the differential comparator module, offset voltage existing by introducing correction voltage is offset, and the correction process of the correction circuit is stopped until the output of the differential comparator module continuously turns over twice between the high level and the low level.
In an embodiment of the present invention, the complementary encoded signal is set to a 4-bit binary number. Under the condition that no offset voltage exists, the coding correction control module firstly sets the complementary coding signal at an intermediate scale value 4'b1000, namely a first control correction signal Dp_cal [3:0] and a second control correction signal Dn_cal [3:0] corresponding to the complementary coding signal are both expressed as 4' b1000, and at the moment, the differential comparator module makes the capacitance of the first adjustable capacitor C1 and the capacitance of the second adjustable capacitor C2 equal under the level control action of the first control correction signal Dp_cal [3:0] and the second control correction signal Dn_cal [3:0 ]; meanwhile, the reference digital signal output by the built-in register of the coding control module is converted into analog reference voltage through the DAC module, and the reference signal is provided for the differential comparator module.
In the embodiment of the present invention, the working principle of the correction circuit is specifically described that if there is a negative offset voltage δ <0, the first control correction signal dp_cal [3:0] is subtracted by one to obtain 4'b0111 based on the intermediate scale value 4' b1000, the second control correction signal dn_cal [3:0] is added by one to obtain 4'b1000 based on the intermediate scale value 4' b1000, the first adjustable capacitor C1 corresponding to the first control correction signal dp_cal [3:0] is reduced, and the second adjustable capacitor C2 corresponding to the second control correction signal dn_cal [3:0] is increased. At this time, when the voltage difference between the positive input terminal vip and the negative input terminal vin of the pre-amplifier sub-module is 0, since the capacitance of the first node vn2 is smaller than that of the second node vp2, the reset signal v_latch on the gates of the first PMOS tube PM1 and the second PMOS tube PM2 jumps to a high level, and the first NMOS tube NM1 is turned on, so that the voltage at the first node vn2 drops faster than the voltage at the second node vp2, that is, the voltage at the first node vn2 is low, and the voltage at the second node vp2 is high, so that a positive differential voltage Δu= - δ >0 is introduced to offset the negative offset voltage originally existing. Therefore, in the latch comparator submodule, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are turned off, and the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are turned on, so that the voltage of the fourth node P3 is pulled down to zero, and the voltage of the third node N3 is pulled up to the power supply voltage terminal VCC by the third PMOS transistor PM3 and the fifth PMOS transistor PM 5. And finally, obtaining a comparison judgment result v_cmp of the differential comparator module from the output end of the output latching submodule to be high level.
However, if the comparison judgment result v_cmp of the latch comparator sub-module is still at a low level after the operational amplifier feedback action, which means that there is still a small negative offset voltage, the first control correction signal dp_cal [3:0] continues to decrease by one, the second control correction signal dn_cal [3:0] continues to increase by one, the corresponding first adjustable capacitor C1 continues to decrease, and the second adjustable capacitor C2 continues to increase, so that the capacitance of the first node vn2 is further smaller than the capacitance of the second node vp2, thereby introducing a positive differential voltage with a larger value to offset the originally existing negative offset voltage. And then outputting a high-level comparison judgment signal through the operational amplifier feedback action of the latch comparator sub-module to serve as a comparison judgment result v_cmp of the differential comparator module.
The coding correction control module adjusts the first control correction signal Dp_cal [3:0] and the second control correction signal Dn_cal [3:0] according to the comparison judgment result v_cmp of the differential comparator module, so that when the comparison judgment result v_cmp of the differential comparator module continuously turns from high level to low level twice, the highest precision is achieved for correcting the offset voltage of the system, and the correction process is controlled to stop.
In the embodiment of the present invention, the working principle of the correction circuit is specifically described that if there is a positive offset voltage δ >0, the first control correction signal dp_cal [3:0] is added with a value 4'b1001 based on the intermediate scale value 4' b1000, the second control correction signal dn_cal [3:0] is subtracted with a value 4'b0111 based on the intermediate scale value 4' b1000, the first adjustable capacitance C1 corresponding to the first control correction signal dp_cal [3:0] is increased, and the second adjustable capacitance C2 corresponding to the second control correction signal dn_cal [3:0] is decreased, so that the capacitance of the first node vn2 is larger than the capacitance of the second node vp 2. At this time, if the voltage difference between the positive input terminal vip and the negative input terminal vin of the pre-amplifier sub-module is still 0, since the capacitance of the first node vn2 is greater than that of the second node vp2, the reset signal v_latch on the gates of the first PMOS tube PM1 and the second PMOS tube PM2 jumps to a high level, so that the voltage at the first node vn2 drops at a slower rate than the voltage at the second node vp2, that is, the voltage at the first node vn2 is at a high level, and the voltage at the second node vp2 is at a low level, so as to introduce a negative differential voltage Δu= - δ <0, so as to cancel out the positive offset voltage originally existing. Therefore, in the latch comparator sub-module, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are turned on, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are turned off, the voltage of the third node N3 is pulled down to zero, and the voltage of the fourth node P3 is pulled up to the supply voltage terminal VCC by the third PMOS transistor PM3 and the fifth PMOS transistor PM 5. And finally, obtaining a comparison judgment result v_cmp of the differential comparator module from the output end of the output latching submodule to be low level.
However, after the feedback action of the operational amplifier of the latch comparator sub-module, the comparison and judgment result v_cmp of the differential comparator module is still at a high level, which means that there is still a small positive offset voltage, then the first control correction signal dp_cal [3:0] continues to be added by one, the second control correction signal dn_cal [3:0] continues to be subtracted by one, the corresponding first adjustable capacitor C1 continues to be increased, and the second adjustable capacitor C2 continues to be reduced, so that the capacitance of the first node vn2 is further greater than the capacitance of the second node vp 2. Thereby introducing a negative differential voltage of greater magnitude to offset the originally existing positive offset voltage. And then outputting a low-level comparison judgment signal through the operational amplifier feedback action of the latch comparator sub-module to serve as a comparison judgment result v_cmp of the differential comparator module.
The coding correction control module adjusts the first control correction signal Dp_cal [3:0] and the second control correction signal Dn_cal [3:0] according to the comparison judgment result v_cmp of the differential comparator module, so that when the comparison judgment result v_cmp of the differential comparator module continuously turns from low level to high level twice, the highest precision is achieved for correcting the offset voltage of the system, and then the correction process is controlled to stop.
The correction circuit based on the differential comparator provided by the embodiment of the invention is purely digital control, the capacitance value corresponding to the corresponding control code is changed, the introduced voltage can be easily changed to offset the offset voltage, the implementation is simple, after the correction mode is finished, the value of the complementary code signal is fixed and does not change, then the whole SAR_ADC can normally sample and convert the analog voltage, and the differential comparator module normally works, and only the capacitance of the first adjustable capacitor C1 and the second adjustable capacitor C2 are different. The whole implementation is simple, all the digital forms are adopted, the extra power consumption is not required, and different processes can be used for rapidly realizing the chip manufacturing flow.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
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| CN110071720B (en) * | 2019-04-25 | 2023-05-26 | 湖南品腾电子科技有限公司 | Self-calibrating full-capacitance successive approximation digital-to-analog conversion circuit |
| CN110474638B (en) * | 2019-07-30 | 2023-04-25 | 成都铭科思微电子技术有限责任公司 | Background correction circuit and method for offset error of latch comparator |
| KR102720543B1 (en) * | 2019-09-19 | 2024-10-21 | 삼성전자주식회사 | Analog digital converter and method for analog to digital converting in the analog digital converter |
| CN110890889B (en) * | 2019-10-21 | 2023-06-06 | 西安电子科技大学 | A Statistical-Based SAR ADC Dual Comparator Offset Mismatch Calibration Method and Circuit |
| US10848166B1 (en) | 2019-12-06 | 2020-11-24 | Analog Devices International Unlimited Company | Dual mode data converter |
| CN111130512B (en) * | 2019-12-11 | 2023-08-01 | 芯创智创新设计服务中心(宁波)有限公司 | Quick comparison circuit and electronic equipment |
| CN114614819B (en) * | 2022-03-17 | 2024-07-02 | 北京安酷智芯科技有限公司 | Source following reference buffer with offset voltage self-correction function |
| CN116938176B (en) * | 2023-06-29 | 2024-04-09 | 华中科技大学 | A real-time DC offset calibration circuit without coupling capacitor |
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