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CN108461594A - LED chip and its manufacturing method - Google Patents

LED chip and its manufacturing method Download PDF

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Publication number
CN108461594A
CN108461594A CN201810063558.2A CN201810063558A CN108461594A CN 108461594 A CN108461594 A CN 108461594A CN 201810063558 A CN201810063558 A CN 201810063558A CN 108461594 A CN108461594 A CN 108461594A
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layer
substrate
led chip
quantum wire
quantum
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陈立人
陆骐峰
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Poly - Can Optoelectronic Technology (suqian) Co Ltd
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Poly - Can Optoelectronic Technology (suqian) Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/811Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/817Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous

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  • Led Devices (AREA)

Abstract

本发明揭示了一种LED芯片及其制造方法,LED芯片包括衬底及位于衬底上的外延结构,衬底为蓝宝石衬底,衬底的晶面沿C晶面偏向M晶面或R晶面而形成偏角。本发明的LED芯片使用特制的衬底,配合相应的工艺条件,在不需要另外制备掩膜的基础上,生长出类量子线外延结构,进一步降低态密度,增强量子局限效应,从而提高发光或电子器件的性能。

The invention discloses an LED chip and a manufacturing method thereof. The LED chip includes a substrate and an epitaxial structure on the substrate. The substrate is a sapphire substrate, and the crystal plane of the substrate is biased toward the M crystal plane or the R crystal plane along the C crystal plane. face to form a deflection angle. The LED chip of the present invention uses a special substrate, cooperates with corresponding process conditions, and grows a quasi-quantum wire epitaxial structure on the basis of not needing to prepare additional masks, further reduces the density of states, and enhances the quantum confinement effect, thereby improving luminescence or performance of electronic devices.

Description

LED芯片及其制造方法LED chip and manufacturing method thereof

技术领域technical field

本发明涉及半导体发光器件技术领域,尤其涉及一种LED芯片及其制造方法。The invention relates to the technical field of semiconductor light emitting devices, in particular to an LED chip and a manufacturing method thereof.

背景技术Background technique

LED照明灯是利用第四代绿色光源LED做成的一种照明灯具。LED被称为第四代照明光源或绿色光源,具有节能、环保、寿命长、体积小等特点,可以广泛应用于各种指示、显示、装饰、背光源、普通照明和城市夜景等领域。LED lighting is a lighting fixture made of the fourth-generation green light source LED. LED is called the fourth-generation lighting source or green light source. It has the characteristics of energy saving, environmental protection, long life, and small size. It can be widely used in various indications, displays, decorations, backlights, general lighting and urban night scenes.

现有光电器件的主流技术多为量子阱结构。The mainstream technology of existing optoelectronic devices is mostly quantum well structure.

Arakawa教授等于1986年在理论上预言,如果相邻量子线或者量子点之间没有强的耦合,则由它们制造的激光器在阈值电流、调制动力学和谱线特性等方面将优于量子阱激光器。Sakaki教授于1987年预言,在量子线中,由于维度限制大大减小了弹性散射概率,就能得到非常高的电子迁移率,因此能用于制作高速电子器件。Professor Arakawa et al. predicted in theory in 1986 that if there is no strong coupling between adjacent quantum wires or quantum dots, the lasers manufactured by them will be superior to quantum well lasers in terms of threshold current, modulation dynamics and spectral line characteristics. . Professor Sakaki predicted in 1987 that in quantum wires, due to the greatly reduced elastic scattering probability due to dimensional constraints, very high electron mobility can be obtained, so it can be used to make high-speed electronic devices.

量子线结构材料的研究不仅是半导体物理学、材料学研究的基本问题,而且其优异的光学和电学特性可直接被利用制备成性能优良的器件产品,因此国内外都投入很大的资金和技术力量来从事这一领域的研究。The study of quantum wire structure materials is not only a basic issue in semiconductor physics and materials science, but also its excellent optical and electrical properties can be directly used to prepare devices with excellent performance. Therefore, a lot of money and technology have been invested at home and abroad. to engage in research in this field.

目前,如何提高器件产品的性能是研究重点。At present, how to improve the performance of device products is the focus of research.

发明内容Contents of the invention

本发明的目的在于提供一种LED芯片及其制造方法。The object of the present invention is to provide an LED chip and a manufacturing method thereof.

为实现上述发明目的之一,本发明一实施方式提供一种LED芯片,包括衬底及位于所述衬底上的外延结构,所述衬底为蓝宝石衬底,所述衬底的晶面沿C晶面偏向M晶面或R晶面而形成偏角。To achieve one of the objectives of the above invention, an embodiment of the present invention provides an LED chip, including a substrate and an epitaxial structure on the substrate, the substrate is a sapphire substrate, and the crystal plane of the substrate is along the The C crystal plane is biased towards the M crystal plane or the R crystal plane to form an off angle.

作为本发明一实施方式的进一步改进,所述偏角范围为0.7°~1.5°。As a further improvement of an embodiment of the present invention, the range of the off-angle is 0.7°-1.5°.

作为本发明一实施方式的进一步改进,所述偏角范围为0.8°~1°。As a further improvement of an embodiment of the present invention, the range of the off-angle is 0.8°-1°.

作为本发明一实施方式的进一步改进,所述外延结构包括量子线发光层,所述量子线发光层根据所述偏角生长而形成褶皱状,且所述量子线发光层的发光区于所述外延结构叠加方向的高度不小于0.5nm。As a further improvement of an embodiment of the present invention, the epitaxial structure includes a quantum wire light-emitting layer, the quantum wire light-emitting layer is grown in a wrinkled shape according to the off-angle growth, and the light-emitting region of the quantum wire light-emitting layer is located between the The height of the superposition direction of the epitaxial structure is not less than 0.5nm.

作为本发明一实施方式的进一步改进,所述发光区的原子层数量不小于10个。As a further improvement of an embodiment of the present invention, the number of atomic layers in the light emitting region is not less than 10.

作为本发明一实施方式的进一步改进,所述外延结构由下向上依次包括缓冲层、高温AlGaN层、N型AlGaN层、N型AlGaN表面处理层、量子线发光层、量子势垒层、电子阻挡层、P型披覆层、P型接触层,其中,所述量子线发光层为AlGaN/GaN多重类量子线发光层。As a further improvement of an embodiment of the present invention, the epitaxial structure includes a buffer layer, a high-temperature AlGaN layer, an N-type AlGaN layer, an N-type AlGaN surface treatment layer, a quantum wire light-emitting layer, a quantum barrier layer, and an electron barrier layer from bottom to top. layer, a P-type cladding layer, and a P-type contact layer, wherein the quantum-ray emitting layer is an AlGaN/GaN multi-type quantum-ray emitting layer.

作为本发明一实施方式的进一步改进,所述外延结构由下向上依次包括低缺陷GaN层、InGaN应力调试层、N型AlGaN/GaN层、N型InGaN表面处理层、量子线发光层、量子势垒层、电子阻挡层、P型披覆层、P型接触层,其中,所述量子线发光层为GaN/InGaN多重类量子线发光层。As a further improvement of an embodiment of the present invention, the epitaxial structure includes a low-defect GaN layer, an InGaN stress adjustment layer, an N-type AlGaN/GaN layer, an N-type InGaN surface treatment layer, a quantum wire light-emitting layer, and a quantum potential A barrier layer, an electron blocking layer, a P-type cladding layer, and a P-type contact layer, wherein the quantum-wire light-emitting layer is a GaN/InGaN multi-type quantum-wire light-emitting layer.

为实现上述发明目的之一,本发明一实施方式提供一种LED芯片的制造方法,包括步骤:In order to achieve one of the purposes of the above invention, an embodiment of the present invention provides a method for manufacturing an LED chip, including steps:

提供一衬底,所述衬底为蓝宝石衬底;Provide a substrate, the substrate is a sapphire substrate;

切抛所述衬底而使得所述衬底的晶面沿C晶面偏向M晶面或R晶面而形成偏角;cutting and polishing the substrate so that the crystal plane of the substrate is biased toward the M crystal plane or the R crystal plane along the C crystal plane to form an off angle;

于所述衬底上形成外延结构。An epitaxial structure is formed on the substrate.

作为本发明一实施方式的进一步改进,所述偏角范围为0.7°~1.5°。As a further improvement of an embodiment of the present invention, the range of the off-angle is 0.7°-1.5°.

作为本发明一实施方式的进一步改进,所述外延结构包括量子线发光层,所述量子线发光层根据所述偏角生长而形成褶皱状,且所述量子线发光层的发光区于所述外延结构叠加方向的高度不小于0.5nm。As a further improvement of an embodiment of the present invention, the epitaxial structure includes a quantum wire light-emitting layer, the quantum wire light-emitting layer is grown in a wrinkled shape according to the off-angle growth, and the light-emitting region of the quantum wire light-emitting layer is located between the The height of the superposition direction of the epitaxial structure is not less than 0.5nm.

与现有技术相比,本发明的有益效果在于:本发明一实施方式的LED芯片使用特制的衬底,配合相应的工艺条件,在不需要另外制备掩膜的基础上,生长出类量子线外延结构,进一步降低态密度,增强量子局限效应,从而提高发光或电子器件的性能。Compared with the prior art, the beneficial effect of the present invention is that: the LED chip in one embodiment of the present invention uses a special substrate, cooperates with the corresponding process conditions, and grows quasi-quantum wires on the basis of not needing to prepare additional masks. The epitaxial structure further reduces the density of states and enhances the quantum confinement effect, thereby improving the performance of light-emitting or electronic devices.

附图说明Description of drawings

图1是本发明一实施方式的LED芯片示意图;Fig. 1 is a schematic diagram of an LED chip according to an embodiment of the present invention;

图2是本发明一实施方式的量子线发光层区域示意图;Fig. 2 is a schematic diagram of the region of the quantum wire light-emitting layer according to an embodiment of the present invention;

图3是本发明另一实施方式的LED芯片示意图;Fig. 3 is a schematic diagram of an LED chip according to another embodiment of the present invention;

图4是本发明一实施方式的LED芯片的制造方法步骤图。Fig. 4 is a step diagram of a method for manufacturing an LED chip according to an embodiment of the present invention.

具体实施方式Detailed ways

以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明,本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

参图1,为本发明一实施方式的LED芯片100的示意图。Referring to FIG. 1 , it is a schematic diagram of an LED chip 100 according to an embodiment of the present invention.

LED芯片100包括衬底10及位于衬底10上的外延结构20。The LED chip 100 includes a substrate 10 and an epitaxial structure 20 on the substrate 10 .

衬底10为蓝宝石衬底。The substrate 10 is a sapphire substrate.

该衬底10可以为平片衬底,也可以为图案化衬底。The substrate 10 can be a flat substrate or a patterned substrate.

衬底10的晶面沿C晶面偏向M晶面或R晶面而形成偏角。The crystal plane of the substrate 10 forms an off angle along the C crystal plane to the M crystal plane or the R crystal plane.

这里,LED芯片100使用特制的衬底,配合相应的工艺条件,在不需要另外制备掩膜的基础上,生长出类量子线外延结构,进一步降低态密度,增强量子局限效应,从而提高发光或电子器件的性能。Here, the LED chip 100 uses a special substrate, cooperates with corresponding process conditions, and grows a quasi-quantum wire epitaxial structure on the basis of not needing to prepare an additional mask, further reduces the density of states, enhances the quantum confinement effect, and thus improves luminescence or performance of electronic devices.

在本实施方式中,偏角范围为0.7°~1.5°。In this embodiment, the range of the off-angle is 0.7°˜1.5°.

较佳的,偏角范围为0.8°~1°。Preferably, the deflection angle ranges from 0.8° to 1°.

在本实施方式中,外延结构20以AlGaN基紫外发光二极管外延结构为例。In this embodiment, the epitaxial structure 20 is an example of an AlGaN-based ultraviolet light emitting diode epitaxial structure.

外延结构20由下向上依次包括缓冲层21、高温AlGaN层22、N型AlGaN层23、N型AlGaN表面处理层24、量子线发光层25、量子势垒层26、电子阻挡层27、P型披覆层28、P型接触层29。The epitaxial structure 20 includes a buffer layer 21, a high-temperature AlGaN layer 22, an N-type AlGaN layer 23, an N-type AlGaN surface treatment layer 24, a quantum light emitting layer 25, a quantum barrier layer 26, an electron blocking layer 27, and a P-type AlGaN layer from bottom to top. cladding layer 28 and P-type contact layer 29 .

一般的,紫外光随着波长变短,需要在发光层加入大量Al组份以提高禁带宽度。Generally, as the wavelength of ultraviolet light becomes shorter, it is necessary to add a large amount of Al components in the light-emitting layer to increase the forbidden band width.

一方面,由于发光层承受张应力,发光模态为TM模,不利于出光;另一方面,Al含量多时对LED芯片的质量有负面影响。On the one hand, since the light-emitting layer is subjected to tensile stress, the light-emitting mode is TM mode, which is not conducive to light emission; on the other hand, a high Al content has a negative impact on the quality of the LED chip.

本实施方式使用特定偏角的衬底10结合外延工艺形成自组装AlGaN/GaN多重类量子线发光层作为发光层,利用二维量子局限效应提高量子能级,从而达到波长变短的目的。In this embodiment, a self-assembled AlGaN/GaN multi-quantum-like light-emitting layer is formed using a substrate 10 with a specific off-angle combined with an epitaxial process as a light-emitting layer, and the two-dimensional quantum confinement effect is used to increase the quantum energy level, thereby achieving the purpose of shortening the wavelength.

以下对外延结构20的各层作具体说明。Each layer of the epitaxial structure 20 will be described in detail below.

缓冲层21为AlN层,可以使用溅射机台在衬底10上制备15~25nm厚的AlN层,这里以缓冲层21的厚度为20nm为例。The buffer layer 21 is an AlN layer. A sputtering machine can be used to prepare an AlN layer with a thickness of 15-25 nm on the substrate 10 . Here, the thickness of the buffer layer 21 is 20 nm as an example.

高温AlGaN层22为非掺杂AlGaN层,高温AlGaN层22的厚度为3um。The high temperature AlGaN layer 22 is a non-doped AlGaN layer, and the thickness of the high temperature AlGaN layer 22 is 3um.

这里,设备温度控制在1120℃,压强控制在50Torr。Here, the temperature of the equipment is controlled at 1120° C., and the pressure is controlled at 50 Torr.

N型AlGaN层23的厚度为1.5um。The thickness of the N-type AlGaN layer 23 is 1.5um.

这里,设备温度控制在1100℃,压强控制在50Torr,N型AlGaN层23的掺杂浓度为8*1018/cm3。Here, the device temperature is controlled at 1100° C., the pressure is controlled at 50 Torr, and the doping concentration of the N-type AlGaN layer 23 is 8*10 18 /cm3.

N型AlGaN表面处理层24的厚度为0.3um。The thickness of the N-type AlGaN surface treatment layer 24 is 0.3um.

这里,设备温度控制在980~1100℃范围,压强控制在100Torr~200torr范围,N型AlGaN表面处理层24为低掺杂表面处理层。Here, the device temperature is controlled in the range of 980-1100° C., the pressure is controlled in the range of 100 Torr-200 Torr, and the N-type AlGaN surface treatment layer 24 is a low-doped surface treatment layer.

量子线发光层25为AlGaN/GaN多重类量子线发光层。The quantum beam light-emitting layer 25 is an AlGaN/GaN multi-type quantum beam light-emitting layer.

这里,设备温度控制在900~980℃范围,压强控制在100~200Torr范围,V族/III族反应物的摩尔比控制在1000~3000范围。Here, the equipment temperature is controlled in the range of 900-980° C., the pressure is controlled in the range of 100-200 Torr, and the molar ratio of Group V/Group III reactants is controlled in the range of 1000-3000.

量子势垒层26的厚度为5~10nm。The thickness of the quantum barrier layer 26 is 5-10 nm.

这里,设备温度控制在980℃,压强控制在100~200Torr范围。Here, the temperature of the equipment is controlled at 980° C., and the pressure is controlled at a range of 100 to 200 Torr.

需要说明的是,量子线发光层25及量子势垒层26可重复生长,这里以重复生长5~15次为例。It should be noted that the quantum wire light-emitting layer 25 and the quantum barrier layer 26 can be grown repeatedly, and here the repeated growth is taken 5-15 times as an example.

电子阻挡层27为P型电子阻挡层,电子阻挡层27的厚度为30nm。The electron blocking layer 27 is a P-type electron blocking layer, and the thickness of the electron blocking layer 27 is 30 nm.

这里,设备温度控制在900~980℃范围,压强控制在50Torr。Here, the temperature of the equipment is controlled in the range of 900-980° C., and the pressure is controlled at 50 Torr.

P型披覆层28为P型AlGaN披覆层,P型披覆层28的厚度为40nm。The P-type cladding layer 28 is a P-type AlGaN cladding layer, and the thickness of the P-type cladding layer 28 is 40 nm.

这里,设备温度控制在1000~1050℃,压强控制在50Torr。Here, the temperature of the equipment is controlled at 1000-1050° C., and the pressure is controlled at 50 Torr.

另外,生长完P型披覆层28后透过生长工艺可以使表面恢复平整以利于后续工艺制作。In addition, after the growth of the P-type cladding layer 28 , the growth process can restore the surface to be flat, so as to facilitate subsequent manufacturing processes.

P型接触层29为P型GaN接触层,P型接触层29的厚度为8nm。The P-type contact layer 29 is a P-type GaN contact layer, and the thickness of the P-type contact layer 29 is 8 nm.

这里,设备温度控制在900~980℃,压强控制在50Torr。Here, the temperature of the equipment is controlled at 900-980° C., and the pressure is controlled at 50 Torr.

当然,上述温度、压强、厚度等的描述仅是示例性说明,不以此为限。Of course, the above descriptions of temperature, pressure, thickness, etc. are only exemplary descriptions and are not limited thereto.

在本实施方式中,量子线发光层25根据衬底10偏角生长而形成褶皱状。In this embodiment, the quantum beam light-emitting layer 25 is grown in a corrugated shape according to the off-angle growth of the substrate 10 .

具体的,参图2,N型AlGaN表面处理层24成褶皱状,调整适当的温度和V族/III族反应物的摩尔,在N型AlGaN表面处理层24上进行量子线发光层25的生长,在衬底10的偏角选定得当并且各层温度条件控制良好的前提下,量子线发光层25将沿晶体特定面向的“台阶”选择性生长,并且通过偏角及生长条件,可控制量子线发光层25的层高,而后,在量子线发光层25上在生长一层较量子线发光层25禁带宽度更高的量子势垒层26。Specifically, referring to FIG. 2, the N-type AlGaN surface treatment layer 24 is wrinkled, and the appropriate temperature and the moles of group V/III reactants are adjusted to grow the quantum beam light emitting layer 25 on the N-type AlGaN surface treatment layer 24. , under the premise that the off angle of the substrate 10 is properly selected and the temperature conditions of each layer are well controlled, the quantum wire light-emitting layer 25 will grow selectively along the "step" of the specific face of the crystal, and through the off angle and growth conditions, it can control The layer height of the quantum wire light emitting layer 25 is high, and then, a quantum barrier layer 26 with a higher forbidden band width than the quantum wire light emitting layer 25 is grown on the quantum wire light emitting layer 25 .

这里,量子线发光层25纵向受到两较高的禁带宽度限制,在平面上沿着原子台阶选择性生长,两者结合形成类量子线的效果。Here, the quantum wire light-emitting layer 25 is limited by two higher forbidden band widths in the longitudinal direction, and grows selectively along the atomic steps on the plane, and the combination of the two forms a quantum wire-like effect.

需要说明的是,量子线发光层25在不同的区域厚度不同,参图2,量子线发光层25在虚线框处的厚度较大,虚线框处的量子线发光层25才是真正起到发光作用的发光区25’。It should be noted that the thickness of the quantum wire light-emitting layer 25 is different in different regions. Referring to FIG. 2, the thickness of the quantum wire light-emitting layer 25 at the dotted line frame is relatively large, and the quantum wire light-emitting layer 25 at the dotted line frame is the one that really plays a role in emitting light. The active light-emitting area 25'.

量子线发光层25的发光区25’于外延结构20叠加方向的高度不小于0.5nm,即此时台阶高度不小于0.5nm。The height of the light-emitting region 25' of the quantum wire light-emitting layer 25 in the stacking direction of the epitaxial structure 20 is not less than 0.5 nm, that is, the step height is not less than 0.5 nm.

发光区25’的原子层数量不小于10个,这里,以生长10~50原子层为例。The number of atomic layers in the light-emitting region 25' is not less than 10. Here, the growth of 10-50 atomic layers is taken as an example.

在本发明另一实施方式中,结合图3,外延结构20a以GaN半导体激光二极管外延结构为例。In another embodiment of the present invention, referring to FIG. 3 , the epitaxial structure 20 a is an epitaxial structure of a GaN semiconductor laser diode as an example.

外延结构20a由下向上依次包括低缺陷GaN层21a、InGaN应力调试层22a、N型AlGaN/GaN层23a、N型InGaN表面处理层24a、量子线发光层25a、量子势垒层26a、电子阻挡层27a、P型披覆层28a、P型接触层29a。The epitaxial structure 20a includes, from bottom to top, a low-defect GaN layer 21a, an InGaN stress adjustment layer 22a, an N-type AlGaN/GaN layer 23a, an N-type InGaN surface treatment layer 24a, a quantum wire light-emitting layer 25a, a quantum barrier layer 26a, an electron barrier layer 27a, P-type cladding layer 28a, and P-type contact layer 29a.

这里,类量子线组成的量子线发光层25a具有二维量子局限的优势,拥有更小的态密度,使得微分增益更高,进而降低阀值电流。Here, the quantum wire light-emitting layer 25a composed of quasi-quantum wires has the advantage of two-dimensional quantum confinement, and has a smaller density of states, which makes the differential gain higher, thereby reducing the threshold current.

以下对外延结构20a的各层作具体说明。Each layer of the epitaxial structure 20a will be specifically described below.

低缺陷GaN层21a使用HVPE或Elog法形成。The low-defect GaN layer 21a is formed using HVPE or Elog method.

InGaN应力调试层22a的厚度为1um。The thickness of the InGaN stress adjustment layer 22a is 1um.

这里,设备温度控制在900℃,压强控制在200Torr。Here, the temperature of the equipment is controlled at 900° C., and the pressure is controlled at 200 Torr.

N型AlGaN/GaN层23a的厚度为1.5um。The thickness of the N-type AlGaN/GaN layer 23a is 1.5um.

这里,设备温度控制在1100℃,压强控制在100Torr,N型AlGaN/GaN层23a的掺杂浓度为8*1018/cm3。Here, the device temperature is controlled at 1100° C., the pressure is controlled at 100 Torr, and the doping concentration of the N-type AlGaN/GaN layer 23 a is 8*10 18 /cm3.

N型InGaN表面处理层24a的厚度为0.3um。The thickness of the N-type InGaN surface treatment layer 24a is 0.3um.

这里,设备温度控制在980~1100℃范围,压强控制在100Torr~200torr范围,N型InGaN表面处理层24a为低掺杂N型InGaN表面处理层。Here, the device temperature is controlled in the range of 980-1100° C., the pressure is controlled in the range of 100 Torr-200 Torr, and the N-type InGaN surface treatment layer 24 a is a low-doped N-type InGaN surface treatment layer.

量子线发光层25a为GaN/InGaN多重类量子线发光层。The quantum beam light-emitting layer 25a is a GaN/InGaN multi-type quantum beam light-emitting layer.

这里,设备温度控制在780~800℃范围,压强控制在100~200Torr范围,V族/III族反应物的摩尔比控制在1000~3000范围。Here, the equipment temperature is controlled in the range of 780-800° C., the pressure is controlled in the range of 100-200 Torr, and the molar ratio of Group V/Group III reactants is controlled in the range of 1000-3000.

量子势垒层26a的厚度为5~10nm。The thickness of the quantum barrier layer 26a is 5-10 nm.

这里,设备温度控制在900℃,压强控制在100~200Torr范围。Here, the temperature of the equipment is controlled at 900° C., and the pressure is controlled at a range of 100 to 200 Torr.

需要说明的是,量子线发光层25a及量子势垒层26a可重复生长,这里以重复生长3~6次为例。It should be noted that the quantum wire light-emitting layer 25 a and the quantum barrier layer 26 a can be grown repeatedly, and the repeated growth is taken 3 to 6 times as an example.

电子阻挡层27a为P型电子阻挡层,电子阻挡层27a的厚度为30nm。The electron blocking layer 27 a is a P-type electron blocking layer, and the thickness of the electron blocking layer 27 a is 30 nm.

这里,设备温度控制在900~980℃范围,压强控制在50Torr。Here, the temperature of the equipment is controlled in the range of 900-980° C., and the pressure is controlled at 50 Torr.

P型披覆层28a为P型AlGaN/GaN披覆层,P型披覆层28a的厚度为800nm。The P-type cladding layer 28 a is a P-type AlGaN/GaN cladding layer, and the thickness of the P-type cladding layer 28 a is 800 nm.

这里,设备温度控制在1000~1050℃范围,压强控制在50Torr。Here, the temperature of the equipment is controlled in the range of 1000-1050° C., and the pressure is controlled at 50 Torr.

P型接触层29a为P型GaN接触层,P型接触层29a的厚度为8nm。The P-type contact layer 29 a is a P-type GaN contact layer, and the thickness of the P-type contact layer 29 a is 8 nm.

这里,设备温度控制在900~980℃,压强控制在50Torr。Here, the temperature of the equipment is controlled at 900-980° C., and the pressure is controlled at 50 Torr.

在本实施方式中,量子线发光层25a纵向受到两较高的禁带宽度限制,在平面上沿着原子台阶选择性生长,两者结合形成类量子线的效果。In this embodiment, the quantum wire light-emitting layer 25a is limited by two higher forbidden band widths in the longitudinal direction, and grows selectively along the atomic steps on the plane, and the combination of the two forms a quantum wire-like effect.

外延结构20a的其他说明可以参考上一实施方式,在此不再赘述。For other descriptions of the epitaxial structure 20a, reference may be made to the previous embodiment, which will not be repeated here.

本发明一实施方式还提供一种LED芯片100的制造方法,结合上述LED芯片100的结构说明及图4,LED芯片100的制造方法包括步骤:An embodiment of the present invention also provides a method for manufacturing the LED chip 100. Combining the above structural description of the LED chip 100 and FIG. 4, the method for manufacturing the LED chip 100 includes steps:

提供一衬底10,衬底10为蓝宝石衬底;Provide a substrate 10, the substrate 10 is a sapphire substrate;

切抛衬底10而使得衬底10的晶面沿C晶面偏向M晶面或R晶面而形成偏角;Cutting and throwing the substrate 10 so that the crystal plane of the substrate 10 is biased toward the M crystal plane or the R crystal plane along the C crystal plane to form an off angle;

于衬底10上形成外延结构20。An epitaxial structure 20 is formed on the substrate 10 .

这里,LED芯片100使用特制的衬底,配合相应的工艺条件,在不需要另外制备掩膜的基础上,生长出类量子线外延结构,进一步降低态密度,增强量子局限效应,从而提高发光或电子器件的性能。Here, the LED chip 100 uses a special substrate, cooperates with corresponding process conditions, and grows a quasi-quantum wire epitaxial structure on the basis of not needing to prepare an additional mask, further reduces the density of states, enhances the quantum confinement effect, and thus improves luminescence or performance of electronic devices.

在本实施方式中,偏角范围为0.7°~1.5°。In this embodiment, the range of the off-angle is 0.7°˜1.5°.

较佳的,偏角范围为0.8°~1°。Preferably, the deflection angle ranges from 0.8° to 1°.

在本实施方式中,外延结构20包括量子线发光层25,量子线发光层25根据偏角生长而形成褶皱状,且量子线发光层25的发光区25’于外延结构20叠加方向的高度不小于0.5nm。In this embodiment, the epitaxial structure 20 includes a quantum wire light-emitting layer 25, and the quantum-wire light-emitting layer 25 forms wrinkles according to the off-angle growth, and the height of the light-emitting region 25' of the quantum-wire light-emitting layer 25 in the stacking direction of the epitaxial structure 20 is different. Less than 0.5nm.

本实施方式的LED芯片100的制造方法的其他说明可以参考上述LED芯片100的说明,在此不再赘述。For other descriptions of the manufacturing method of the LED chip 100 in this embodiment, reference may be made to the description of the above-mentioned LED chip 100 , which will not be repeated here.

应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施方式中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。It should be understood that although this description is described according to implementation modes, not each implementation mode only contains an independent technical solution, and this description in the description is only for clarity, and those skilled in the art should take the description as a whole, and each The technical solutions in the embodiments can also be properly combined to form other embodiments that can be understood by those skilled in the art.

上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明,它们并非用以限制本发明的保护范围,凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。The series of detailed descriptions listed above are only specific descriptions for feasible implementations of the present invention, and they are not intended to limit the protection scope of the present invention. Any equivalent implementation or implementation that does not depart from the technical spirit of the present invention All changes should be included within the protection scope of the present invention.

Claims (10)

1. a kind of LED chip, which is characterized in that the epitaxial structure including substrate and on the substrate, the substrate are indigo plant The crystal face of jewel substrate, the substrate is biased to M crystal faces or R crystal faces along C crystal faces and forms drift angle.
2. LED chip according to claim 1, which is characterized in that the angle range is 0.7 °~1.5 °.
3. LED chip according to claim 2, which is characterized in that the angle range is 0.8 °~1 °.
4. LED chip according to claim 1, which is characterized in that the epitaxial structure includes quantum wire luminescent layer, described Quantum wire luminescent layer grows according to the drift angle and forms accordion, and the luminous zone of the quantum wire luminescent layer is in the extension The height in folded structures direction is not less than 0.5nm.
5. LED chip according to claim 4, which is characterized in that the atom layer number of the luminous zone is not less than 10.
6. LED chip according to claim 4, which is characterized in that the epitaxial structure includes buffering successively from bottom to top Layer, high temperature AlGaN layer, N-type AlGaN layer, N-type AlGaN surface-treated layers, quantum wire luminescent layer, quantum barrier layer, electronic blocking Layer, p-type coating layer, p-type contact layer, wherein the quantum wire luminescent layer is the multiple class quantum wire luminescent layers of AlGaN/GaN.
7. LED chip according to claim 4, which is characterized in that the epitaxial structure includes low lack successively from bottom to top Fall into GaN layer, InGaN stress debugging layer, AlGaN/GaN layers of N-type, N-type InGaN surface-treated layers, quantum wire luminescent layer, quantum potential Barrier layer, electronic barrier layer, p-type coating layer, p-type contact layer, wherein the quantum wire luminescent layer is the multiple class amounts of GaN/InGaN Sub-line luminescent layer.
8. a kind of manufacturing method of LED chip, it is characterised in that including step:
A substrate is provided, the substrate is Sapphire Substrate;
It cuts and throws the substrate and the crystal face of the substrate is made to form drift angle along C crystal faces deviation M crystal faces or R crystal faces;
In forming epitaxial structure on the substrate.
9. the manufacturing method of LED chip according to claim 8, which is characterized in that the angle range be 0.7 °~ 1.5°。
10. the manufacturing method of LED chip according to claim 8, which is characterized in that the epitaxial structure includes quantum wire Luminescent layer, the quantum wire luminescent layer grow according to the drift angle and form accordion, and the quantum wire luminescent layer is luminous The height of epitaxial structure Direction of superposition described in Qu Yu is not less than 0.5nm.
CN201810063558.2A 2018-01-23 2018-01-23 LED chip and its manufacturing method Withdrawn CN108461594A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101528991A (en) * 2006-10-20 2009-09-09 松下电工株式会社 Sapphire substrate, nitride semiconductor luminescent element using the sapphire substrate, and method for manufacturing the nitride semiconductor luminescent element
CN103296168A (en) * 2012-02-28 2013-09-11 苏州新纳晶光电有限公司 InGaN quantum dot epitaxial wafer prepared through substrate with atom step and preparation method thereof
CN103762286A (en) * 2013-08-09 2014-04-30 青岛杰生电气有限公司 LED with high light extraction efficiency
CN104037287A (en) * 2014-06-10 2014-09-10 广州市众拓光电科技有限公司 LED epitaxial wafer grown on Si substrate and preparation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101528991A (en) * 2006-10-20 2009-09-09 松下电工株式会社 Sapphire substrate, nitride semiconductor luminescent element using the sapphire substrate, and method for manufacturing the nitride semiconductor luminescent element
CN103296168A (en) * 2012-02-28 2013-09-11 苏州新纳晶光电有限公司 InGaN quantum dot epitaxial wafer prepared through substrate with atom step and preparation method thereof
CN103762286A (en) * 2013-08-09 2014-04-30 青岛杰生电气有限公司 LED with high light extraction efficiency
CN104037287A (en) * 2014-06-10 2014-09-10 广州市众拓光电科技有限公司 LED epitaxial wafer grown on Si substrate and preparation method thereof

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