CN108449086B - Method and circuit for synchronizing parallel ports of multi-channel high-speed serial bus sending end - Google Patents
Method and circuit for synchronizing parallel ports of multi-channel high-speed serial bus sending end Download PDFInfo
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- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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Abstract
The invention relates to a method, a circuit and a chip for synchronizing parallel ports of a sending end in a multi-channel high-speed serial bus. In the prior art, parallel port synchronization is usually realized by using a cache, and the cache usually occupies a large chip area and increases the cost. The circuit/chip only uses a plurality of logic gates, and is matched with automatic phase detection to dynamically adjust the phase of the parallel clock in the actual working process to realize port synchronization. The method, the circuit and the chip of the invention simultaneously solve the problems of parallel port synchronization and clock domain crossing, avoid using a buffer, reduce resource overhead and link delay, automatically adjust the phase relation between clocks in the actual working process and ensure that the system is not influenced by voltage, temperature and process deviation.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a physical layer design in a high-speed serial bus, in particular to a method, a circuit and a chip for synchronizing parallel data ports of a sending end in the physical layer.
Background
In the field of communications, serial communication is a communication method in which only one bit of data is transmitted at a time when data is transmitted. More and more parallel bus architectures are now being replaced by serial buses, such as PCIe, SATA and USB, among others. Serial buses typically have SerDes as the physical layer basis, and the communication medium is typically traces on a printed circuit board, a backplane, a cable, or the like. The communication adopts a point-to-point topological structure, differential routing is adopted, and the problem of clock skew does not exist. Meanwhile, a clock signal is not required to be sent simultaneously along with the data, and a receiving end can extract and recover a clock from the data to receive the data.
High speed serial bus designs often use a multi-lane architecture to increase bandwidth, such as PCIe architectures that often use 2 lanes, 4 lanes, or even 32 lanes. The multi-channel structure often faces the problem of time domain offset between channels, the main offset is from the communication medium, and in order to deal with the problem, a de-offset buffer is often implemented at the receiving end. However, the cache usually occupies a large chip area, the design cost is increased, various protocols usually strictly limit the maximum clock skew of the transmitting end, and the chip design must meet the protocol requirements. The PCIe fourth generation protocol requires that the time domain offset of the transmitting end is less than 1.25 nanoseconds. In various protocols, the requirement for clock skew of a multi-channel transmitting end in a high-speed serial bus is often smaller than the period of a parallel clock, for example, when the parallel bit width is 16 bits or 32 bits, the number of parallel clock periods of a PCIe physical layer and an upper layer is in the range of 2 nanoseconds to 4 nanoseconds, and if time domain skew smaller than 1.25ns is to be achieved, timing sequence difference cannot exist among multiple channels of a parallel data port.
In the prior art, all channels usually generate parallel clocks at the same time when the physical layer is initialized, and the phases of the parallel clocks are similar, so as to ensure that no time sequence difference exists when the parallel data ports transmit data. However, because the multi-channel occupies a large area on a chip, process deviation often exists between the channels, and voltage and temperature drift conditions are encountered in the actual application process, so that clock synchronization initialization fails or after initialization succeeds, in the actual working process, along with the change of temperature and voltage, the conditions of synchronization failure, clock domain crossing problem and the like of a certain channel or certain channels occur, and finally, the connection failure of the whole communication link is caused.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method, a circuit and a chip for synchronizing parallel ports of a multi-channel high-speed serial bus transmitting end. The circuit/chip only uses a plurality of logic gates, and is matched with automatic phase detection to dynamically adjust the phase of the parallel clock in the actual working process to realize port synchronization. The method, the circuit and the chip of the invention simultaneously solve the problems of parallel port synchronization and clock domain crossing, avoid using a buffer, reduce resource overhead and link delay, automatically adjust the phase relation between clocks in the actual working process and ensure that the system is not influenced by voltage, temperature and process deviation.
In order to achieve the above purposes, the invention adopts the technical scheme that: a method for synchronizing parallel ports of a multi-channel high-speed serial bus sending end comprises the following steps:
s1, locking by a phase-locked loop to generate a local high-speed clock;
s2, selecting one output clock from the output clocks of each transmitting end transmission channel as a system master clock, and transmitting the system master clock to each transmitting end transmission channel;
s3, selecting each transmitting end transmission channel to be subjected to information transmission, and when each selected transmitting end transmission channel detects that a phase-locked loop is locked, performing clock initialization and transmitting a clock preparation signal;
s4, performing AND operation on each clock preparation signal sent by each sending end transmission channel to obtain a fully-reset clock preparation signal, sampling the fully-reset clock preparation signal by a system master clock to obtain a synchronization enabling signal in a system master clock domain, and sending the synchronization enabling signal to each selected sending end transmission channel;
s5, the selected transmission channels of each sending end use the synchronous enabling signal as the adjusting signal of the clock generated by the frequency divider, start the frequency divider, generate the frequency dividing clock as the output clock of the transmission channels of each sending end;
s6, comparing the phase difference value of the system master clock and the output clock of the transmitting end channel;
and S7, when the phase difference value is larger than or smaller than the threshold value, adjusting the phase of the output clock to keep the system main clock and the output clock to keep a fixed phase difference and achieve clock synchronization.
Further, the specific method for comparing the phase difference value between the system master clock and the output clock of the sending end channel is to phase-discriminate through a phase discriminator, compare the phase difference, and record the specific phase difference value through a counter.
Further, the phase detector is a JK trigger or a Hogge phase detector.
Further, the specific method for adjusting the phase of the output clock is to keep the phase difference value between 3-4 local high-speed clock cycles, and when the phase difference value is greater than 2, keep the phase of the output clock of the channel still; when the phase difference value is less than or equal to 2, the output clock phase of the channel is shifted backwards.
A kind of multi-channel high-speed serial bus sending end parallel port synchronous circuit, this circuit includes: the device comprises a phase-locked loop, a clock signal selection unit, a plurality of transmitting end transmission channels and a synchronous enabling generation unit; the transmission channel at the transmitting end also comprises a frequency divider, a phase comparator, a phase controller and a parallel-serial data converter;
the phase-locked loop is used for generating a local high-speed clock signal and is connected with a plurality of transmitting end transmission channels;
the clock signal selection unit is used for selecting one output clock signal from the output clocks of the plurality of transmitting end transmission channels as a system main clock to be transmitted to each transmitting end transmission channel;
the transmitting end transmission channel is used for carrying out clock initialization on the transmitting end transmission channel when the phase-locked loop is detected to be locked, and transmitting a clock preparation signal to the synchronization enabling generation unit;
the synchronous enabling generation unit is used for performing AND operation on the clock preparation signals sent by the selected channels to obtain fully-reset clock preparation signals, and performing system master clock sampling on the fully-reset clock preparation signals to obtain synchronous enabling signals in a system master clock domain;
the parallel-serial data converter of the transmission channel of the sending end is used for converting data of a parallel port of a system into serial data to be transmitted in the channel;
the frequency divider of the transmission channel of the sending end is started according to the synchronous enabling signal, frequency division is carried out based on a local high-speed clock, and a frequency division clock is generated to be used as an output clock of the transmission channel of the sending end;
the phase comparator of the transmission channel at the transmitting end receives the output clock and the system main clock generated by the frequency divider, is connected with the phase controller and is used for comparing the phase difference value of the system main clock and the output clock of the transmission channel at the transmitting end;
and the phase controller of the transmission channel at the transmitting end is connected with the frequency divider, the phase comparator and the phase-locked loop and used for adjusting the local high-speed clock phase of the phase-locked loop when the phase difference value is greater than or less than a threshold value so as to adjust the output clock phase.
Furthermore, the phase comparator comprises a phase discriminator and a two-bit phase counter, phase discrimination is carried out through the phase discriminator, phase difference is compared, and a specific phase difference value is recorded through the two-bit phase counter.
Further, the phase detector is a JK trigger or a Hogge phase detector.
Further, the specific method for adjusting the phase of the output clock by the phase controller is that the phase difference value is kept between 3-4 local high-speed clock cycles, and when the phase difference value is larger than 2, the phase of the output clock of the channel is kept unchanged; when the phase difference value is less than or equal to 2, the output clock phase of the channel is shifted backwards.
A multichannel high-speed serial bus transmitting terminal parallel port synchronization chip comprises the multichannel high-speed serial bus transmitting terminal parallel port synchronization circuit.
The method and the circuit solve the problem of synchronization of the parallel port of the sending end in the high-speed serial bus, and have the following advantages:
1) meanwhile, the problems of parallel port synchronization and clock domain crossing are solved, the use of a buffer is avoided, and the resource overhead and the link delay are reduced;
2) the system layer implementation method is simple and convenient, the cost is low, and only a plurality of AND gate logics and latches are provided;
3) in the actual working process, the phase relation between clocks is automatically adjusted, and the system is not influenced by voltage, temperature and process deviation.
Drawings
FIG. 1 is a flow chart of a method for synchronizing parallel ports of a transmitting end of a multi-channel high-speed serial bus according to the invention;
FIG. 2 is a schematic diagram of a parallel port synchronization circuit of a multi-channel high-speed serial bus transmitting terminal according to the present invention;
FIG. 3 is a timing diagram of the synchronization of the parallel ports of the multi-channel high-speed serial bus transmitting end.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1, a method for synchronizing parallel ports of a multi-channel high-speed serial bus transmitting end includes the following steps:
s1, locking by a phase-locked loop, generating a local high-speed clock, and connecting each transmitting end transmission channel;
s2, selecting one channel output clock from the output clocks of each transmitting end transmission channel as a system master clock, transmitting the system master clock to each transmitting end transmission channel, and sending parallel data;
s3, selecting each transmitting end transmission channel to be transmitted, initializing a clock after each selected transmitting end transmission channel detects that a phase-locked loop is locked, resetting a frequency divider, and transmitting a clock preparation signal;
s4, performing AND operation on each clock preparation signal sent by each sending end transmission channel to obtain a fully-reset clock preparation signal, sampling the fully-reset clock preparation signal by a system master clock to obtain a synchronization enabling signal in a system master clock domain, and sending the synchronization enabling signal to each selected sending end transmission channel;
s5, the selected transmission channels of each sending end use the synchronous enabling signal as the adjusting signal of the clock generated by the frequency divider, start the frequency divider, generate the frequency dividing clock as the output clock of the transmission channels of each sending end, namely, each channel generates the synchronous parallel clock;
s6, comparing the phase difference value of the system main clock and the output clock of the channel;
and S7, when the phase difference value is larger than or smaller than the threshold value, adjusting the phase of the output clock to keep the system main clock and the output clock to keep a fixed phase difference and achieve clock synchronization.
In this embodiment, a specific method for comparing the phase difference value between the system main clock and the output clock of the channel is to perform phase discrimination by using a phase discriminator, compare the phase difference, and record the specific phase difference value.
In this embodiment, the number of transmission channels at the transmitting end may be 1 to n, where n > is 2;
in this embodiment, a system master clock is transmitted to frequency dividers of transmission channels of each transmitting end through a D flip-flop, and the system master clock is used for transmitting parallel data, sampling a clock preparation signal, and sampling a phase difference value in system parallel-to-serial conversion, and controls a signal timing sequence in a system master clock domain.
In this embodiment, the phase-locked loop is connected to the frequency divider of each transmission channel of the transmitting end, when the phase-locked loop is locked, a local high-speed clock signal is generated, and each transmission channel of the transmitting end detects that the phase-locked loop is locked, performs clock initialization on each module of the channel, and resets the frequency divider.
In this embodiment, each transmitting end transmission channel to be subjected to data transmission is selected, when a phase-locked loop is locked, a parallel-serial conversion unit of each selected transmitting end transmission channel respectively sends out a clock preparation signal, and sends each clock preparation signal to an and gate for and operation. The synchronization enable signal is transmitted to the parallel-to-serial converter in the transmission channel, and the parallel-to-serial converter starts operating.
In this embodiment, the frequency divider starts the frequency divider according to the synchronization enable signal, performs frequency division based on the local high-speed clock to generate a frequency-divided clock as an output clock of the transmission channel of the transmitting end, where the output clock of the transmission channel of the transmitting end is used to receive serial-to-parallel converted serial data, and the frequency divider is connected to the phase comparator and the phase controller;
in this embodiment, as shown in fig. 3, since the synchronization enable signal is obtained by sampling the system master clock, and the output clock signal generated by the frequency divider is generated by the synchronization enable signal, based on the local high-speed clock frequency division, firstly, frequency division is performed for 3 times and 2 times on the basis of the local high-speed clock frequency division, that is, a frequency division 8 signal equivalent to the local high-speed clock is used as the output clock signal of the transmitting end channel, the output clock signal and the system master clock signal have a fixed phase interval, and meanwhile, due to the metastable state, the synchronization enable signal is delayed for 2-3 high-speed clock cycles in the master clock domain, so that a fixed interval of 1-3 high-speed clock cycles exists between the rising edge of the output clock signal and the falling edge of the master clock signal, the fixed interval is usually between several hundred picoseconds and one-two nanoseconds, such an interval can ensure that the parallel data of the system can be directly received by the output clock of the channel when being transmitted to the channel, the optimal setup time and hold time are reserved, the problem of clock domain crossing is solved, and the fixed interval can be set to be 3-4 high-speed clock cycles.
In this embodiment, the specific method for comparing the phase difference value between the system main clock and the output clock of the channel includes performing phase discrimination by using a phase discriminator, comparing the phase difference, and recording the specific phase difference value by using a phase counter.
In this embodiment, the circuit providing the phase comparator for comparing the phases of the output clock of the channel and the system master clock includes a phase detector and a phase counter. The method comprises the following steps: and performing phase discrimination through a JK trigger, and comparing the actual phase difference value of the rising edge of the output clock of the channel and the falling edge of the main clock of the system. Other linear phase detectors, such as Hogge phase detectors, may be used to implement this function. The phase difference value is counted by a phase counter and the specific phase difference value is recorded, i.e. the actual duration of the phase difference between the two clocks is measured. For the low-power-consumption design of the circuit, the phase counter is set to be of a two-bit structure, the phase counter is saturated after counting to 3, errors are prevented from being caused after overflowing, and the count value is between 0 and 3. In a system with lower power consumption requirement, the counter can be given more bit width, and the adjustment precision is improved. The counting result is sampled by the system master clock to obtain a phase difference value. When the phase difference is less than or equal to 2, the rising edge of the output clock of the channel is considered to be very close to the rising edge of the system main clock, and the margin for the holding time is very small. The generated phase difference value is sent to a phase controller to control the phase of the phase-locked loop high-speed clock, and then the phase of the output clock of the frequency-divided channel is adjusted. The control rule of the phase controller is as follows:
when the phase difference is greater than 2, the output clock phase of the channel is kept unchanged.
And when the phase difference value is less than or equal to 2, the phase of the output clock of the channel is shifted backwards, so that the system main clock and the output clock of the channel are kept in 3-4 clock cycles.
In this embodiment, if the output clock of the channel is very high, that is, the frequency division system of the frequency divider is relatively small, as shown in fig. 3, for the frequency division 2 signal based on the local high-speed clock, the rising edge of the output clock of the channel is ahead of the falling edge of the system main clock, which may cause a clock domain crossing problem, so that the data is not ready in time and is received according to the output clock, and at this time, the data is also disturbed. In this case, a phase comparison module is additionally added, which compares the phase difference between the rising edge of the output clock and the falling edge of the system main clock, and when the phase difference is positive, that is, when the output clock of the channel is found to be advanced, the phase control module can be controlled to shift the phase of the output clock backward.
As shown in fig. 2, a multi-channel high-speed serial bus transmitter parallel port synchronization circuit includes:
the device comprises a phase-locked loop, a clock signal selection unit, a plurality of transmitting end transmission channels and a synchronous enabling generation unit; the transmission channel at the transmitting end also comprises a frequency divider, a phase comparator, a phase controller and a parallel-serial data converter,
in this embodiment, the number of the transmission channels at the sending end may be 1 to n, where n > is 2, and in this embodiment, a channel 0, a channel 1, a channel 2, and a channel 3 are given, and a specific implementation scheme is shown as a channel 1. The output clock generated by the frequency divider in each transmitting end transmission channel is connected to the clock signal selection unit;
the clock signal selection unit selects one output clock signal from the output clocks of a plurality of transmitting end transmission channels as a system main clock to be transmitted to each transmitting end transmission channel,
in this embodiment, the system master clock generated by the clock signal selection unit is transmitted to the frequency dividers of the respective transmission channels, and is also used for sending parallel data, sampling a fully-reset clock preparation signal, sampling a phase difference value of the phase comparator, and controlling a signal timing sequence in the system master clock domain.
The phase-locked loop is used for generating a local high-speed clock signal, the phase-locked loop is connected with a plurality of transmitting end transmission channels, the transmitting end transmission channels are used for carrying out clock initialization on each module of the transmitting end transmission channels when the phase-locked loop is detected to be locked, resetting the frequency divider and sending a clock preparation signal to the synchronization enabling generation unit, specifically, the phase-locked loop is connected with the parallel-serial data converter and the frequency divider of each transmission channel, and when the phase-locked loop is detected to be locked by each transmission channel, carrying out clock initialization on each module of the channel and resetting the frequency divider;
the parallel-serial data converter of the transmission channel is used for converting data of a system parallel port into serial data and transmitting the serial data in a high-speed serial line, namely converting multi-bit parallel data into a plurality of 1-bit serial data for single-bit transmission, and receiving the converted serial data by using an output clock generated by the transmission channel at a transmitting end;
in this embodiment, the parallel-to-serial data converters are further configured to send out the clock preparation signals respectively from the parallel-to-serial data converters of the selected transmission channels when the phase-locked loop is locked.
In this embodiment, the synchronization enable generating unit receives the clock preparation signals of each channel to perform an and operation, and the generated clock preparation signals also have a certain delay due to different clock initialization times of each transmission channel, and generate a full-reset clock preparation signal through the and operation, so that it is ensured that each selected transmission channel is reset by the frequency divider through the full-reset clock preparation signal, i.e., the clock initialization is completed, and the full-reset clock preparation signal is sampled by the system master clock, and generates a synchronization enable signal in the system master clock domain to be transmitted to each transmission channel. The synchronization enable signal is transmitted to the parallel-to-serial converter in the transmission channel, and the parallel-to-serial converter starts operating.
The frequency divider of the transmission channel of the sending end starts the frequency divider according to the synchronous enabling signal generated by the synchronous enabling generation unit, and the frequency divider divides frequency based on a local high-speed clock to generate a frequency division clock as an output clock of the transmission channel of the sending end;
in this embodiment, the frequency divider starts the frequency divider according to the synchronization enable signal, which uses the synchronization enable signal as an adjustment signal for the frequency divider to generate a clock, divides the frequency by using a local high-speed clock, generates a frequency-divided clock as an output clock of the transmission channel at the transmitting end, and is connected to the phase comparator and the phase controller;
in this embodiment, as shown in fig. 3, since the synchronization enable signal is obtained by sampling the system master clock, and the output clock signal generated by the frequency divider is generated by the synchronization enable signal, based on the local high-speed clock frequency division, firstly, frequency division is performed for 3 times and 2 times on the basis of the local high-speed clock frequency division, that is, a frequency division 8 signal equivalent to the local high-speed clock is used as the output clock signal of the transmitting end channel, the output clock signal and the system master clock signal have a fixed phase interval, and meanwhile, due to the metastable state, the synchronization enable signal is delayed for 2-3 high-speed clock cycles in the master clock domain, so that a fixed interval of 1-3 high-speed clock cycles exists between the rising edge of the output clock signal and the falling edge of the master clock signal, the fixed interval is usually between several hundred picoseconds and one-two nanoseconds, such an interval can ensure that the parallel data of the system can be directly received by the output clock of the channel when being transmitted to the channel, the optimal setup time and hold time are reserved, the problem of clock domain crossing is solved, and the fixed interval can be set to be 3 high-speed clock cycles.
The phase comparator of the transmission channel at the sending end receives the output clock information and the system main clock signal generated by the frequency divider, is connected with the phase controller and is used for comparing the phase difference value of the system main clock and the output clock of the channel;
the phase controller of the transmission channel at the sending end is connected with the frequency divider, the phase comparator and the phase-locked loop and used for adjusting the local high-speed clock phase of the phase-locked loop when the phase difference value is larger than or smaller than a threshold value, so that the output clock phase after frequency division by the frequency divider is adjusted;
in this embodiment, due to the influence of voltage, temperature, and process deviation, in the actual working process of the system, the fixed phase interval between the output clock and the system master clock may change, and the problem of clock domain crossing may occur when the interval is short or long, and the problem of synchronization of the clock domain crossing port may be influenced because data cannot be normally received by the output clock of the channel. In order to solve the problem, a phase comparison module is implemented in each channel, the phase difference between the output clock and the system main clock is compared in real time, the change value of the phase difference is judged, when the change value of the phase difference is larger than or smaller than a certain threshold value, the phase of the output clock is automatically adjusted in the channel, the change of the phase interval between the rising edge of the output clock and the falling edge of the system main clock is kept within 1 high-speed clock cycle, and if the fixed interval is set to be 3 high-speed clock cycles, the phase interval between the rising edge of the output clock and the falling edge of the system main clock is kept within 4 high-speed clock cycles in actual work. The phase comparison module can continuously monitor the phase relationship of the two clocks when the system works, and when the phase difference between the two clocks is changed by more than 1 high-speed clock period, the channel can automatically adjust the phase of the output clock so as to maintain the stable operation of the system.
In this embodiment, a phase comparator for comparing the phases of the output clock of a channel and the system master clock in the channel is provided, which includes a phase detector and a phase counter. The method comprises the following steps: and performing phase discrimination through a JK trigger, and comparing the actual phase difference value of the rising edge of the output clock of the channel and the falling edge of the main clock of the system. Other linear phase detectors, such as Hogge phase detectors, may be used to implement this function. The phase difference value is counted by a phase counter and the specific phase difference value is recorded, i.e. the actual duration of the phase difference between the two clocks is measured. For the low-power-consumption design of the circuit, the phase counter is set to be of a two-bit structure, the phase counter is saturated after counting to 3, errors are prevented from being caused after overflowing, and the count value is between 0 and 3. In a system with lower power consumption requirement, the counter can be given more bit width, and the adjustment precision is improved. The counting result is sampled by the system master clock to obtain a phase difference value. When the phase difference is less than or equal to 2, the rising edge of the output clock of the channel is considered to be very close to the rising edge of the system main clock, and the margin for the holding time is very small. The generated phase difference value is sent to a phase controller to control the phase of the phase-locked loop high-speed clock, and then the phase of the output clock of the frequency-divided channel is adjusted. The phase controller is a clock that an analog circuit can generate various phases by four-phase clocks, including PLLCLK 0 °, PLLCLK 90 °, PLLCLK180 °, PLLCLK 270 ° phases. The control rule of the phase controller is as follows:
when the phase difference is greater than 2, the output clock phase of the channel is kept unchanged.
And when the phase difference value is less than or equal to 2, the phase of the output clock of the channel is shifted backwards, so that the system main clock and the output clock of the channel are kept in 3-4 clock cycles.
In this embodiment, if the output clock of the channel is very high, that is, the frequency division system of the frequency divider is relatively small, as shown in fig. 3, for the frequency division 2 signal based on the local high-speed clock, the rising edge of the output clock of the channel is ahead of the falling edge of the system main clock, which may cause a clock domain crossing problem, so that the data is not ready in time and is received according to the output clock, and at this time, the data is also disturbed. In this case, a phase comparison module is additionally added, which compares the phase difference between the rising edge of the output clock and the falling edge of the system main clock, and when the phase difference is positive, that is, when the output clock of the channel is found to be advanced, the phase control module can be controlled to shift the phase of the output clock backward.
It will be appreciated by those skilled in the art that the method and system of the present invention are not limited to the embodiments described in the detailed description, which is for the purpose of explanation and not limitation. Other embodiments will be apparent to those skilled in the art from the following detailed description, which is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method for synchronizing parallel ports of a multi-channel high-speed serial bus sending end is characterized by comprising the following steps:
s1, locking by a phase-locked loop to generate a local high-speed clock;
s2, selecting one output clock from the output clocks of each transmitting end transmission channel as a system master clock, and transmitting the system master clock to each transmitting end transmission channel;
s3, selecting each transmitting end transmission channel to be subjected to information transmission, and when each selected transmitting end transmission channel detects that a phase-locked loop is locked, performing clock initialization and transmitting a clock preparation signal;
s4, performing AND operation on each clock preparation signal sent by each sending end transmission channel to obtain a fully-reset clock preparation signal, sampling the fully-reset clock preparation signal by a system master clock to obtain a synchronization enabling signal in a system master clock domain, and sending the synchronization enabling signal to each selected sending end transmission channel;
s5, the selected transmission channels of each sending end use the synchronous enabling signal as the adjusting signal of the clock generated by the frequency divider, start the frequency divider, generate the frequency dividing clock as the output clock of the transmission channels of each sending end;
s6, comparing the phase difference between the system main clock and the output clock of the transmission channel of the sending end;
and S7, when the phase difference value is larger than or smaller than the threshold value, adjusting the phase of the output clock to keep the system main clock and the output clock to keep a fixed phase difference and achieve clock synchronization.
2. The method for synchronizing the parallel ports of the transmitting end of the multi-channel high-speed serial bus according to claim 1, wherein the method comprises the following steps: the specific method for comparing the phase difference value between the main clock of the system and the output clock of the sending end channel comprises the steps of phase discrimination through a phase discriminator, phase difference comparison, and recording of the specific phase difference value through a counter.
3. The method for synchronizing the parallel ports of the transmitting end of the multi-channel high-speed serial bus according to claim 2, wherein the method comprises the following steps: the phase detector is a JK trigger or a Hogge phase detector.
4. The method for synchronizing the parallel ports of the transmitting end of the multi-channel high-speed serial bus according to claim 1, wherein the method comprises the following steps: the specific method for adjusting the phase of the output clock is to keep the phase difference value between 3-4 local high-speed clock cycles, and when the phase difference value is larger than 2, keep the phase of the output clock of a transmission channel of a sending end still; and when the phase difference value is less than or equal to 2, the phase of the output clock of the transmission channel of the sending end is shifted backwards.
5. A multichannel high-speed serial bus sending end parallel port synchronous circuit is characterized by comprising: the device comprises a phase-locked loop, a clock signal selection unit, a plurality of transmitting end transmission channels and a synchronous enabling generation unit; the transmission channel at the transmitting end also comprises a frequency divider, a phase comparator, a phase controller and a parallel-serial data converter;
the phase-locked loop is used for generating a local high-speed clock signal and is connected with a plurality of transmitting end transmission channels;
the clock signal selection unit is used for selecting one output clock signal from the output clocks of the plurality of transmitting end transmission channels as a system main clock to be transmitted to each transmitting end transmission channel;
the transmitting end transmission channel is used for carrying out clock initialization on the transmitting end transmission channel when the phase-locked loop is detected to be locked, and transmitting a clock preparation signal to the synchronization enabling generation unit;
the synchronous enabling generation unit is used for performing AND operation on the clock preparation signals sent by the selected channels to obtain fully-reset clock preparation signals, and performing system master clock sampling on the fully-reset clock preparation signals to obtain synchronous enabling signals in a system master clock domain;
the parallel-serial data converter of the transmission channel of the sending end is used for converting data of a parallel port of a system into serial data to be transmitted in the channel;
the frequency divider of the transmission channel of the sending end is started according to the synchronous enabling signal, frequency division is carried out based on a local high-speed clock, and a frequency division clock is generated to be used as an output clock of the transmission channel of the sending end;
the phase comparator of the transmission channel at the transmitting end receives the output clock and the system main clock generated by the frequency divider, is connected with the phase controller and is used for comparing the phase difference value of the system main clock and the output clock of the transmission channel at the transmitting end;
and the phase controller of the transmission channel at the transmitting end is connected with the frequency divider, the phase comparator and the phase-locked loop and used for adjusting the local high-speed clock phase of the phase-locked loop when the phase difference value is greater than or less than a threshold value so as to adjust the output clock phase.
6. The multi-channel high-speed serial bus sender parallel port synchronization circuit of claim 5, wherein: the phase comparator comprises a phase discriminator and a two-bit phase counter, phase discrimination is carried out through the phase discriminator, phase difference is compared, and a specific phase difference value is recorded through the two-bit phase counter.
7. The multi-channel high-speed serial bus sender parallel port synchronization circuit of claim 6, wherein: the phase detector is a JK trigger or a Hogge phase detector.
8. The multi-channel high-speed serial bus sender parallel port synchronization circuit of claim 5, wherein: the specific method for adjusting the phase of the output clock by the phase controller is that the phase difference value is kept between 3-4 local high-speed clock cycles, and when the phase difference value is larger than 2, the phase of the output clock of a transmission channel of a sending end is kept unchanged; and when the phase difference value is less than or equal to 2, the phase of the output clock of the transmission channel of the sending end is shifted backwards.
9. A multi-channel high-speed serial bus sender parallel port synchronization chip, characterized in that it is arranged to comprise a multi-channel high-speed serial bus sender parallel port synchronization circuit according to any of claims 5-8.
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| CN111355484B (en) | 2018-12-20 | 2023-09-05 | 深圳市中兴微电子技术有限公司 | Device and method for realizing data synchronization |
| CN112840571B (en) * | 2018-12-29 | 2024-04-23 | 华为技术有限公司 | Cross-clock domain processing circuit |
| CN111626011B (en) * | 2020-04-20 | 2023-07-07 | 芯创智(上海)微电子有限公司 | FPGA comprehensive rapid iteration method and system based on configurable breakpoint restart |
| CN119182738B (en) * | 2024-11-26 | 2025-02-28 | 无锡芯领域微电子有限公司 | A dynamic adaptation method and system for PCIE switch port WRR phase table |
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