CN108431978A - Monolithic 3D memory array formed using sacrificial polysilicon pillars - Google Patents

Abstract

Methods of forming monolithic three-dimensional memory arrays are provided. The method includes forming a first vertically oriented polysilicon column over a substrate, the first vertically oriented polysilicon column surrounded by a dielectric material, removing the first vertically oriented polysilicon column to form a first void in the dielectric material , and fill the first gap with a conductive material to form a first through hole.

Description

Monolithic 3D memory array formed using sacrificial polysilicon pillars

Background technique

Semiconductor memory is widely used in various electronic devices such as mobile computing devices, mobile phones, solid state drives, electronic cameras, personal digital assistants, medical electronics, servers, and non-mobile computing devices. Semiconductor memory may include nonvolatile memory or volatile memory. Non-volatile memory allows information to be stored or retained even when the non-volatile memory device is not connected to a power source, such as a battery.

Examples of non-volatile memory include flash memory (such as NAND-type and NOR-type flash memory), electrically erasable programmable read-only memory (EEPROM), ferroelectric memory (such as FeRAM), magnetoresistive memory (such as MRAM ) and phase-change memory (such as PRAM). In recent years, nonvolatile memory devices have been scaled in order to reduce the cost per bit. However, as process geometries shrink, many design and process challenges arise. These challenges include increasing variability in memory cell I-V characteristics, reducing memory cell sense current, and increasing bit line settlement times.

Description of drawings

Figure 1A depicts an embodiment of a memory system and host.

Figure IB depicts an embodiment of a memory core control circuit.

Figure 1C depicts an embodiment of a memory core.

Figure ID depicts an embodiment of a memory bay.

Figure IE depicts an embodiment of a memory block.

Figure IF depicts another embodiment of a memory bay.

Figure 2A depicts a schematic diagram of the memory carrier of Figure IF.

Figure 2B depicts a schematic diagram of a memory bay arrangement in which word lines and bit lines are shared across memory blocks and both row and column decoders are separate.

Figure 3A depicts an embodiment of a portion of a monolithic three-dimensional memory array.

3B depicts a subset of memory arrays and layout layers of an example of a three-dimensional memory array.

3C-3D depict various embodiments of cross-point memory arrays.

Figure 4A depicts an embodiment of a portion of a monolithic three-dimensional memory array.

Figure 4B depicts an embodiment of a portion of a monolithic three-dimensional memory array comprising vertical strips of non-volatile memory material.

5A-5D depict various views of an embodiment monolithic three-dimensional memory array.

6A-6L2 are cross-sectional views of portions of the substrate during exemplary fabrication of the monolithic three-dimensional memory array of FIGS. 5A-5D .

Detailed ways

Techniques for monolithic three-dimensional memory arrays are described. In particular, conductive vias are formed by using sacrificial polysilicon pillars. In particular, sacrificial vertically oriented polysilicon pillars are formed while forming vertically oriented polysilicon pillars that will function as vertically oriented bit line select transistors. The sacrificial vertically oriented polysilicon pillars are removed to form voids. A conductive material is deposited over the pores to form vias. Vias may be used to form vertical conductive connections between material layers of a monolithic three-dimensional memory array.

For example, a row selection line may comprise a first portion and a second portion, wherein the first portion of the row selection line is separated by a distance from the second portion of the row selection line. In an embodiment, a word line hookup region separates a first portion of the row select line from a second portion of the row select line. Vias, such as though using sacrificial vertically oriented polysilicon pillars as described above, may be used to electrically couple the first portion of the row select line to the second portion of the row select line.

In some embodiments, the memory array may comprise a cross-point memory array. A cross-point memory array may refer to a memory array in which two-terminal memory cells are placed at the intersection of a first set of control lines (such as word lines) arranged in a first direction and a second set of control lines (such as bit lines) , the second set is arranged in a second direction perpendicular to the first direction. Two-terminal memory cells may contain impedance-switching materials such as phase change materials, ferroelectric materials, or metal oxides such as nickel oxide or hafnium oxide. In some cases, each memory cell in a cross-point memory array can be placed in series with a steering element or an isolation element, such as a diode, to reduce leakage current. Especially because leakage current can vary widely over bias voltage and temperature, controlling and minimizing leakage current can be an important issue in cross-point memory arrays where the memory cells do not contain isolation elements.

In one embodiment, a non-volatile storage system may contain one or more two-dimensional arrays of non-volatile memory cells. Memory cells within a two-dimensional memory array may form a single layer of memory cells and may be via control lines (eg, word lines and bit lines) selected in the X and Y directions. In another embodiment, a non-volatile storage system may comprise one or more monolithic three-dimensional memory arrays, where two or more layers of memory cells may be formed over a single substrate without any intervening the substrate. In some cases, a three-dimensional memory array can include one or more vertical columns of memory cells above and orthogonal to a substrate. In one example, a non-volatile storage system may include a memory array having bit lines or bit lines arranged orthogonally to a semiconductor substrate. The substrate may include a silicon substrate. The memory array may comprise rewritable non-volatile memory cells, wherein each memory cell comprises a reversible resistance-switching element without an isolation element in series with the reversible resistance-switching element (e.g., no diode in series with the reversible resistance-switching element) .

In some embodiments, a nonvolatile storage system may include nonvolatile memory monolithically formed in one or more physical levels of an array of memory cells that The level has an active area disposed over a silicon substrate. The non-volatile storage system may also include circuitry associated with the operation of the memory cells (eg, decoders, state machines, page registers, or control circuitry to control the reading or programming of the memory cells). Circuitry associated with the operation of the memory cells may be located above the substrate or within the substrate.

In some embodiments, a non-volatile storage system may include a monolithic three-dimensional memory array. A monolithic three-dimensional memory array may contain one or more levels of memory cells. Each memory cell within a first level of the one or more levels of memory cells may include an active region over a substrate (eg, over a single crystal substrate or a single crystal silicon substrate). In one example, the active region may contain a semiconductor junction (eg, a PN junction). The active region may comprise part of the source or drain region of the transistor. In another example, the active region may contain a channel region of a transistor.

FIG. 1A depicts one embodiment of a memory system 100 and a host 102 . The memory system 100 may include a non-volatile storage system that interfaces with a host 102 (eg, a mobile computing device). In some cases, memory system 100 may be embedded within host 102 . In other cases, memory system 100 may include memory cards. As depicted, memory system 100 includes memory chip controller 104 and memory chip 106 . Although a single memory chip 106 is depicted, the memory system 100 may contain more than one memory chip (eg, four, eight, or other numbers of memory chips). The memory chip controller 104 can receive data and commands from the host 102 and provide memory chip data to the host 102 .

Memory chip controller 104 may contain one or more state machines, page registers, SRAM, and control circuitry that control the operation of memory chip 106 . The one or more state machines, page registers, SRAM, and control circuits that control the operation of memory chip 106 may be referred to as management or control circuits. Management or control circuitry may cause one or more memory array operations such as form, erase, program, or read operations.

In some embodiments, management or control circuitry (or portions of management or control circuitry) that facilitates operation of one or more memory arrays may be integrated in memory chip 106 . Memory chip controller 104 and memory chip 106 may be arranged on a single integrated circuit. In other embodiments, memory chip controller 104 and memory chip 106 may be disposed on different integrated circuits. In some cases, memory chip controller 104 and memory chip 106 may be integrated on a system board, logic board, or PCB.

Memory chip 106 includes memory core control circuitry 108 and memory core 110 . Memory core control circuitry 108 may contain logic to control the selection of memory blocks (or arrays) within memory core 110, to control the generation of voltage references to bias a particular memory array into a read or write state, or to generate row address and column address.

Memory core 110 may contain one or more two-dimensional arrays of memory cells or one or more three-dimensional arrays of memory cells. In one embodiment, memory core control circuitry 108 and memory core 110 are arranged on a single integrated circuit. In other embodiments, memory core control circuitry 108 (or portions of memory core control circuitry 108 ) and memory core 110 may be disposed on different integrated circuits.

Memory operations may be initiated when the host 102 sends an instruction to the memory chip controller 104 indicating that the host 102 is about to read data from or write data to the memory system 100 . In the event of a write (or program) operation, the host 102 will send both a write command and the data to be written to the memory chip controller 104 . Data to be written may be buffered by the memory chip controller 104, and an error correction code (ECC) may be generated corresponding to the data to be written. ECC data (which allows data to be detected and/or corrected during transmission or storage) may be written to memory core 110 or stored in non-volatile memory within memory chip controller 104 . In one embodiment, ECC data may be generated and data errors corrected by circuitry within the memory chip controller 104 .

The memory chip controller 104 controls the operation of the memory chip 106 . In one example, before issuing a write operation to memory chip 106, memory chip controller 104 may check a status register to ensure that memory chip 106 is able to accept the data to be written. In another example, prior to issuing a read operation to the memory chip 106, the memory chip controller 104 may pre-read overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within the memory chip 106 where the requested data is to be read. Once a read or write operation is initiated by memory chip controller 104, memory core control circuitry 108 may generate appropriate bias voltages for word and bit lines within memory core 110, and generate appropriate memory block, row, and column addresses.

In some embodiments, one or more management or control circuits may be used to control the operation of the memory array. One or more management or control circuits may provide control signals to the memory array to perform read operations and/or write operations on the memory array. In one example, the one or more management or control circuits may comprise any one or combination of the following: control circuits, state machines, decoders, sense amplifiers, read/write circuits, and/or controllers. One or more management or control circuits may conduct or facilitate one or more memory array operations including erase, program or read operations. In one example, one or more management circuits may include an on-chip memory controller to determine row and column addresses, word line and bit line addresses, memory array enable signals, and data latch signals.

FIG. 1B depicts one embodiment of memory core control circuitry 108 . As depicted, the memory core control circuitry 108 includes (as described in detail below) an address decoder 120, a voltage generator 122 for selected control lines, a voltage generator 124 for unselected control lines, and a signal generator for reference signals. device 126. The control lines may comprise word lines, bit lines, or a combination of word lines and bit lines. The selected control lines may include selected word lines and/or selected bit lines, which are used to place the memory cells into the selected state. Unselected control lines may include unselected word lines and/or unselected bit lines, which are used to place memory cells into an unselected state.

Address decoder 120 may generate memory block addresses, as well as row and column addresses for a particular memory block. The selected control line voltage generator (or voltage regulator) 122 may include one or more voltage generators that generate the selected control line voltage. The voltage generators for unselected control lines 124 may include one or more voltage generators that generate unselected control line voltages. The signal generator 126 for the reference signal may include one or more voltage generators for generating a reference voltage and/or one or more current generators for generating a reference current.

1C-1F depict an embodiment of a memory core organization including a memory core with multiple memory bays, and each memory bay has multiple memory blocks. Although a memory core organization is disclosed where memory bays contain memory blocks and memory blocks contain groups of memory cells, other organizations or groupings may also be used with the techniques described herein.

Figure 1C depicts one embodiment of the memory core 110 of Figure 1A. As depicted, memory core 110 includes memory bay 130 and memory bay 132 . In some embodiments, the number of memory trays per memory core may vary for different implementations. For example, a memory core may contain only a single memory bay or multiple memory bays (eg, 16 or other number of memory bays).

Figure ID depicts one embodiment of memory bay 130 in Figure 1C. As depicted, memory bay 130 includes memory blocks 140 - 144 and read/write circuitry 146 . In some embodiments, the number of memory blocks per memory bay may vary for different implementations. For example, a memory bay may contain one or more memory blocks (eg, 32 per memory bay or other number of memory blocks). Read/write circuitry 146 includes circuitry to read and write memory cells within memory blocks 140-144.

As depicted, read/write circuitry 146 may be shared across multiple memory blocks within a memory bay. This allows chip area to be reduced since a single set of read/write circuits 146 can be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to read/write circuitry 146 at a particular time to avoid signal conflicts.

In some embodiments, read/write circuitry 146 may be used to write one or more pages of data into memory blocks 140-144 (or into a subset of memory blocks). Memory cells within memory blocks 140-144 may allow direct rewriting of pages (i.e., data representing a page or portion of a page may be written into memory blocks 140-144 without requiring an erase on the memory cells prior to writing the data. delete or reset operation).

In one example, memory system 100 in FIG. 1A may receive a write command that includes a target address and a set of data to be written to the target address. Memory system 100 may perform a read before write (RBW) operation to read data currently stored at a target address and/or to obtain overhead information (e.g., ECC information).

In some cases, read/write circuitry 146 may be used to program a particular memory cell in one of three or more data/resistance states (ie, a particular memory cell may comprise a multi-level memory cell). In one example, read/write circuitry 146 may apply a first voltage difference (e.g., 2V) across a particular memory cell to program the particular memory cell to a first of three or more data/resistance states, Alternatively, a second voltage difference (eg, 1 V) is applied across the particular memory cell that is less than the first voltage difference to program the particular memory cell to a second state of the three or higher plurality of data/resistance states.

Applying a smaller voltage difference across a particular memory cell can cause the particular memory cell to be partially programmed or programmed at a lower rate than when a larger voltage difference is applied. In another example, read/write circuit 146 may apply a first voltage difference across a particular memory cell for a first period of time (eg, 150 ns) to program the particular memory cell to three or more data/resistance In a first of the states, either the first voltage difference across the particular memory cell is applied for a second period of time (eg, 50 ns) that is less than the first period of time. Following the memory cell verification phase, one or more programming pulses may be used to program the particular memory cell in the correct state.

Figure IE depicts one embodiment of memory block 140 in Figure ID. As depicted, memory block 140 includes memory array 150 , row decoder 152 and column decoder 154 . Memory array 150 may contain contiguous groups of memory cells having contiguous word lines and bit lines. Memory array 150 may contain one or more layers of memory cells. Memory array 150 may comprise a two-dimensional memory array or a three-dimensional memory array.

At the appropriate time (eg, when reading or writing a memory cell in memory array 150 ), row decoder 152 decodes the row address and selects a particular word line in memory array 150 . Column decoder 154 decodes the column address and selects one or more bit lines in memory array 150 for electrical coupling to read/write circuitry, such as read/write circuitry 146 in FIG. 1D . In one embodiment, the number of word lines is 4K per memory layer, the number of bit lines is 1K per memory layer, and the number of memory layers is 4 to provide a memory array 150 containing 16M memory cells.

One embodiment of memory bay 134 is depicted in FIG. 1F . Memory bay 134 is one example of an alternative implementation for memory bay 130 in FIG. 1D . In some embodiments, row decoders, column decoders, and read/write circuits can be split or shared between memory arrays. As depicted, because row decoder 152b controls word lines in both memory arrays 150a and 150b, row decoder 152b is shared between memory arrays 150a and 150b (i.e., word lines driven by row decoder 152b are shared). Wire).

Row decoders 152a and 152b may be separated such that even word lines in memory array 150a are driven by row decoder 152a and odd word lines in memory array 150a are driven by row decoder 152b. Row decoders 152c and 152b may be split such that even word lines in memory array 150b are driven by row decoder 152c and odd word lines in memory array 150b are driven by row decoder 152b.

Column decoders 154a and 154b may be separated such that even bit lines in memory array 150a are driven by column decoder 154b and odd bit lines in memory array 150a are driven by column decoder 154b. Column decoders 154c and 154d may be separated such that even bit lines in memory array 150b are driven by column decoder 154d and odd bit lines in memory array 150b are driven by column decoder 154c.

Selected bit lines controlled by column decoder 154a and column decoder 154c may be electrically coupled to read/write circuitry 146a. Selected bit lines controlled by column decoder 154b and column decoder 154d may be electrically coupled to read/write circuitry 146b. Separating the read/write circuitry into read/write circuits 146a and 146b may allow for a more efficient layout of the memory bays while separating the column decoders.

Figure 2A depicts one embodiment of a schematic diagram (including word lines and bit lines) corresponding to memory tray 134 in Figure IF. As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 150a and 150b and are controlled by row decoder 152 of FIG. 1F. Word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 150a and are controlled by row decoder 152a of FIG. 1F. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 150b and are controlled by row decoder 152c of FIG. 1F.

Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 150a and are controlled by row decoder 154b of FIG. 1F. Bit lines BL1, BL3, and BL5 are driven from the top of memory array 150a and are controlled by row decoder 154a of FIG. 1F. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 150b and are controlled by column decoder 154d of FIG. 1F. Bit lines BL8, BL10, and BL12 are driven from the top of memory array 150b and are controlled by column decoder 154c of FIG. 1F.

In one embodiment, memory arrays 150a and 150b may include memory layers oriented in a horizontal plane that is horizontal to the supporting substrate. In another embodiment, memory arrays 150a and 150b may include memory layers oriented in a vertical plane perpendicular to the supporting substrate (ie, the vertical plane is perpendicular to the supporting substrate).

Figure 2B depicts one embodiment of a schematic diagram (including word lines and bit lines) corresponding to a memory bay arrangement in which word lines and bit lines are shared across memory blocks and both row and column decoders are separate. Sharing word lines and/or bit lines helps reduce layout area because a single row decoder and/or column decoder can be used to support both memory arrays.

As depicted, word lines WL1, WL3, and WL5 are shared between memory arrays 150a and 150b, and word lines WL8, WL10, and WL12 are shared between memory arrays 150c and 150d. Bit lines BL1, BL3, and BL5 are shared between memory arrays 150a and 150c, and bit lines BL8, BL10, and BL12 are shared between memory arrays 150b and 150d.

The row decoders are split such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 150a and word lines WL1, WL3, and WL5 are driven from the right side of memory array 150a. Likewise, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 150c and word lines WL8, WL10, and WL12 are driven from the right side of memory array 150c.

The column decoders are split such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 150a and bit lines BL1, BL3, and BL5 are driven from the top of memory array 150a. Likewise, bit lines BL21, BL23, BL25, and BL27 are driven from the top of memory array 150d and bit lines BL8, BL10, and BL12 are driven from the bottom of memory array 150d. Separate row decoders and/or column decoders also help to alleviate layout constraints (eg row decoder pitch can be relieved by 2x because separate column decoders only need to drive every other bit line instead of every bit line).

FIG. 3A depicts one embodiment of a portion of a monolithic three-dimensional memory array 300 comprising a first memory level 302 and a second memory level 304 above the first memory level 302 . Memory array 300 is one example of an implementation of memory array 150 in FIG. 1E . The bit lines 306 and 308 are arranged in a first direction, and the word line 310 is arranged in a second direction perpendicular to the first direction. As described, the upper conductors of the first memory level 302 may be used as the lower conductors of the second memory level 304 . In memory arrays with additional memory array layers, there will be additional layers of corresponding bit lines and word lines.

Memory array 300 includes a plurality of memory cells 312 . The memory unit 312 may include a rewritable memory unit, and may include a nonvolatile memory unit or a volatile memory. With respect to first memory level 302 , a first portion of memory cells 312 is between and connected to bitline 306 and wordline 310 . With respect to second memory level 304 , a second portion of memory cells 312 is between bit line 308 and word line 310 and is connected to bit line 306 and word line 310 . In one embodiment, each memory cell 312 includes a steering element (eg, a diode) and a memory cell (ie, a state change element).

In one example, the diodes of the first memory level 302 may point upward as indicated by arrow A1 (e.g., have a p-region at the bottom of the diode), while the diodes of the second memory level 304 may point downward as indicated by arrow A2 Diodes are indicated (eg with n-region at the bottom of the diode) and vice versa. In another embodiment, each memory cell 312 contains only state change elements. The lack of diodes (or other steering elements) from memory cells can reduce process complexity and lower costs associated with fabricating memory arrays.

In one embodiment, memory cell 312 includes a rewritable non-volatile memory cell that includes a reversible resistance-switching element. A reversible resistance-switching element may comprise a reversible resistance-switching material that has a resistance that can be switched between two or more states. In one embodiment, the reversible resistance-switching material may comprise a metal oxide (eg, a binary metal oxide). The metal oxide may comprise nickel oxide, hafnium oxide or any other metal oxide material. In another embodiment, the reversible impedance-switching material may comprise a phase change material. The phase change material may contain chalcogenides. In some cases, the rewritable non-volatile memory cells may comprise resistive RAM (ReRAM) devices.

In another embodiment, memory cell 312 may include a conductive bridge memory element. Conductive bridge memory elements may also be referred to as programmable metallization cells. Conductive bridge memory elements can be used as state change elements based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may comprise two solid metal electrodes, one relatively inert (such as tungsten) and the other electrochemically active (such as silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions can increase to cause the programming threshold of the conductive bridge memory cells to decrease. Accordingly, conductive bridge memory elements can have a wide range of programming thresholds with temperature.

In one embodiment of a read operation, one of the word lines (ie, the selected word line) can be biased to the selected word line voltage (eg, 0V) in the read mode to read the Data in one of the memory cells 312. The sense amplifier can then be used to bias the selected bit line connected to the selected memory cell to the selected bit line voltage (eg 1.0V) in read mode. In some cases, to avoid sensing leakage current from many unselected word lines to the selected bit line, the unselected word lines may be biased to the same voltage as the selected bit line (eg, 1.0V). To avoid leakage current from many selected word lines to unselected bit lines, the unselected bit lines can be biased to the same voltage as the selected word lines (eg, 0V). However, biasing the unselected word lines to the same voltage as the selected bit line and biasing the unselected bit lines to the same voltage as the selected word line The selected bit line drives the unselected memory cells to place substantial voltage stress.

In an alternative read biasing scheme, both the unselected word line and the unselected bit line can be biased to a voltage intermediate between the selected word line voltage and the selected bit line voltage. Applying the same voltage to both unselected word lines and unselected bit lines can reduce voltage stress across unselected memory cells driven by the unselected word lines and unselected bit lines.

However, the reduced voltage stress comes at the expense of increased leakage current associated with selected word lines and selected bit lines. The selected bit line may be applied to the selected bit line before the selected word line voltage has been applied to the selected word line, and then the sense amplifier may sense an auto-zero amount of current through the selected memory bit line that can subtract the bit line current in the second current sensed when the selected word line voltage is applied to the selected word line. Leakage current can be subtracted using automatic zero current sensing.

In one embodiment of a write operation, the reversible resistance-switching material may be in an initial high-resistance state that is switchable to a low-resistance state upon application of a first voltage and/or current. Application of the second voltage and/or current may return the reversible resistance-switching material to a high resistance state. Alternatively, the reversible resistance-switching material may be in an initial low-resistance state that is switchable to a high-resistance state upon application of appropriate voltage(s) and/or current(s).

When used in a memory cell, one resistive state can represent binary data "0" and the other resistive state can represent binary data "1." In some cases, a memory cell may be considered to contain more than two data/resistance states (ie, a multi-level memory cell). In some cases, a write operation may be similar to a read operation, except with a larger voltage range across selected memory cells.

The process of switching the resistance of the reversible resistance-switching element from a high-resistance state to a low-resistance state may refer to setting the reversible resistance-switching element. The process of switching the resistance of the reversible resistance-switching element from a low-resistance state to a high-resistance state may refer to resetting the reversible resistance-switching element. The high resistance state may be associated with binary data "1" and the low resistance state may be associated with binary data "0". In other embodiments, set and reset operations and/or data encoding may be preserved. In some embodiments, the first time to set the resistance-switching element may need to be higher than normal programming voltage and may refer to a forming operation.

In one embodiment of a write operation, data can be written to multiple One of the storage units 312. A write circuit can be used to bias the bit line connected to the selected memory cell to the selected bit line voltage in the write mode (eg 0V).

In some cases, to prevent program disturb of unselected memory cells sharing a selected word line, the unselected bit lines may be biased such that a first voltage difference between the selected word line voltage and the unselected bit line voltage less than the first interference threshold. In some cases, to prevent program disturb of unselected memory cells sharing a selected word line, the unselected bit lines may be biased such that a first voltage difference between the selected word line voltage and the unselected bit line voltage less than the first interference threshold. The first disturb threshold and the second disturb threshold may be different depending on the amount of time that unselected memory cells susceptible to disturb are stressed.

In one write biasing scheme, both the unselected word line and the unselected bit line can be biased to a voltage intermediate between the selected word line voltage and the selected bit line voltage. The intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is greater than a second voltage difference across other unselected memory cells sharing a selected bit line. The reason for placing the first voltage difference across the unselected memory cells sharing the selected word line is that the memory cells sharing the selected word line can be verified directly after the write operation to detect write disturb.

Figure 3B depicts a subset of the memory array and wiring layers of one embodiment of a three-dimensional memory array, such as memory array 150 of Figure IE. As depicted, a memory array layer is placed over the substrate. The memory array layers include bit line layers BL0, BL1 and BL2, and word line layers WL0 and WL1. In other embodiments, additional bitline and wordline layers may also be implemented. Support circuits such as row decoders, column decoders, and read/write circuits may be disposed on the surface of the substrate with the memory array layer fabricated above the support circuits.

An integrated circuit implementing a three-dimensional memory array may also contain multiple metal layers for routing signals between different components of the support circuitry, and between the support circuitry and the bit lines and word lines of the memory array. These wiring layers may be arranged over support circuitry implemented on the surface of the substrate and below the memory array layer.

As depicted in FIG. 3B, two metal layers R1 and R2 are used for wiring layers. However, other embodiments may include more or less than two metal layers. In one example, the metal layers R1 and R2 are composed of tungsten (approximately 1 ohm/square). Positioned above the memory array layer may be one or more top metal layers, such as a top metal layer, for routing signals between different components of the integrated circuit. In one example, the top metal layer is composed of copper or aluminum (approximately 0.5 ohms/square), which can provide a lower resistance per unit area than metal layers R1 and R2. In some cases, metal layers R1 and R2 may not be implemented using the same materials as those used for the top metal layer, because the material used for R1 and R2 must be able to withstand the process of fabricating the memory array layer on top of R1 and R2 step.

FIG. 3C depicts one embodiment of a cross-point memory array 360 . Cross-point memory array 360 may correspond to memory array 300 in FIG. 3A . As depicted, cross-point memory array 360 includes word lines 365-368 and bit lines 361-364. Wordline 366 includes the selected wordline, and bitline 362 includes the selected bitline. At the intersection of the selected word line 366 and the selected bit line 362 is the selected memory cell (S cell). The voltage across the S cell is the difference between the selected word line voltage and the selected bit line voltage.

The memory cells at the intersection of the selected word line 366 and the unselected bit lines 361, 363, and 364 comprise unselected memory cells (H cells). H cells are unselected memory cells that share the selected word line biased to the selected word line voltage. The voltage across the H cells is the difference between the selected word line voltage and the unselected bit line voltage.

The memory cells at the intersection of the selected bit line 362 and the unselected word lines 365, 367, and 368 comprise unselected memory cells (F cells). F cells are unselected memory cells that share the selected bit line biased to the selected bit line voltage. The voltage across the F cell is the difference between the unselected word line voltage and the selected bit line voltage.

The memory cells at the intersection of unselected word lines 365, 367, and 368 and unselected bit lines 361, 363, and 364 comprise unselected memory cells (U cells). The voltage across the U cell is the difference between the unselected word line voltage and the unselected bit line voltage.

The number of F cells is related to the length of the bit line (or the number of memory cells connected to the bit line), whereas the number of H cells is related to the length of the word line (or the number of memory cells connected to the word line). The number of U cells is related to the product of word line length and bit line length. In one embodiment, each memory cell sharing a particular word line, such as word line 365 , may be associated with a particular page stored within cross-point memory array 360 .

Figure 3D depicts an alternative example of a cross-point memory array. Cross-point memory array 370 may correspond to memory array 300 in FIG. 3A . As depicted, cross-point memory array 370 includes word lines 375-378 and bit lines 371-374. Word line 376 comprises the selected word line, and bit lines 372 and 374 comprise the selected bit lines. Although both bit lines 372 and 374 are selected, the voltages applied to bit line 372 and bit line 374 may be different. For example, where bitline 372 is associated with a first memory cell to be programmed (ie, an S cell), then bitline 372 can be biased to a selected bitline voltage to program the first memory cell. In the event that bit line 374 is associated with a second memory cell that is not being programmed (ie, an I cell), then bit line 374 can be biased to a program inhibit voltage (ie, the bit line voltage will prevent the second memory cell from being programmed).

At the intersection of the selected word line 376 and the selected bit line 374 is a program inhibit memory cell (I-cell). The voltage across the I cell is the difference between the selected word line voltage and the program inhibit voltage. The memory cells at the intersection of the selected bit line 374 and the unselected word lines 375, 377 and 378 comprise unselected memory cells (X cells). X cells are unselected memory cells that share the selected bit line biased to the program inhibit voltage. The voltage across cell X is the difference between the unselected word line voltage and the program inhibit voltage.

In one embodiment, the program inhibit voltage applied to the selected bit line 374 may be similar to the unselected bit line voltage. In another embodiment, the program inhibit voltage may be a voltage greater or less than the unselected bit line voltage. For example, the program inhibit voltage may be set to a voltage between a selected word line voltage and an unselected bit line voltage. In some cases, the applied program inhibit voltage can be a function of temperature. In one example, the program inhibit voltage can track the unselected bit line voltage over temperature.

In one embodiment, two or more pages may be associated with a particular word line. In one example, word line 375 may be associated with a first page and a second page. The first page may correspond to bit lines 371 and 373 , and the second page may correspond to bit lines 372 and 374 . In this case, the first page and the second page may correspond to interdigitated memory cells sharing the same word line. Because memory cells associated with one or more other pages will share the same selected word line as the first page, when a memory array operation (such as a programming operation) is being performed on the first page and the selected word line 376 is off When brought to the selected word line voltage, one or more other pages also associated with the selected word line 376 may contain H cells.

In some embodiments, not all unselected bit lines can be driven to the voltage of the unselected bit lines. Instead, several unselected bit lines can be floating and indirectly biased via unselected word lines. In this case, the memory cells of memory cell 370 may include resistive memory elements instead of isolation diodes. In one embodiment, bitlines 372 and 373 may comprise vertical bitlines in a three-dimensional memory array including comb wordlines.

FIG. 4A depicts one embodiment of a portion of a monolithic three-dimensional memory array 400 that includes a first memory level 410 and a second memory level 412 positioned above the first memory level 410 . Memory array 400 is one example of an implementation of memory array 150 in Figure IE. The local bit lines LBL ₁₁ -LBL ₃₃ are arranged in a first direction (eg, z direction), and the word lines WL ₁₀ -WL ₂₃ are arranged in a second direction (eg, x direction) perpendicular to the first direction. This arrangement of vertical bit lines in a monolithic three-dimensional memory array is one embodiment of a vertical bit line memory array.

As depicted, disposed between the intersection of each local bit line and each word line is a particular memory cell (eg, memory cell M ₁₁₁ is disposed between local bit line LBL ₁₁ and word line WL ₁₀ ). Certain memory cells may comprise floating gate devices, charge trapping devices (eg using silicon nitride materials), reversible resistance switching elements, ReRAM devices, or other similar devices. The global bit lines _GBL1 - _GBL3 are arranged in a third direction (eg, y direction) perpendicular to both the first direction and the second direction.

Each local bit line LBL ₁₁ -LBL ₃₃ has an associated bit line select transistor Q ₁₁ -Q ₃₃ , respectively. Bit line select transistors _Q11 - _Q33 may be field effect transistors such as shown or may be any other transistors. As depicted, bit line select transistors Q ₁₁ -Q ₃₁ are associated with local bit lines LBL ₁₁ -LBL ₃₁ , respectively, using row select line SG ₁ , and can be used to connect local bit lines LBL ₁₁ -LBL ₃₁ respectively to Global bit lines GBL ₁ -GBL ₃ . In particular, each of the bit line selection transistors Q ₁₁ -Q ₃₁ has a first terminal (eg drain/source terminal) respectively coupled to a corresponding one of the local bit lines LBL ₁₁ -LBL ₃₁ , respectively coupled to to a second terminal (eg, a source/drain terminal) of a corresponding one of the global bit lines _GBL1 - _GBL3 , and a third terminal (eg, a gate terminal) coupled to the row select line _SG1 .

Similarly, bit line select transistors Q ₁₂ -Q ₃₂ are associated with local bit lines LBL 12 -LBL ₃₂ , respectively, using row select _line SG ₂ , and can be used to connect local bit lines LBL ₁₂ -LBL ₃₂ respectively to global bit lines Lines GBL ₁ -GBL ₃ . In particular, each of the bit line select transistors Q ₁₂ -Q ₃₂ has a first terminal (eg drain/source terminal) respectively coupled to a corresponding one of the local bit lines LBL ₁₂ -LBL ₃₂ , respectively coupled to to a second terminal (eg, source/drain terminal) of a corresponding one of the global bit lines _GBL1 - _GBL3 , and a third terminal (eg, gate terminal) coupled to row select line _SG2 .

Likewise, bit line select transistors Q ₁₃ -Q ₃₃ are associated with local bit lines LBL 13 -LBL ₃₃ , respectively, using row select _line SG ₃ , and can be used to connect local bit lines LBL ₁₃ -LBL ₃₃ respectively to global bit lines Lines GBL ₁ -GBL ₃ . In particular, each of the bit line selection transistors Q ₁₃ -Q ₃₃ has a first terminal (eg drain/source terminal) respectively coupled to a corresponding one of the local bit lines LBL ₁₃ -LBL ₃₃ , respectively coupled to to a second terminal (eg, a source/drain terminal) of a corresponding one of the global bit lines _GBL1 - _GBL3 , and a third terminal (eg, a gate terminal) coupled to a row selection line _SG3 .

Because a single bitline select transistor is associated with a corresponding local bitline, the voltage of a particular local bitline can be applied to the corresponding local bitline. Therefore, when the first set of local bitlines (eg, LBL ₁₁ -LBL ₃₁ ) are biased to the global bitlines, the other local bitlines (eg, LBL ₁₂ -LBL ₃₂ and LBL ₁₃ -LBL ₃₃ ) must either be driven to the same Global bit lines GBL ₁ -GBL ₃ , or floating.

In one embodiment, during memory operation, all local bitlines within the memory array are first biased to an unselected bitline voltage by connecting each of the local bitlines to one or more local bitlines. After biasing the local bitlines to the unselected bitline voltage, however only the first set of local bitlines _LBL11 - _LBL31 are biased to one or more selected bitlines via the global bitlines _GBL1 - _GBL3 voltage while other local bit lines (eg, LBL ₁₂ -LBL ₃₂ and LBL ₁₃ -LBL ₃₃ ) are floating. The one or more selected bit line voltages may correspond to, for example, one or more read voltages during a read operation or one or more program voltages during programming.

In one embodiment, a vertical bit line memory array, such as memory array 400, contains a greater number of memory cells along word lines (e.g., memory cells along word lines) than the number of memory cells along vertical bit lines. The number of cells can be more than ten times the number of memory cells along a bit line). In one example, the number of memory cells along each bit line may be 16 or 32, but the number of memory cells along each word line may be 2048 or more than 4096. Other numbers of memory cells along each bit line and along each word line may be used.

In one embodiment of a read operation, data stored in a selected memory cell (eg, memory cell M ₁₁₁ ) may be biased by biasing the memory cell connected to the selected memory cell (eg, selected word line WL ₁₀ ) to The selected word line voltage (for example, 0V) in the read mode is used for reading. Via the associated bit line select transistor (eg Q _{11 ) coupled to the selected local bit line (LBL 11 )} and the global bit line (eg GBL ₁ ) coupled to the bit line select transistor (Q ₁₁ ), The local bit line (eg LBL ₁ ) coupled to the selected memory cell (M ₁₁₁ ) is biased to the selected bit line voltage (eg IV) in read mode. A sense amplifier can then be coupled to the selected local bit line (LBL ₁₁ ) to determine the read current I _READ of the selected memory cell (M ₁₁₁ ). Read current I _READ is conducted by bit line select transistor Q ₁₁ and may be between about 100 nA and about 500 nA, although other read currents may be used.

In one embodiment _of a write operation, data can be written to the selected memory unit (for example, memory unit M ₂₂₁ ). Via the associated bit line select transistor (eg Q ₂₁ ) coupled to the selected local bit line (LBL ₂₁ ) and the global bit line (eg GBL ₂ ) coupled to the bit line select transistor (Q ₂₁ ), The local bit line (eg LBL ₂₁ ) coupled to the selected memory cell (M ₂₂₁ ) is biased to the selected bit line voltage (eg IV) in read mode. During a write operation, programming current I _PGRM is conducted by the associated bit line select transistor Q ₂₁ and may be between about 3 μA and about 500 μA, although other programming currents may be used.

Figure 4B depicts an embodiment of a portion of a monolithic three-dimensional memory array comprising vertical strips of non-volatile memory material. The physical structure depicted in Figure 4B may comprise one implementation of a portion of the monolithic three-dimensional memory array depicted in Figure 4A. Vertical strips of non-volatile memory material may be formed in a direction perpendicular to the substrate (eg, in the z-direction). The vertical strips of nonvolatile memory material 414 may comprise, for example, vertical oxide layers, vertical reversible resistance-switching element materials (e.g., metal oxide layers such as nickel oxide, or other similar metal oxide materials, phase change materials, or other reversible resistive switching element material), or a vertical charge trapping layer (such as a silicon nitride layer). A vertical strip of material may comprise a single continuous layer of material that may be used by multiple memory cells or devices.

In one example, the portion of the vertical strip of nonvolatile memory material 414 may include the portion of the first memory cell associated with the cross section between WL ₁₂ and LBL ₁₃ and the portion of the second memory cell associated with WL ₂₂ and LBL ₁₃ between the associated parts of the cross-section. In some cases, a vertical bit line such as LBL ₁₃ may contain vertical structures (e.g., rectangular prisms, cylinders, or pillars), and nonvolatile material may completely or partially surround the vertical structures (e.g., around the sides of the vertical structures). Conformal layer of phase change material on the edge).

As depicted, each of the vertical bitlines can be connected to one of the set of global bitlines via an associated vertically oriented bitline select transistor (eg, Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₂₃ ). Each vertically oriented bit line select transistor may comprise a MOS device (eg, an NMOS device) or a vertical thin film transistor (TFT).

In an embodiment, each vertically-oriented bitline select transistor is a vertically-oriented pillar-shaped TFT coupled between an associated local bitline pillar and a global bitline. In an embodiment, a vertically oriented bit line select transistor is formed in a pillar select layer (which is formed over a CMOS substrate), and a memory layer including multiple layers of word lines and memory elements is formed over the pillar select layer.

5A-5D depict various views of an embodiment of a portion of a monolithic three-dimensional memory array 500 comprising vertical strips of non-volatile memory material. The physical structures depicted in Figures 5A-5D may comprise one implementation of portions of the monolithic three-dimensional memory array depicted in Figure 4A.

The monolithic three-dimensional memory array 500 includes vertical bit lines LBL ₁₁ -LBL ₈₈ arranged in a first direction (eg, z direction), and word lines WL ₁₀ arranged in a second direction (eg, x direction) perpendicular to the first direction. , WL ₂₀ , ..., WL ₆₁₅ , row selection lines SG ₁ , SG ₂ , ..., SG ₈ arranged in the second direction, and arranged in a third direction (eg, y direction) perpendicular to the first and second directions Global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ on . Vertical bit _lines LBL ₁₁ -LBL ₈₈ are arranged above the global bit lines GBL ₁ , GBL ₂ , .

In an embodiment _, the global bit lines GBL ₁ , GBL ₂ , . . . ) or other substrates with or without additional circuitry). In an embodiment, an isolation layer 504 such as a layer of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating layer may be formed over the substrate 502 . In an embodiment, dielectric layers 506 and 508 (eg, silicon dioxide) are formed over isolation layer 504 , and global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ are disposed over dielectric layer 508 .

Memory cells are disposed between the intersection of each vertical bit line and each word line (eg memory cell M ₁₁₁₄ is disposed between vertical bit line LBL ₁₇ and word line WL ₁₁₃ and memory cell M ₄₁₉ is disposed between vertical bit line LBL ₁₅ and word line WL ₄₈ ). Each memory cell may comprise a floating gate device, a charge trapping device (eg using silicon nitride material), a resistance change memory device, or another type of memory device. Vertically oriented bit line select transistors _Q11 - _Q88 may be used to select a corresponding one of the vertical bit lines _LBL11 - _LBL88 . The vertically oriented bit line select transistors _Q11 - _Q88 may be field effect transistors, but any other transistor type may be used.

Each of the vertically oriented bit line select transistors _Q11 - _Q88 has a first terminal (eg, drain/source terminal), a second terminal (eg, source/drain terminal), a first control terminal (eg, second a gate terminal) and a second control terminal (eg, a second gate terminal). The first gate terminal and the second gate terminal may be disposed on opposite sides of the vertically oriented bit line select transistor. The first gate terminal may be used to selectively induce a first conductive channel between the first terminal and the second terminal of the transistor, and the second gate terminal may be used to selectively induce the first terminal and the second terminal of the transistor between the second conductive channel.

In an embodiment, the first gate terminal and the second gate terminal are coupled together to form a single control terminal that can be used to collectively turn on or off the vertically oriented bit line select transistor. Thus, the first and second gate terminals of each of the vertically oriented bit line select transistors Q ₁₁ -Q ₈₈ can be used to select the corresponding one of the vertical bit lines LBL ₁₁ , LBL ₁₂ , . . _. One. Without wishing to be bound by any particular theory, for each of the vertically oriented bit line select transistors _Q11 - _Q88 , it is believed that a Both to increase the current drive capability of the transistor to turn on the transistor. For simplicity, the selection of the first and second gate terminals of each of transistors Q ₁₁ -Q ₈₈ may refer to a single gate terminal.

Referring to FIG. 5A, vertically oriented bit line select transistors Q ₁₁ , Q ₁₂ , ..., Q ₁₈ are used to selectively select vertical bit lines LBL ₁₁ , LBL ₁₂ using row select lines SG ₁ , SG ₂ , ..., SG _8, respectively. , . . . , LBL ₁₈ are connected to the global bit line GBL ₁ or disconnected from the global bit line GBL ₁ , respectively, the vertical bit lines LBL ₁₁ , LBL ₁₂ , . . . , LBL ₁₈ . In particular, each _{of the vertically oriented bit line select transistors Q 11 , Q 12 , . . .} , Q ₁₈ has a first terminal (eg drain/source terminal), a second terminal (eg source/drain terminal) respectively coupled to a corresponding one of the global bit lines GBL ₁ , and to row select lines SG ₁ , SG ₂ , . . . , the third terminal (eg, gate terminal) of SG ₈ . The row selection lines SG ₁ , SG ₂ , ..., SG ₈ are used to turn on/off the vertically oriented bit line selection transistors Q ₁₁ , Q ₁₂ , ..., Q ₁₈ respectively, so that the vertical bit lines LBL ₁₁ , LBL ₁₂ , . . . , LBL ₁₈ are connected to the global bit line GBL ₁ , or the vertical bit lines LBL ₁₁ , LBL ₁₂ , . . . , LBL ₁₈ are respectively disconnected from the global bit line GBL ₁ .

Similarly, referring to FIG. 5C, the vertically oriented bit line selection transistors Q ₁₁ , Q ₂₁ , ..., Q ₈₁ are used to use the row selection line SG ₁ to selectively communicate with the global bit lines GBL ₁ , GBL ₂ , ..., GBL, respectively. _8. Connect/disconnect vertical bit lines LBL ₁₁ , LBL ₂₁ , . . . , LBL ₈₁ . In particular, each _of the vertically oriented bit line selection transistors Q ₁₁ , Q _{21 ,} . . _. , Q ₈₁ has a first terminal (eg, drain/source terminal), a second terminal (eg, source/drain terminal) respectively coupled to a corresponding one of the global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ , and coupling to the third terminal (eg gate terminal) of row select line _SG1 . _The row selection line SG ₁ is used to turn on/off _the vertically oriented bit line selection transistors Q ₁₁ , Q ₂₁ , _{. .} . The bitlines _GBL1 , _GBL2 , ..., _GBL8 or the vertical bitlines _LBL11 , _LBL21 , ..., _LBL81 are disconnected from the global bitlines _GBL1 , _GBL2 , ..., _GBL8 , respectively.

Similarly, referring to FIG. 5D, the vertically oriented bit line selection transistors Q ₁₄ , Q ₂₄ , ..., Q ₈₄ are used to use the row selection line SG ₄ to selectively select the vertical bit lines LBL ₁₄ , LBL ₂₄ , ..., LBL respectively. ₈₄ is connected to global bit lines GBL ₁ , _{GBL 2 , . . . , GBL 8 or disconnects vertical bit lines LBL 14 , LBL 24 , .} In particular, each of _the vertically oriented bit line select transistors Q ₁₄ , Q ₂₄ , . _{. . , Q 84 has a} first terminal (eg, drain/source terminal), a second terminal (eg, source/drain terminal) respectively coupled to a corresponding one of the global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ , and coupling to the third terminal (eg gate terminal) of row select line SG ₄ . The _row select line SG ₄ is used to turn on/off _{the vertically oriented bit line select transistors Q 14 , Q 24 , . . .} The bitlines _GBL1 , _GBL2 , ..., _GBL8 or the vertical bitlines _LBL14 , _LBL24 , ..., _LBL84 are disconnected from the global bitlines _GBL1 , _GBL2 , ..., _GBL8 , respectively.

In an embodiment, the monolithic three-dimensional memory array 500 includes a first set of local bit lines (eg, LBL ₁₁ , LBL ₂₁ , LBL ₃₁ , LBL ₄₁ , . . . , LBL ₁₈ , LBL ₂₈ , LBL ₃₈ , LBL ₄₈ ) and Region 510 between the second set of local bit lines (eg, LBL ₅₁ , LBL ₆₁ , LBL ₇₁ , LBL ₈₁ , . . . , LBL ₆₈ , LBL6 ₂₈ , LBL ₇₈ , LBL ₈₈ ). In an embodiment, region 510 includes vertical conductors 512 extending in a first direction (eg, z-direction). Vertical conductors 512 may be coupled to some or all of word lines WL ₁₀ , WL ₂₀ , . . . , WL ₆₁₅ . Therefore, the region 510 may also be referred to as a "word line junction region 510".

As depicted in FIG. 5B , row select lines SG ₁ , SG ₂ , SG ₇ , and SG ₈ extend through word line junction region 510 in a third direction (eg, the y direction). The row selection lines SG ₃ , SG ₄ , SG ₅ , and SG ₆ also extend in the y direction without extending through the word line wiring region 510 . Instead, each of row select lines SG ₃ , SG ₄ , SG ₅ , and SG ₆ is divided into two sections, a first section to the left of word line wiring region 510 (depicted in FIG. The second part on the right (depicted in Figure 5B). In an embodiment, the first and second portions of row select lines SG ₃ , SG ₄ , SG ₅ , and SG ₆ are separated by a distance X of between about 4500 Angstroms and about 27000 Angstroms.

In an embodiment, the row selection lines SG ₃ , SG ₄ , SG ₅ and SG ₆ are connected via vertical conductive pillars and conductive traces on a conductive layer (eg, metal layer M1 ) disposed under the word line connection region 510 . The first and second parts of each are connected to each other. In this regard, the first and second portions of each of the row select lines SG ₃ , SG ₄ , SG ₅ , and SG ₆ are coupled together without extending through the word line wiring region 510 .

For example, as shown in FIG. 5B , conductive pillar 514a1 , conductive trace 516a , and conductive pillar 514a2 couple the first and second portions of row select line SG ₃ together. Likewise, as shown in FIGS. 5A and 5D , conductive post 514b1 conductive trace 5156b and conductive post 516b2 couple row select line SG ₄ together. Similarly, as shown in FIG. 5A, conductive post 514c1, conductive trace 516c, and conductive post 514c2 couple the first and second portions of row select line _SG5 together, and conductive post 514d1, conductive trace 516d, and conductive Post 514d2 couples together the first and second portions of row select line SG ₆ .

As shown in FIG. 5D , in an embodiment, vias 518 and 520 may be used to connect conductive posts 514b1 and 514b2 to conductive trace 516b. In an embodiment, the via 520 is formed in the global bit line layer, and the via 518 is formed in a layer between the global bit line layer and the metal layer M1. Although not shown in FIGS. 5A-5D , similar vias 518 and 520 may be used to connect conductive posts 514a1 and 514a2 to conductive trace 516a, conductive posts 514c1 and 514c2 to conductive trace 516c, and Conductive posts 514d1 and 514d2 are connected to conductive trace 516d. In another embodiment, conductive traces 514a-514d may alternatively be formed on the same level and using the same conductive layer material as global bitlines _GBL1 , _GBL2 , . . . , _GBL8 . Such an embodiment may eliminate the need for via 518 .

Referring to FIGS. 6A-6L2 , an example method of forming a monolithic three-dimensional memory array, such as the monolithic three-dimensional memory array of FIGS. 5A-5D , is described.

Referring to FIG. 6A , a substrate 502 is shown as it has been subjected to several process steps. Substrate 502 may be any suitable substrate such as silicon, germanium, germanium silicide, undoped, doped, bulk, silicon-on-insulator (“SOI”), or other substrate with or without additional circuitry . For example, substrate 502 may contain one or more n-well or p-well regions (not shown). An isolation layer 504 is formed over the substrate 502 . In some embodiments, the isolation layer 504 may be a layer of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating layer.

Following the formation of the isolation layer 504 , a conductive layer 505 is deposited on the isolation layer 504 . Conductive layer 505 may comprise any suitable conductive material such as tungsten or another suitable metal, heavily doped semiconductor material, conductive silicide, conductive silicon germanide, conductive germanium, etc., formed by any suitable method (e.g., CVD, PVD etc.) deposition. In at least one embodiment, conductive layer 505 may include between about 200 and about 2500 Angstroms of tungsten. Other conductive layer materials and/or thicknesses may be used. In some embodiments, an adhesive layer (not shown) such as titanium silicon nitride or other similar adhesive layer material may be disposed between the isolation layer 504 and the conductive layer 505, and/or between the conductive layer 505 and the subsequent vertical Orientation of the bit line between select transistor layers.

Those of ordinary skill in the art will understand that the adhesive layer can be formed on the conductive layer by PVD or other methods. For example, the adhesion layer may be between about 20 and about 500 Angstroms, and in some embodiments about 100 Angstroms of titanium nitride or other suitable adhesion layer such as tantalum nitride, tungsten nitride, tungsten, molybdenum, combination of one or more adhesive layers, etc.). Other adhesive layer materials and/or thicknesses may be used. To simplify the drawings, the adhesive layer is not depicted in any of Figures 6A-6L2. Those of ordinary skill in the art will appreciate that such adhesive layers may be used.

Following the formation of the conductive layer 505, the conductive layer 505 is patterned and etched. For example, the conductive layer 505 can be patterned and etched using conventional photolithography techniques with soft or hard masks and wet or dry etching processes. In at least one embodiment, conductive layer 505 is patterned and etched to form conductive traces 516a-516e. Example widths of the conductive traces 516a-516e and/or spacing between the conductive traces 516a-516e range from about 480 Angstroms to about 1000 Angstroms, although other conductive widths and/or spacings may be used.

After the conductive traces 516a-516e have been formed, a layer of dielectric material 506 is formed on the substrate 502 to fill the voids between the conductive traces 516a-516e. For example, approximately 3000-7000 Angstroms of silicon oxide may be deposited on substrate 502 and planarized using a chemical mechanical polishing or etch-back process to form planarized surface 507, resulting in the structures shown in FIGS. 6B1-6B2 . Planarized surface 507 includes exposed top surfaces of conductive traces 516a - 516e separated by dielectric material 506 . Other dielectric materials and/or other dielectric material layer thicknesses may be used, such as silicon nitride, silicon oxynitride, low-K dielectrics, and/or the like. Example low-K dielectrics include carbon doped oxides, silicon carbon layers, and the like.

In other embodiments, the conductive traces 516a-516e may be formed using a damascence process in which the layer of dielectric material 506 is formed, patterned, and etched to create openings or voids for the conductive traces 516a-516e. The opening or void is then filled with a conductive layer 505 (and/or a conductive seed layer, a conductive fill layer, and/or a barrier layer if desired). Conductive layer 505 is then planarized to form planarized surface 507 .

Following planarization, vias 518 are formed, resulting in the structures shown in FIGS. 6C1-6C2. Vias 518 may comprise any suitable conductive material such as tungsten or another suitable metal, heavily doped semiconductor material, conductive suicide, conductive silicon germanide, conductive germanium, etc., formed by any suitable method such as CVD , PVD, etc.) deposition. In at least one embodiment, conductive layer 518 may comprise highly doped polysilicon of between about 480 to about 1000 Angstroms. Other conductive layer materials and/or thicknesses may be used. Example widths of vias 518 and/or spacing between vias 518 range from about 480 Angstroms to about 1000 Angstroms, although other via widths and/or spacings may be used. Although vias 518 are shown as having a rectangular shape, other shapes may be used.

After the vias 518 have been formed, a layer of dielectric material 508 is formed on the substrate 502 to fill the voids between the vias 518 . For example, approximately 3000-7000 Angstroms of silicon oxide may be deposited on substrate 502 and planarized using a chemical mechanical polishing or etch back process. Other dielectric materials and/or other dielectric material layer thicknesses may be used, such as silicon nitride, silicon oxynitride, low-K dielectrics, and/or the like. Example low-K dielectrics include carbon doped oxides, silicon carbon layers, and the like.

In other embodiments, the vias 518 may be formed using a damascene process in which the layer of dielectric material 508 is formed, patterned, and etched to create openings or voids for the vias 518 . The opening or void may be filled with a conductive layer (and/or a conductive seed layer, a conductive fill layer, and/or a barrier layer if desired).

Following planarization, global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ and vias 520 are formed. For example, a conductive layer may be deposited on the substrate 502 and then patterned and etched using conventional photolithographic techniques with soft or hard masks and wet or dry etch processes to form global bit lines _GBL1 , _GBL2 , ..., GBL ₈ . Exemplary widths of global bitlines _{GBL 1} , GBL ₂ , . . . , GBL ₈ and/or spacing between global bitlines GBL ₁ , GBL ₂ , . Use other conductive widths and/or spacing. Example widths of vias 520 and/or spacing between vias 520 range from about 240 Angstroms to about 1000 Angstroms, although other via widths and/or spacings may be used. In an embodiment, the via 520 has a rectangular shape, although other shapes may be used.

In an embodiment, global bit _lines GBL ₁ , GBL ₂ , . . . etc., which are deposited by any suitable method (eg, CVD, PVD, etc.). In at least one embodiment, the global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ and via 520 comprise between about 240 and about 1000 Angstroms of tungsten. Other conductive layer materials and/or thicknesses may be used.

After _the global bit lines GBL ₁ , GBL ₂ , _{. . .} and the gap between the vias 520 . For example, approximately 3000-7000 Angstroms of silicon oxide may be deposited on substrate 502 and planarized using a chemical mechanical polishing or etch-back process to form planarized surface 524, resulting in the structures shown in FIGS. 6D1-6D3 . Planarized surface 524 includes exposed top surfaces of global bitlines GBL ₁ , GBL ₂ , . . . , GBL ₈ and vias 520 separated by dielectric material 524 . Other dielectric materials and/or other dielectric material layer thicknesses may be used, such as silicon nitride, silicon oxynitride, low-K dielectrics, and/or the like. Example low-K dielectrics include carbon doped oxides, silicon carbon layers, and the like.

In _other embodiments _, global bitlines GBL ₁ , GBL ₂ , . The space between GBL ₂ , . . . , GBL ₈ and via 520 . The opening or void may be filled with a conductive layer (and/or a conductive seed layer, a conductive fill layer, and/or a barrier layer if desired).

Following planarization, the semiconductor material used to form the vertically oriented bit line select transistors Q ₁₁ -Q ₈₈ is formed over the planarized top surface 524 of the substrate 502 . In some embodiments, each vertically oriented bit line select transistor is constructed of a polycrystalline semiconductor material such as polycrystalline silicon, polycrystalline silicon-germanium alloy, polycrystalline germanium, or any other suitable material. Alternatively, the vertically oriented bit line select transistors Q ₁₁ -Q ₈₈ can be constructed of a wide bandgap semiconductor material such as ZnO, InGaZnO or SiC, which can provide a high breakdown voltage and is typically used in Offers a junction-free FET. One of ordinary skill in the art will understand that other materials may be used.

In some embodiments, each vertically oriented bit line select transistor may comprise a first region (e.g. n+ polysilicon), a second region (e.g. p polysilicon) to form the drain/source, and source of the vertical FET, respectively. /drain region. For example, heavily doped n+ polysilicon layer 526 may be deposited on planarized top surface 524 . In some embodiments, n+ polysilicon layer 526 is in an amorphous state as deposited. In other embodiments, n+ polysilicon layer 526 is in polycrystalline as deposited. CVD or any other suitable process may be used to deposit n+ polysilicon layer 526 .

In an embodiment, for example, the n+ polysilicon layer 526 may be composed of phosphorus or arsenic doped silicon with a doping concentration of about 100 to about 500 Angstroms with a doping concentration of about 10 ²¹ cm ⁻³ . Other layer thicknesses, doping types and/or doping concentrations may be used. For example, N+ polysilicon layer 526 may be doped in situ by flowing a supply gas during deposition. Other doping methods (such as implantation) can be used.

After the deposition of n+ polysilicon layer 526 , doped p-type silicon layer 528 may be formed over n+ polysilicon layer 526 . P-type silicon can either be deposited and doped by ion implantation, or can be doped in situ during deposition to form p-type silicon layer 528 . For example, an intrinsic silicon layer may be deposited on the n+ polysilicon layer 526, and a dummy p-type implant may be used to implant boron to a predetermined depth within the intrinsic silicon layer. Example implanted molecular ions include BF ₂ , BF ₃ , B, and the like. In some embodiments, an implant dose of about 1-10×10 ¹³ ions/cm ² may be used. Other infusion types and/or doses may be used. Additionally, in some embodiments, a diffusion process may be employed. In an embodiment, the resulting p-type silicon layer 528 has a thickness from about 800 to about 4000 Angstroms, although other p-type silicon layers may be used.

Following the formation of the p-type silicon layer 528 , a heavily doped n+ polysilicon layer 530 is deposited on the p-type silicon layer 528 . In some embodiments, n+ polysilicon layer 530 is in an amorphous state as deposited. In other embodiments, n+ polysilicon layer 530 is in polycrystalline as deposited. CVD or any other suitable process may be used to deposit n+ polysilicon layer 530 .

In an embodiment, for example, the n+ polysilicon layer 530 may be composed of phosphorus or arsenic doped silicon having a doping concentration of about 100 to about 500 angstroms with a doping concentration of about 10 ²¹ cm ⁻³ . Other layer thicknesses, doping types and/or doping concentrations may be used. For example, the N+ polysilicon layer 530 may be doped in-situ by flowing a supply gas during deposition. Other doping methods (such as implantation) can be used. Those of ordinary skill in the art will appreciate that silicon layers 526, 528, and 530 may alternatively be doped p+/n/p+ separately, or may be doped with a single type of dopant to make a junctionless FET.

Following the formation of n+ polysilicon layer 530 , silicon layers 526 , 528 and 530 are patterned and etched to form first etched row 532 and second etched row 534 . For example, silicon layers 526, 528, and 530 may be patterned and etched in a wet or dry etch process using conventional photolithographic techniques. In an embodiment, the silicon layers 526, 528, and 530 are patterned and etched to form a first etch row 531 disposed over the global bit lines GBL ₁ , GBL ₂ , . . . , GBL ₈ , and disposed over the via 520 The second etch row 534 of .

As described in more detail below, the first etch row 532 will be used to form the vertically oriented bit line select transistors Q ₁₁ -Q ₈₈ , and the second etch row 534 will be used to form the vertical conductor 512 and vertical pillars of FIGS. 5A-5D . 514a1-514d2. Each of the first etched row 532 and the second etched row 534 may have a square, rectangular, or other shape, each having a width between about 240 Angstroms and about 1000 Angstroms, although other widths may be used.

Silicon layers 526, 528, and 530 may be patterned and etched in a single pattern/etch process or using separate pattern/etch steps. Any suitable masking and etching process may be used to form the first etched row 532 and the second etched row 534 . For example, silicon layers 526, 528, and 530 may be patterned using photoresist ("PR") of about 1 to about 1.5 microns, more preferably about 1.2 to about 1.4 microns, using standard photolithographic techniques. Thinner PR layers with smaller critical dimensions and technology nodes can be used. In some embodiments, an oxide hardmask may be used under the PR layer to improve pattern switching and protect the underlying layer during etching.

In some embodiments, after etching, first etch row 532 and second etch row 534 may be cleaned using a dilute hydrofluoric acid/sulfuric acid cleaner. Such cleaning may be performed with any suitable cleaning implement, such as a Raider tool (available from Semitool of Kalispell, Montana). An example post-etch clean may include using extremely dilute sulfuric acid (e.g., about 1.5-1.8 wt %) for about 60 seconds and/or extremely dilute hydrofluoric ("HF") acid (e.g., about 0.4-0.6 wt %) for 60 seconds . Megasonic waves may or may not be used. Other cleaning chemistries, times and/or techniques may be employed.

After the first etched row 532 and the second etched row 534 have been formed, a layer of dielectric material 536 is formed over the substrate 502 to fill the void between the first etched row 532 and the second etched row 534 . For example, approximately 3000-7000 Angstroms of silicon oxide may be deposited on substrate 502 and planarized using a chemical mechanical polishing or etch-back process to form planarized surface 538, resulting in the structures shown in FIGS. 6E1-6E3. Planarized surface 538 includes exposed top surfaces of first etched row 532 and second etched row separated by dielectric material 536 . Other dielectric materials such as silicon nitride, silicon oxynitride, low-K dielectrics, etc., and/or other dielectric material layer thicknesses may be used. Example low-K dielectrics include carbon doped oxides, silicon carbon layers, and the like.

In a second masking step, silicon layers 526 , 528 , and 530 are patterned and etched to form vertical transistor pillars 540 and sacrificial pillars 542 . For example, silicon layers 526, 538, and 530 may be patterned and etched using conventional photolithographic techniques in a wet or dry etch process. In an embodiment, silicon layers 526, 528, and 530 are patterned and etched to form vertical transistor pillars 540 and sacrificial pillars 542, resulting in the structures shown in FIGS. 6F1-6F3. Each of the second etching chambers 616b may have a square, rectangular, or other shape, each of which has a width between about 240 angstroms and about 1000 angstroms, and a length between about 240 angstroms and about 1000 angstroms, but Other widths and lengths can be used.

Silicon layers 526, 528, and 530 may be patterned and etched in a single pattern/etch process or using separate pattern/etch steps. Any suitable masking and etching process may be used to form vertical transistor pillars 540 and sacrificial pillars 542 . For example, silicon layers 526, 528, and 530 may be patterned using standard photolithographic techniques with a PR of about 1 to about 1.5 microns, more preferably about 1.2 to about 1.4 microns. Thinner PR layers with smaller critical dimensions and technology nodes can be used. In some embodiments, an oxide hardmask may be used under the PR layer to improve pattern switching and protect the underlying layer during etching.

In some embodiments, after etching, vertical transistor pillars 540 and sacrificial pillars 542 may be cleaned using a dilute hydrofluoric acid/sulfuric acid cleaner. Such cleaning may be performed with any suitable cleaning implement, such as a Raider tool (available from Semitool of Kalispell, Montana). Example post-etch cleaning may include using very dilute sulfuric acid (eg, about 1.5-1.8 wt %) for about 60 seconds and/or very dilute HF acid (eg, about 0.4-0.6 wt %) for 60 seconds. Megasonic waves may or may not be used. Other cleaning chemistries, times and/or techniques may be employed.

A gate dielectric layer 544 is conformally disposed over the substrate 502 and is formed on the sidewalls of the vertical transistor pillar 540 and the sacrificial pillar 542, resulting in the structures shown in FIGS. 6G1-6G3. For example, silicon oxide can be deposited at about 30 Angstroms and about 100 Angstroms. Other dielectric materials such as silicon nitride, silicon oxynitride, low-K dielectrics, etc., and/or other dielectric material layer thicknesses may be used.

Gate electrode material is deposited over vertical transistor pillar 540 and sacrificial pillar 542 and gate dielectric layer 544 to fill the gap between vertical transistor pillar 540 and sacrificial pillar 542 . For example, approximately 10 nm to approximately 20 nm of titanium nitride or other similar materials, highly doped semiconductors such as n+ polysilicon, p+ polysilicon, or other similar conductive materials may be deposited. The gate electrode material as deposited is then etched back to form row select lines SG ₁ , SG ₂ , . . . , SG ₈ , resulting in the structures shown in FIGS. 6H1-6H3 .

A layer of dielectric material 546 is deposited on the recessed row select lines SG ₁ , SG ₂ , . . . , SG ₈ . For example, approximately 5000 to approximately 8000 Angstroms of silicon oxide may be deposited or planarized using a chemical mechanical polishing or etch back process. Other dielectric materials and/or thicknesses may be used. Dielectric material layer 546 is then patterned and etched to form voids over vertical transistor pillars 540 and sacrificial pillars 542, and silicon nitride (or other etch stop material) is then deposited over substrate 502 to fill the voids, forming Silicon nitride plugs 548, resulting in the structures shown in Figures 6I1-6I3.

Next, silicon nitride plug 548, sacrificial pillar 542, and gate dielectric layer 544 are removed in word line junction region 510, creating void 550, resulting in the structure shown in FIGS. 6J1-6J3. For example, an etch may be selectively applied to the word line connection region 510 to remove the silicon nitride plug 548 , the sacrificial pillar 542 and the gate dielectric layer 544 . Etching can be applied in one or more steps.

A conductive material is deposited over substrate 502 , filling void 550 to form conductive via 552 . For example, approximately 500 to greater than 3000 Angstroms of tungsten can be deposited and planarized using a chemical mechanical polishing or etch back process, resulting in the structures shown in Figures 6K1-6K2. Other conductive materials and/or thicknesses may be used.

Finally, a chemical mechanical polishing or etch back process is used to remove portions of dielectric material 546, silicon nitride plug 548 and conductive via 552, resulting in the structure shown in FIGS. 6L1-6L2. As is known in the art, other process steps may be used to form word lines WL ₁₀ , WL ₂₀ , . . . , WL _{615 ,} vertical bit lines LBL ₁₁ , LBL ₁₂ , . To form the monolithic three-dimensional array 500 shown in FIGS. 5A-5D .

Without wishing to be bound by any particular theory, it is believed that the disclosed techniques can reduce the area required for the word line junction region 510 . For example, in an embodiment, the word line junction region 510 may be between about 0.2 μm ² and about 2.8 μm ² .

Furthermore, without wishing to be bound by any particular theory, it is believed that the disclosed technique can substantially eliminate the connection between any of the row select lines SG ₁ , SG ₂ , . . . , SG ₈ and the select gates. Risk of electrical short between any of the posts 514a1-514d2.

Thus, as noted above, one embodiment of the disclosed technology includes a method of forming a monolithic three-dimensional memory array. The method includes forming a first vertically oriented polysilicon column over a substrate, the first vertically oriented polysilicon column surrounded by a dielectric material, removing the first vertically oriented polysilicon column to form a first void in the dielectric material, And the first gap is filled with a conductive material to form a first through hole.

One embodiment of the disclosed technology includes forming a plurality of vertically oriented polysilicon pillars on a substrate, each of the plurality of vertically oriented polysilicon pillars surrounded by a dielectric material, the plurality of vertically oriented polysilicon pillars comprising a first vertically oriented The polysilicon pillars of the vertical orientation and the second vertically oriented polysilicon pillars, the row selection line is placed adjacent to the first vertically oriented polysilicon pillars, the second vertically oriented polysilicon pillars are removed to form voids in the dielectric material, and the voids are filled with conductive material to form a first via hole, and couple a row selection line to the via hole.

One embodiment of the disclosed technology includes a method of forming row select lines for a monolithic three-dimensional memory array. The method includes forming a first portion of a row selection line and a second portion of the row selection line, the first portion of the row selection line is separated from the second portion of the row selection line by a distance, forming a first through hole and a second through hole, and separating the row selection line from the second portion of the row selection line by a distance. A first portion of the select line is coupled to the first via, and a second portion of the row select line is coupled to the second via. The first and second via holes are formed by forming first and second vertically oriented polysilicon pillars above the substrate, each of the first vertically oriented polysilicon pillars and the second vertically oriented polysilicon pillars one surrounded by dielectric material, a first vertically oriented polysilicon pillar removed to form a first void in the dielectric material, and a second vertically oriented polysilicon pillar removed to form a second void in the second dielectric material , and filling the first void with a dielectric material to form a first via and filling the second void with a dielectric material to form a second via.

For the purposes of this document, each process associated with the disclosed techniques may be performed sequentially and by one or more computing devices. Each step in the process may be performed by the same or a different computing device than those used in the other steps, and does not necessarily need to be performed by a single computing device.

For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," and "another embodiment" may be used to describe different embodiments and not necessarily to refer to the same embodiment .

For the purposes of this document, a connection may be direct or indirect (eg, via other components).

For the purposes of this document, the term "collection" of objects may refer to a "collection" of one or more objects.

Although the subject matter has been described in language specific to structural features and/or subject acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (15)

1. A method of forming a monolithic three-dimensional memory array, the method comprising: forming a first vertically oriented polysilicon column over the substrate, the first vertically oriented polysilicon column surrounded by a dielectric material; removing the first vertically oriented polysilicon pillars to form a first void in the dielectric material; and The first void is filled with a conductive material to form a first through hole. 2. The method of claim 1, wherein the first vertically oriented polysilicon pillar comprises a first region, a second region and a third region. 3. The method of claim 2, wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon. 4. The method of claim 2, wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon. 5. The method according to any one of the preceding claims, further comprising: forming a second vertically oriented polysilicon column over the substrate, the second vertically oriented polysilicon column surrounded by the dielectric material; removing the second vertically oriented polysilicon pillars to form a second void in the dielectric material; and The second void is filled with the conductive material to form a second via hole. 6. The method of claim 5, wherein the second vertically oriented polysilicon pillar comprises a first region, a second region and a third region. 7. The method of claim 6, wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon. 8. The method of claim 6, wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon. 9. The method of claim 5, further comprising: forming a row selection line including a first portion and a second portion, the first portion of the row selection line being separated by a distance from the second portion of the row selection line; and A first portion of the row select line is coupled to the first via and a second portion of the row select line is coupled to the second via. 10. The method of claim 9, wherein the distance is between about 4500 Angstroms and about 27000 Angstroms. 11. A monolithic three-dimensional memory array comprising: a row selection line comprising a first portion and a second portion, the first portion of the row selection line being separated by a distance from the second portion of the row selection line; and a first via coupled to a first portion of the row selection line and a second via coupled to a second portion of the row selection line, Wherein the first through hole and the second through hole are formed by: forming first and second vertically oriented polysilicon pillars over the substrate, each of the first vertically oriented polysilicon pillar and the second vertically oriented polysilicon pillar being surrounded by a dielectric material; removing the first vertically oriented polysilicon pillars to form a first void in the dielectric material; removing the second vertically oriented polysilicon pillars to form a second void in the dielectric material; and The first void is filled with a conductive material to form the first via hole and the second void is filled with the conductive material to form the second via hole. 12. The method of claim 11, wherein the first vertically oriented polysilicon column and the second vertically oriented polysilicon column comprise a first region, a second region, and a third region. 13. The method of claim 12, wherein the first region comprises n+ polysilicon, the second region comprises p+ polysilicon, and the third region comprises n+ polysilicon. 14. The method of claim 12, wherein the first region comprises p+ polysilicon, the second region comprises n+ polysilicon, and the third region comprises p+ polysilicon. 15. The method of any one of claims 11-14, further comprising a conductive trace coupling the first via and the second via.