CN108428665B - A laminated chip integrated packaging process - Google Patents

Abstract

The present invention provides an integrated packaging process for stacked chips. The present invention utilizes a hard metal layer with a large thickness and a high hardness to carry the upper through holes to prevent collapse; the upper second and third through holes are connected to the lower through holes. The position of the plug does not correspond to each other, which further prevents the occurrence of collapse; in addition, the hard metal layer can be used as an interconnect structure, and its side can independently bear the electrical connection function, realizing that even when more chips need to be electrically interconnected, there is no need to Larger metal block upper surface area.

Description

A laminated chip integrated packaging process

technical field

The invention relates to the field of semiconductor device manufacturing, in particular to a stacked chip integrated packaging process.

Background technique

After the chips are formed on the substrate or wafer, subsequent steps such as drilling and inter-chip interconnection are required. For example, in FIG. 1 , after the chip on the substrate 1 is electrically connected to the pad 4 through the redistribution layer, it needs to form a through hole 5 in the insulating layer 2 on the pad 4 to realize the conductive lead-out terminal above the substrate 1 At the same time, it is also necessary to form the via 3 under the pad 4. Due to the existence of the via 3, the pad 4 will be recessed downward, and at the same time, the electrical connection of the upper via 5 will be poor or a defect such as the recess 5 will be generated. , which is not conducive to subsequent encapsulation. Therefore, there is a need for an interconnection method that can prevent the generation of recesses, and at the same time solves the flexible design of electrical interconnection of multiple chips at the wafer level.

SUMMARY OF THE INVENTION

Based on solving the above problems, the present invention provides a stacked chip integrated packaging process, which includes the following steps:

(1) Provide a chip substrate, the substrate includes at least a first chip and a second chip on its active surface, and the first chip and the second chip are provided with a common surface with the active surface. multiple electrode pads on the surface;

(2) depositing a first dielectric layer on the active surface, and drilling and filling the first dielectric layer to form a plurality of first through holes corresponding to the plurality of electrode pads;

(3) forming a first photoresist layer on the first dielectric layer, forming a first opening in the first photoresist layer, depositing a thin copper layer on the first opening, and forming the thin copper layer on the first opening. The copper layer just connects one electrode pad of the first chip and one electrode pad of the second chip;

(4) forming a second photoresist layer on a part of the thin copper layer, forming a second opening between the second photoresist layer and the first photoresist layer, and forming a second opening in the second opening Electroplating to form a thick copper layer;

(5) removing the first photoresist layer and the second photoresist layer;

(6) forming a third photoresist layer on the active surface and the thick copper layer, the photoresist layer has a third opening, and the third opening corresponds to the second photoresist For the covered part, a hard metal layer is electroplated in the third opening, and the thickness of the hard metal layer is greater than the thickness of the thick copper layer;

(7) removing the third photoresist layer;

(8) depositing a second dielectric layer on the active surface, the dielectric layer covering the hard metal layer and the thick copper layer;

(9) forming a plurality of second through holes in the second dielectric layer, the plurality of second through holes are located in the annular edge region of the hard metal layer and on the upper surface of the second dielectric layer forming pads, the pads are electrically connected to the plurality of second through holes;

(10) Drilling the backside of the substrate to form blind holes, the blind holes correspond to the circular central area of the hard metal layer and penetrate through the substrate, the first dielectric layer, the A thin copper layer extends into the hard metal layer;

(11) Filling the blind hole with a conductive material to form a conductive hole to form a single-layer semiconductor component;

(12) A plurality of the above-mentioned single-layer semiconductor elements are stacked and soldered on the substrate.

According to an embodiment of the present invention, the first chip and the second chip are chips formed directly on the chip substrate.

According to an embodiment of the present invention, the drilling is achieved by mechanical drilling or laser ablation drilling.

According to an embodiment of the present invention, the hard metal layer is an alloy of at least one of W, Co, and Mo and at least one of WC and TiC.

According to an embodiment of the present invention, the conductive material filled in the second through hole is copper or aluminum or the like.

According to an embodiment of the present invention, the material of the first and second dielectric layers is silicon dioxide or silicon nitride.

According to an embodiment of the present invention, the steps of forming bumps on the pads and forming solder balls on the ends of the through holes are further included.

According to an embodiment of the present invention, the active surface faces away from the substrate, and only the uppermost semiconductor components face the substrate.

The advantages of the present invention are as follows:

(1) Use a hard metal layer with a large thickness and high hardness to carry the load of the upper through hole to prevent collapse;

(2) The second and third through holes above do not correspond to the plug positions below, which further prevents the occurrence of collapse;

(3) In addition, the hard metal layer can be used as an interconnect structure, and its side surface can independently undertake the electrical connection function, so that even when more chips need to be electrically interconnected, a larger upper surface area of the metal block is not required.

Description of drawings

1 is a cross-sectional view of a prior art stacked chip integrated packaging process;

2a-2l are cross-sectional views of the integrated packaging process of the stacked chip of the present invention;

FIG. 3 is a cross-sectional view of the single-layer semiconductor device stack formed in FIG. 2 .

Detailed ways

Referring to Figures 2 and 3, the integrated packaging process of the stacked chip of the present invention includes the following steps:

(1) Provide a chip substrate 11, the substrate 11 includes at least a first chip and a second chip 12 on its active surface, the first chip and the second chip 12 are provided with the same a plurality of electrode pads 13 whose active surfaces are coplanar;

(2) depositing a first dielectric layer 14 on the active surface, and drilling and filling the first dielectric layer 14 to form a plurality of first through holes 15 corresponding to the plurality of electrode pads 13;

(3) A first photoresist layer 16 is formed on the first dielectric layer 14 , a first opening 17 is formed in the first photoresist layer 16 , and thin copper is deposited on the first opening 17 layer 18, the thin copper layer 18 only connects an electrode pad of the first chip and an electrode pad of the second chip;

(4) A second photoresist layer 19 is formed on a part of the thin copper layer 18, a second opening 20 is formed between the second photoresist layer 19 and the first photoresist layer 16, The second opening 20 is electroplated to form a thick copper layer 21;

(5) removing the first photoresist layer 16 and the second photoresist layer 19;

(6) A third photoresist layer 22 is formed on the active surface and the thick copper layer 21, the third photoresist layer 22 has a third opening, and the third opening corresponds to the On the part covered by the second photoresist 19, a hard metal layer 23 is electroplated in the third opening, and the thickness of the hard metal layer 23 is greater than the thickness of the thick copper layer 21;

(7) removing the third photoresist layer 22;

(8) depositing a second dielectric layer 24 on the active surface, the second dielectric layer 24 covering the hard metal layer 23 and the thick copper layer 21;

(9) Forming a plurality of second through holes 25 in the second dielectric layer 24, the plurality of second through holes 25 are located in the annular edge region of the hard metal layer 23, and in the second dielectric layer A pad 26 is formed on the upper surface of the layer 24, and the pad 26 is electrically connected to the plurality of second through holes 25;

(10) Drilling the backside of the substrate 11 to form a blind hole 27, the blind hole 27 corresponds to the circular central area of the hard metal layer 23 and penetrates the substrate 11, the first The dielectric layer 14 and the thin copper layer 18 extend into the hard metal layer 23;

(11) Filling the blind holes 27 with conductive substances to form conductive holes 28 to form a single-layer semiconductor component; further comprising forming bumps 29 on the pads 26 and forming solder balls 30 on the ends of the through holes 28 A step of.

(12) A plurality of the above-mentioned single-layer semiconductor elements are stacked and soldered on the substrate 34 . The formed stacked structure 40 can be seen in FIG. 3 , each layer includes a dielectric layer 35 and a substrate layer 36 , wherein the two layers are electrically connected by bumps 32 , and the bottommost semiconductor component is electrically connected to the substrate 34 by solder balls 33 . The solder ball 33 at this time is the solder ball 30 , and the bump 32 is the bump 29 .

Wherein, the first chip and the second chip are chips directly formed on the chip substrate 11 . The drilling is achieved by mechanical drilling or laser ablation drilling. The hard metal layer 23 is an alloy of at least one of W, Co, and Mo and at least one of WC and TiC. The conductive material filled in the second through hole 25 is copper or aluminum. The first and second dielectric layers 16 and 26 are made of silicon dioxide or silicon nitride.

Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (8)

1. A laminated chip integrated packaging process, comprising the following steps: (1) Provide a chip substrate, the substrate includes at least a first chip and a second chip on its active surface, and the first chip and the second chip are provided with a common surface with the active surface. multiple electrode pads on the surface; (2) depositing a first dielectric layer on the active surface, and drilling and filling the first dielectric layer to form a plurality of first through holes corresponding to the plurality of electrode pads; (3) forming a first photoresist layer on the first dielectric layer, forming a first opening in the first photoresist layer, depositing a thin copper layer on the first opening, and forming the thin copper layer on the first opening. The copper layer just connects one electrode pad of the first chip and one electrode pad of the second chip; (4) forming a second photoresist layer on a part of the thin copper layer, forming a second opening between the second photoresist layer and the first photoresist layer, and forming a second opening in the second opening Electroplating to form a thick copper layer; (5) removing the first photoresist layer and the second photoresist layer; (6) A third photoresist layer is formed on the active surface and the thick copper layer, the third photoresist layer has a third opening, and the third opening corresponds to the second photoresist layer. On the part covered by the resist, a hard metal layer is electroplated in the third opening, and the thickness of the hard metal layer is greater than the thickness of the thick copper layer; (7) removing the third photoresist layer; (8) depositing a second dielectric layer on the active surface, the second dielectric layer covering the hard metal layer and the thick copper layer; (9) forming a plurality of second through holes in the second dielectric layer, the plurality of second through holes are located in the annular edge region of the hard metal layer and on the upper surface of the second dielectric layer forming pads, the pads are electrically connected to the plurality of second through holes; (10) Drilling the backside of the substrate to form blind holes, the blind holes correspond to the circular central area of the hard metal layer and penetrate through the substrate, the first dielectric layer, the A thin copper layer extends into the hard metal layer; (11) Filling the blind hole with a conductive material to form a conductive hole to form a single-layer semiconductor component; (12) A plurality of the above-mentioned single-layer semiconductor elements are stacked and soldered on the substrate. 2 . The integrated packaging process of stacked chips according to claim 1 , wherein the first chip and the second chip are chips directly formed on the chip substrate. 3 . 3 . The integrated packaging process for stacked chips according to claim 1 , wherein the drilling is realized by mechanical drilling or laser ablation drilling. 4 . 4 . The integrated packaging process for stacked chips according to claim 1 , wherein the hard metal layer is an alloy of at least one of W, Co, and Mo and at least one of WC and TiC. 5 . 5 . The integrated packaging process for stacked chips according to claim 1 , wherein the conductive material filled in the second through hole is copper or aluminum. 6 . 6 . The integrated packaging process for stacked chips according to claim 1 , wherein the material of the first dielectric layer and the second dielectric layer is silicon dioxide or silicon nitride. 7 . 7 . The stacked chip integrated packaging process according to claim 1 , further comprising the steps of forming bumps on the pads and forming solder balls on the ends of the through holes. 8 . 8 . The stacked chip integrated packaging process according to claim 1 , wherein the active surface faces away from the substrate, and only the uppermost semiconductor components face the substrate. 9 .

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