CN108417615A - A high-voltage substrate PNP bipolar junction transistor and its manufacturing method - Google Patents

Abstract

The invention discloses a high-voltage substrate PNP bipolar junction transistor and a manufacturing method thereof; specifically, on the basis of a conventional substrate PNP bipolar junction transistor, the collector area close to the base side The first layer of metal is added to the edge, so that the first layer of metal edge of the collector covers the collector area, and the size exceeds one to five times the junction depth of the collector area, and the first layer of metal edge of the emitter also covers the emitter area Above that, the size exceeds one to five times the junction depth of the emitter region. Theoretical analysis When the device is in the reverse CE/EB/CB withstand voltage working state, the edge of the withstand voltage junction is covered by the metal field plate, so that the curvature effect of the edge surface junction when the depletion region diffuses is greatly reduced, and the BVcbo/BVceo/BVebo resistance The voltage increases sharply without any loss of forward gain, and the present invention perfectly solves the problem of achieving a compromise between gain and withstand voltage in the substrate PNP tube.

Description

A high-voltage substrate PNP bipolar junction transistor and its manufacturing method

technical field

The invention relates to a semiconductor device and a manufacturing process, in particular to a high-voltage substrate PNP bipolar junction transistor and a manufacturing method thereof.

Background technique

In the mid-1940s, due to the increasingly complex electronic device systems such as navigation, communication, and weaponry, the demand for integration and miniaturization of electronic circuits became increasingly urgent. In 1959, Fairchild Semiconductor Corporation of the United States finally gathered the technological achievements of its predecessors The first practical silicon integrated circuit was manufactured by using planar bipolar process integration technology, which created a precedent for the application and vigorous development of integrated circuits. Most widely, with the continuous advancement of integrated circuit technology, despite the huge challenge of CMOS technology, bipolar technology still develops still by virtue of its advantages in high speed, high transconductance, low noise and high current drive capability. Faster, the current main application areas are analog and ultra-high-speed integrated circuits such as high-precision operational amplifiers, drivers, interfaces, and power management.

In the early days of bipolar integrated circuits, standard silicon materials were mainly used as substrates, and buried layer technology and isolation technology were used. On the basis of standard bipolar planar technology, polysilicon emitter bipolar, complementary bipolar, SiGe bipolar, and SiGe bipolar were successively invented. SOI all-dielectric isolation bipolar technology, and widely adopted technologies such as thin-layer epitaxy, deep trench isolation, polysilicon self-alignment, multi-layer metal interconnection, etc., have continuously improved the performance of bipolar devices manufactured by new technology, but Bipolar process integration technology is also becoming more and more complex.

The basic components in the bipolar process include active devices and passive devices. Passive devices mainly include resistors, inductors, and capacitors. Active devices include diodes, NPN transistors, lateral PNP transistors, substrate PNP transistors, and suspension PNP transistors. For a single active component in a bipolar process, the designer hopes that the characteristics of the device are optimal in all aspects. The bipolar junction transistor has a series of advantages such as high gain, high current, and high frequency, but as With the continuous development of bipolar process integration technology, the disadvantages displayed are becoming more and more obvious, especially in the high-voltage field. The withstand voltage and gain, frequency, device size and other parameters of bipolar junction devices are quite difficult to reconcile. Therefore, comprehensive Considering each factor becomes a very difficult problem for the designer.

Contents of the invention

The purpose of the present invention is to solve the problems existing in the prior art, and provide a high-voltage substrate PNP bipolar junction transistor and a manufacturing method thereof.

The technical solution adopted to realize the object of the present invention is as follows, a high-voltage substrate PNP bipolar junction transistor is characterized in that it includes: P-type substrate, P-type buried layer, N-type epitaxial layer, P-type isolation Penetration region, field oxygen layer, pre-oxidation layer, P-type emitter/collector region, N-type heavily doped base region, TEOS metal pre-dielectric layer, first layer metal in collector region, first layer metal in emitter region and Base first layer metal.

The P-type buried layer covers both ends of the upper surface of the P-type substrate.

The N-type epitaxial layer covers part of the surface on the P-type substrate. The N-type epitaxial layer is in contact with the P-type buried layer.

The P-type isolation penetration region covers the P-type buried layer. The P-type isolation penetration region is in contact with both ends of the N-type epitaxial layer.

The P-type emitter/collector includes two parts, one part is located inside the middle position of the N-type epitaxial layer, and is coplanar with the upper surface of the N-type epitaxial layer, and is recorded as the P-type emitter/collector in the middle position. Area. The other part is located inside the left position of the P-type isolation penetrating region, and is coplanar with the upper surface of the P-type isolation penetrating region, and is designated as the P-type emitter/collector region on the left.

The N-type heavily doped base region covers part of the surface above the N-type epitaxial layer, and the N-type heavily doped base region is located in the P-type isolation penetration region at the left end and the P-type emitter/collector in the middle. middle of the area.

The field oxygen layer includes four parts, wherein part I covers the left side of the upper surface of the P-type isolation penetration region at the left end. Part II covers the upper surface between the P-type isolation penetration region and the N-type heavily doped base region at the left end. Part III covers the upper surface between the N-type heavily doped base region and the P-type emitter/collector region in the middle. Part IV covers the upper surface on the right side of the P-type emitter/collector region in the middle.

The pre-oxidation layer covers the upper surface between the field oxygen layers.

The TEOS pre-metal dielectric layer covers the positions of unopened contact holes on the entire surface of the device. The contact holes are respectively located in the P-type emitter/collector region and the N-type heavily doped base region.

The first metal layer of the base is located in the contact hole of the N-type heavily doped base region.

The first layer of metal in the emitter region is located in the contact hole of the P-type emitter region/collector region in the middle.

The first layer of metal in the collector region is located in the P-type emitter/collector contact hole in the P-type isolation penetration region at the left end.

A method for manufacturing a high-voltage substrate PNP bipolar junction transistor, characterized in that it comprises the following steps:

1) Provide a P-type substrate and grow an oxide layer.

2) One-time photolithography, after photolithography etch to remove the glue, grow the oxide layer, and perform P-type buried layer implantation.

3) An N-type epitaxial layer is grown, and an oxide layer is thermally grown.

4) Secondary photolithography, perform P-type isolation penetration region implantation at both ends of the device, and LP (low pressure) deposit SIN (silicon nitride).

5) Three times of photolithography, after photolithography of SIN, implant N-type impurities, and grow field oxygen layer.

6) Strip the remaining SIN, and grow a pre-oxidation layer.

7) Photolithography is performed four times, and the P-type emitter/collector region is implanted after photolithography.

8) Five times of photolithography, and N-type heavily doped base region implantation is performed after photolithography.

9) LP deposits the TEOS metal pre-dielectric layer (an oxide layer formed by a liquid source).

10) Six times of photolithography to etch a contact hole.

11) Metal deposition, seven photolithography, anti-etching aluminum.

12) alloy, passivation.

13) Eight times of photolithography to etch out the pads.

14) After low-temperature annealing, the silicon wafer preliminary test, cutting, mounting, sintering and packaging tests are carried out.

Further, the metal edge of the first layer of the emission region covers the emission region, and the size exceeds one to five times the junction depth of the emission region.

Further, the size of the first layer of metal in the collector region exceeds the junction depth of the collector region by one to five times.

Further, the materials of the P-type substrate and the N-type epitaxial layer include bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

Further, the transistor can be a substrate PNP or a substrate NPN device.

Technical effect of the present invention is beyond doubt, and the present invention has the following advantages:

1) The present invention is based on a conventional substrate PNP bipolar junction transistor, by optimizing the structural layout of the first layer of metal, adding the first layer of metal to the edge of the collector region close to the base side, Make the edge of the first metal layer of the collector cover the collector region, and the size exceeds one to five times the junction depth of the collector region, and the first layer metal edge of the emitter also covers the emitter region, and the size exceeds the junction depth of the emitter region One to five times deeper, the structure is simple and feasible, and there is no additional process.

2) The present invention is specifically a theoretical analysis. When the device is in the reverse withstand voltage working state, it is close to the edge of the withstand voltage junction due to the coverage of the metal field plate, so that the curvature effect of the edge curved surface junction is greatly reduced when the depletion region diffuses, and the withstand voltage is sharp. becomes large without any loss of positive gain.

3) Through simulation and actual tape-out results, it can be concluded that the horizontal high-voltage bipolar junction transistor of the present invention has little influence on the remaining parameters, especially the gain difference is not large, BVcbo is increased by more than 30%, BVebo is increased by more than 30%, The BVceo is increased by more than 20%, which well solves the problem of the compromise between the gain in the substrate PNP tube and the withstand voltage of the BVceo.

Description of drawings

Fig. 1 is a three-dimensional structure diagram of a high-voltage substrate PNP bipolar junction transistor;

Fig. 2 is a plane structural diagram of a high-voltage substrate PNP bipolar junction transistor;

Figure 3 is the layout of the P-type buried layer and its device structure;

Figure 4 is the layout of the P-type isolation punch-through region and its device structure;

Figure 5 is the layout of the active area and its device structure;

Fig. 6 is the layout of the P-type base region and its device structure;

Fig. 7 is the layout of the N-type heavily doped base region and its device structure;

Fig. 8 is the layout of the contact hole area and its device structure;

FIG. 9 shows the M1 metal layout and its device structure.

In the figure: P-type substrate 101, P-type buried layer 102, N-type epitaxial layer 103, P-type isolation penetration region 104, field oxygen layer 105, pre-oxidation layer 106, P-type emitter/collector region 107, N Type heavily doped base region 108, TEOS metal pre-dielectric layer 109, first layer metal 110 in the collector region, first layer metal 111 in the emitter region and first layer metal 112 in the base.

Detailed ways

The present invention will be further described below in conjunction with the examples, but it should not be understood that the scope of the subject of the present invention is limited to the following examples. Without departing from the above-mentioned technical ideas of the present invention, various replacements and changes made according to common technical knowledge and conventional means in this field shall be included in the protection scope of the present invention.

Example 1:

As shown in Figures 1 and 2, a high-voltage substrate PNP bipolar junction transistor is characterized in that it includes: a P-type substrate 101, a P-type buried layer 102, an N-type epitaxial layer 103, and a P-type isolation penetration Region 104, field oxygen layer 105, pre-oxidation layer 106, P-type emitter/collector region 107, N-type heavily doped base region 108, TEOS metal pre-dielectric layer 109, collector region first layer metal 110, emitter region The first layer metal 111 and the base first layer metal 112 .

The P-type buried layer 102 covers both ends of the upper surface of the P-type substrate 101 .

The N-type epitaxial layer 103 covers part of the surface on the P-type substrate 101 . The N-type epitaxial layer 103 is in contact with the P-type buried layer 102 .

The P-type isolation penetration region 104 covers the P-type buried layer 102 . The P-type isolation penetration region 104 is in contact with both ends of the N-type epitaxial layer 103 .

The P-type emitter/collector region 107 includes two parts, one part is located inside the middle position of the N-type epitaxial layer 103, and is coplanar with the upper surface of the N-type epitaxial layer 103, and is denoted as the P-type emitter region in the middle position / collector area 107 . The other part is located inside the left side of the P-type isolation penetrating region 104 and is coplanar with the upper surface of the P-type isolation penetrating region 104 , which is denoted as the left P-type emitter/collector region 107 .

The N-type heavily doped base region 108 covers part of the surface above the N-type epitaxial layer 103, and the N-type heavily doped base region 108 is located between the P-type isolation penetration region 104 at the left end and the P-type emitter at the middle position. region/collector region 107 in the middle.

The field oxygen layer 105 includes four parts, of which part I covers the left side of the upper surface of the P-type isolation penetration region 104 at the left end. Part II covers the upper surface between the P-type isolation penetration region 104 and the N-type heavily doped base region 108 at the left end. Part III covers the upper surface between the N-type heavily doped base region 108 and the P-type emitter/collector region 107 in the middle. Part IV covers the upper surface on the right side of the P-type emitter/collector region 107 in the middle.

The pre-oxidation layer 106 covers the upper surface between the field oxygen layers 105 .

The TEOS pre-metal dielectric layer 109 covers the positions of unopened contact holes on the entire device surface. The contact holes are respectively located in the P-type emitter/collector region 107 and the N-type heavily doped base region 108 .

The base first layer metal 112 is located in the contact hole of the N-type heavily doped base region 108 .

The first metal layer 111 of the emitter region is located in the contact hole of the P-type emitter/collector region 107 in the middle.

The first metal layer 110 of the collector region is located in the contact hole of the P-type emitter region/collector region 107 in the P-type isolation penetration region 104 at the left end.

The edge of the first layer of metal 111 in the emission region covers the emission region, and its size exceeds one to five times the junction depth of the emission region.

The size of the first metal layer 110 of the collector region exceeds the junction depth of the collector region by one to five times.

The materials of the P-type substrate 101 and the N-type epitaxial layer 103 include bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

The transistor can be a substrate PNP or a substrate NPN device.

Example 2:

As shown in Figures 3 to 9, a method for manufacturing a high-voltage substrate PNP bipolar junction transistor is characterized in that it includes the following steps:

1) Select a NTD<111> single chip with less defects, with a thickness of about 500-700 μm and a resistivity of 5-30Ω·cm, marking, cleaning, and drying for later use;

2) Growth of a thick oxide layer Temperature 1100～1150℃, time 100min～120min, dry humidification oxidation conditions.

3) One photolithography, after photolithography etch to remove glue, grow a thin oxide layer Temperature 1000～1020℃, time 30min～40min, pure dry oxidation conditions.

The P-type buried layer 102 is implanted at both ends of the wafer substrate, and the ion implantation conditions are: dose 4e15-8e15cm ^-2 , energy 60-100KeV.

The redistribution conditions are: pure N ₂ atmosphere annealing temperature, 1100-1150°C, time 100min-120min. Remove the oxide layer.

4) growing an N-type epitaxial layer 103 on the surface of the silicon wafer at a temperature of 1100° C. to 1150° C., a thickness of 5 to 30 μm, and a resistivity of 4 to 40 Ω·cm;

5) Grow a thin oxide layer Temperature 1000～1020℃, time 30min～40min, pure dry oxidation conditions.

Secondary photolithography, after photolithography, perform P-type isolation penetration region 104 implantation at both ends of the device, the ion implantation conditions are: dose 1e15-8e15cm ^-2 , energy 60-100KeV.

6) LP deposited SIN with a thickness of

7) The third photolithography, after photolithography etching SIN, generally inject N-type impurities with a dose of 1E11-5E11 and an energy of 60-100KeV, and then grow a thick oxide layer Temperature 1000～1050℃, time 200min～400min, dry humidification oxidation conditions.

The annealing and redistribution conditions are: pure N ₂ atmosphere annealing temperature, 1100-1150°C, time 100min-120min.

8) The residual SIN is peeled off, and the thickness of the peeled layer is about oxide layer. and grow a thin oxide layer Temperature 1000～1020℃, time 30min～40min, pure dry oxidation conditions.

9) Four times of photolithography, after the photolithography, the P-type collector/emitter region 107 is implanted, specifically implanted with glue, and the ion implantation conditions are: dose 1e14～5e14cm ^-2 , energy 60～100KeV;

Redistribution conditions are: anaerobic conditions, temperature 1100-1150°C, time 100min-200min;

10) Five times of photolithography. After photolithography, the N-type heavily doped base region 108 is implanted. Specifically, implantation with glue is used. The ion implantation conditions are: dose 1e15～5e15cm ^-2 , energy 40～80KeV, and the redistribution conditions are: Anaerobic conditions, temperature 950 ~ 1000 ℃, time 30min ~ 60min;

11) LP deposited TEOS with a thickness of

12) Six times of photolithography to etch a contact hole;

16) Metal deposition, metal Al is deposited on the entire surface of the wafer, seven times of photolithography and reverse etching of aluminum;

17) Alloy, furnace temperature 550°C, time 10min-30min, passivation;

18) Eight times of photolithography to etch out the pressure solder joints;

19) Low temperature annealing, the temperature is 500 ° C ~ 510 ° C, and the temperature is constant for 30 minutes;

20) Preliminary testing of silicon wafers, cutting, mounting, sintering, packaging and testing.

In this embodiment, through simulation and actual tape-out results, it can be concluded that the high-voltage substrate PNP bipolar junction transistor of the present invention has little influence on the remaining parameters, and under the condition that the gain remains basically unchanged, the BVcbo is increased by more than 30%, and the BVebo is increased by 30%. % or more, and BVceo increased by more than 20%.

Claims (6)

1. A high-voltage substrate PNP bipolar junction transistor is characterized in that it comprises: a P-type substrate (101), a P-type buried layer (102), an N-type epitaxial layer (103), and a P-type isolation penetration region (104), field oxygen layer (105), pre-oxidation layer (106), P-type emitter/collector region (107), N-type heavily doped base region (108), TEOS metal front dielectric layer (109), The first layer of metal in the collector area (110), the first layer of metal in the emitter area (111) and the first layer of metal in the base (112); The P-type buried layer (102) covers both ends of the upper surface of the P-type substrate (101); The N-type epitaxial layer (103) covers part of the surface on the P-type substrate (101); the N-type epitaxial layer (103) is in contact with the P-type buried layer (102); The P-type isolation penetration region (104) covers the P-type buried layer (102); the P-type isolation penetration region (104) is in contact with both ends of the N-type epitaxial layer (103); The P-type emitter/collector region (107) includes two parts, one part is located inside the middle position of the N-type epitaxial layer (103), and is coplanar with the upper surface of the N-type epitaxial layer (103), which is recorded as the middle The P-type emitter region/collector region (107) at the position; the other part is located inside the left position of the P-type isolation penetration region (104), and is coplanar with the upper surface of the P-type isolation penetration region (104). Be the P-type emitter region/collector region (107) at the left end; The N-type heavily doped base region (108) covers part of the surface above the N-type epitaxial layer (103), and the N-type heavily doped base region (108) is located at the left end of the P-type isolation penetration region (104 ) and the middle position of the P-type emission region/collector region (107) in the middle position; The field oxygen layer (105) includes four parts, wherein part I covers the left side of the upper surface of the P-type isolation penetration region (104) at the left end; part II covers the P-type isolation penetration region (104) at the left end and the upper surface between the N-type heavily doped base region (108); Part III covers the upper surface between the N-type heavily doped base region (108) and the P-type emitter/collector region (107) in the middle Surface; Part IV covers the upper surface on the right side of the P-type emitter/collector region (107) in the middle; The pre-oxidation layer (106) covers the upper surface between the field oxygen layers (105); The TEOS metal pre-dielectric layer (109) covers the positions of unopened contact holes on the entire device surface; the contact holes are respectively located in the P-type emitter/collector region (107), the N-type heavily doped base region (108) )within; The first metal layer (112) of the base is located in the contact hole of the N-type heavily doped base region (108); The first layer of metal (111) in the emitter region is located in the contact hole of the P-type emitter/collector region (107) in the middle; The first layer of metal (110) in the collector region is located in the contact hole of the P-type emitter/collector region (107) in the P-type isolation penetration region (104) at the left end. 2. A method for manufacturing a high voltage substrate PNP bipolar junction transistor, characterized in that it may further comprise the steps: 1) providing a P-type substrate (101), and growing an oxide layer; 2) One-time photolithography, after photolithography etching to remove glue, grow oxide layer, and perform P-type buried layer (102) implantation; 3) growing an N-type epitaxial layer (103), and thermally growing an oxide layer; 4) Secondary photolithography, perform P-type isolation penetration region (104) implantation at both ends of the device, and LP deposit SIN; 5) three times of photolithography, after photolithography of SIN, implant N-type impurities, and grow field oxygen layer (105); 6) peeling off the residual SIN, and growing a pre-oxidation layer (106); 7) Four times of photolithography, after photolithography, perform P-type emitter/collector region (107) implantation; 8) five times of photolithography, and perform N-type heavily doped base region (108) implantation after photolithography; 9) LP depositing a TEOS metal pre-dielectric layer (109); 10) Six times of photolithography to etch a contact hole; 11) Metal deposition, seven photolithography, anti-etching aluminum; 12) alloy, passivation; 13) Eight times of photolithography to etch out the pressure solder joints; 14) After low-temperature annealing, the silicon wafer preliminary test, cutting, mounting, sintering and packaging tests are carried out. 3. A high-voltage substrate PNP bipolar junction transistor and its manufacturing method according to claim 1 or 2, characterized in that: the edge of the first layer of metal (111) in the emitter region covers the emitter region, Dimensions exceeding the emitter junction depth by one to five times. 4. A high-voltage substrate PNP bipolar junction transistor and its manufacturing method according to claim 1 or 2, characterized in that: the size of the first layer metal (110) in the collector region exceeds the junction of the collector region One to five times as deep. 5. A high-voltage substrate PNP bipolar junction transistor and its manufacturing method according to claim 1 or 2, characterized in that: the materials of the P-type substrate (101) and the N-type epitaxial layer (103) These include bulk silicon, silicon carbide, gallium arsenide, indium phosphide, or silicon germanium. 6. A high-voltage substrate PNP bipolar junction transistor and its manufacturing method according to claim 1 or 2, characterized in that: the transistor can be a substrate PNP device or a substrate NPN device.