CN108417594B - An interconnection process method for a back-illuminated CMOS image sensor structure - Google Patents

Abstract

The invention discloses an interconnection process method for a back-illuminated CMOS image sensor structure, which includes: providing a bonded back-illuminated CMOS image sensor silicon wafer, forming a second dielectric layer on the back of the silicon wafer substrate, and performing the interconnection of through holes. Photolithography, etching and patterning process, fill BARC in the through hole and perform back channel photolithography, etching process and degumming to form the sidewall of the back channel structure, and fill the back channel structure with metal materials to form pin patterns. By adjusting the formation sequence of the through hole and the backside channel structure, the present invention enables the lithography related steps to be performed on a plane, which helps to improve the photolithography process effects such as exposure; the process helps to improve the removal of glue residue, thereby reducing Long-term degumming damages the surface of the metal interconnection layer and improves the reliability of electrical connections.

Description

An interconnection process method for a back-illuminated CMOS image sensor structure

technical field

The present invention relates to the technical field of semiconductor manufacturing processes, and more particularly, to an interconnection process method of a back-illuminated CMOS image sensor structure.

Background technique

In the past ten years, with the popularization and upgrading of consumer electronic products, image sensors have been widely used, and their performance has also been greatly improved. At present, there are two main types of image sensors: Complementary Metal Oxide Semiconductor (CMOS) and Charge Coupled Device (CCD), both of which use the photoelectric effect principle of silicon in light detection. : The CCD transfers the output charge through the vertical and horizontal CCD, and the voltage of the CMOS image sensor (CIS) is read out through the row-column decoding similar to the DRAM memory. Compared with CCD, CIS has the advantages of high integration, low power consumption, and compatibility with integrated circuit manufacturing processes, so its share has grown steadily.

The main structure of CMOS image sensor includes image-sensitive cell array, row driver, column driver, timing control logic, AD converter, data output interface, control interface and other parts. Semiconductor processes are used to form image-sensitive cells (photodiodes), row and column drivers, and other control circuits in sensor arrays. To capture color pixels, color filters are also placed on the image-sensitive cells. In order to reduce the pixel size and improve the resolution, CIS technology has undergone the development from front-illuminated (FSI) to back-illuminated (BSI). At present, BSI CIS has become the mainstream technology, which can realize the pixel size of 1.4~1.1μm. To form BSI CIS, semiconductor processes are performed on the backside of the bonded silicon wafers and electrical connections are made. In the related semiconductor process flow, the patterning of larger size, deeper structure and complex film layer is involved, which brings certain difficulties to the related process steps.

At present, the research on BSI CIS has been relatively in-depth, mainly from various aspects such as structural design, performance improvement, material selection, etc. The improvement of the device structure often affects the specific process of realization. U.S. Patent No. 9165970 proposes a method for specific configuration of bonding pads in an interconnect structure, but it does not involve in detail the realization of the specific process, and there is not too much process realization for the conventional BSI CIS interconnect structure. introduce.

Therefore, according to the specific structural characteristics of the back-end interconnection of BSI CIS, it is necessary to provide a reasonable process flow to reduce the difficulty of process realization and improve process reliability.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the above-mentioned defects in the prior art, and to provide an interconnection process method of a back-illuminated CMOS image sensor structure.

For achieving the above object, technical scheme of the present invention is as follows:

A method for interconnecting a back-illuminated CMOS image sensor structure, comprising the following steps:

Step S01 : providing a bonded back-illuminated CMOS image sensor silicon wafer, the silicon wafer includes a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnect structure is formed in the first dielectric layer;

Step S02: forming a second dielectric layer on the backside of the substrate, and forming through holes downwardly connected to the metal interconnect structure through photolithography and etching;

Step S03: filling the through hole with an organic anti-reflection layer material, and covering the surface of the second dielectric layer;

Step S04: carry out photolithography of the back channel pattern, and make the exposure area include a through hole pattern;

Step S05 : etching the backside channel pattern, the etching stops at the first dielectric layer, and removes the glue to form a backside channel structure connecting the through holes; wherein, during the etching process, the organic anti-reflective materials filled in the through holes are made to resist reflection. The layer material is etched synchronously, and after the etching is completed, the remaining organic anti-reflection layer material in the through hole is removed by a degumming process;

Step S06 : forming a third dielectric layer on the surface of the backside channel structure and the via structure, using anisotropic etching to remove the third medium layer at the bottom of the via hole and the backside channel structure, while controlling the loss of the third medium layer on the sidewalls , to form the side walls of the back channel structure;

Step S07: Filling the backside channel structure with a metal material to form a pin pattern.

Preferably, in step S03, a protective layer is selectively grown on the surface of the metal interconnection structure at the bottom of the through hole, and then the organic anti-reflection layer material is filled in the through hole; in step S05, it also includes removing the bottom of the through hole. The protective layer.

Preferably, the protective layer is a CoWP film or a graphene film.

Preferably, in step S03, the CoWP film is formed by chemical plating; in step S05, the CoWP film is removed by wet etching.

Preferably, in step S03, the graphene film is formed by PECVD; in step S05, the graphene film is removed synchronously during the degumming process.

Preferably, in step S02, a composite film layer and a metal layer are sequentially formed on the back surface of the substrate, and metal shielding patterns and alignment marks between the pixels are formed through a patterning process, and then the composite film layer and the alignment mark are formed on the back surface of the substrate. A planarized second dielectric layer is formed on the metal shielding pattern and the alignment mark.

Preferably, the composite film layer includes a stack of SiO ₂ , HfO ₂ , TaO and TEOS.

Preferably, an anti-reflection medium layer is formed on the surface of the metal layer.

Preferably, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are silicon dioxide.

Preferably, the material of the metal layer is Al or W, the material of the metal interconnection structure is Cu, and the material of the pin is Al.

It can be seen from the above technical solutions that the present invention adjusts the formation order of the through holes and the backside channel structure, so that the steps related to lithography can be carried out on a plane, which helps to improve the effects of lithography processes such as exposure; Improve the residue of degumming, thereby reducing the damage to the surface of the metal interconnection layer caused by long-term degumming, and improving the reliability of electrical connections.

Description of drawings

FIG. 1 is a flowchart of an interconnection process method of a back-illuminated CMOS image sensor structure according to the present invention;

2-7 are schematic cross-sectional structural diagrams of each process step of the method according to FIG. 1 in the first preferred embodiment of the present invention;

8 is a schematic cross-sectional structural diagram of the related process steps of the method according to FIG. 1 in the second preferred embodiment of the present invention.

Detailed ways

The interconnection process method of a backside illuminated CMOS image sensor structure (CIS-BSI) of the present invention is mainly used for the formation of an interconnection structure and a pin (Pad) after the pixel silicon wafer and the logic silicon wafer are bonded; for similar silicon wafers Bonding structures are also useful for reference.

The core idea of the back-illuminated CIS interconnection process of the present invention is to adjust the formation sequence of the through holes and the back-side channel structure, so that the photolithography process is basically performed in the plane area, which is convenient for exposure and helps to improve the removal of glue residue and reduce the long-term wear and tear. Glue damage to metal surfaces.

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention and facilitate the description, the structures in the accompanying drawings are not drawn according to the general scale, and the Partial enlargement, deformation and simplification of processing are shown, therefore, it should be avoided to interpret this as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 1 , which is a flowchart of an interconnection process method of a back-illuminated CMOS image sensor structure according to the present invention; please also refer to FIGS. 2-7 , and FIGS. 2-7 . It is a schematic cross-sectional structure diagram of each process step of the method according to FIG. 1 in the first preferred embodiment of the present invention. As shown in FIG. 1 , a method for interconnecting a back-illuminated CMOS image sensor structure of the present invention includes the following steps:

Step S01 : providing a bonded back-illuminated CMOS image sensor silicon wafer, the silicon wafer includes a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnect structure is formed in the first dielectric layer.

See Figure 2. Provide back-illuminated CIS silicon wafers after bonding. There are two silicon wafers. One of the silicon wafers mainly includes pixel units, logic circuits, bonding pads and other structures; the other silicon wafer mainly includes the substrate. 200 and the metal interconnect structure 101 in the first dielectric layer (interlayer dielectric layer) 100 on the substrate. The material of the first dielectric layer can be silicon dioxide, and the material of the metal interconnection structure can be Cu.

The substrate 200 of the silicon wafer is usually thinned, and the thickness may be, for example, about 2.5 μm. Since the interconnection process flow involved in this embodiment is performed on the backside of the interconnection structure silicon wafer, and the patterned area is mainly the area corresponding to the interconnection layer, only the silicon wafer of the metal interconnection structure and the relevant area corresponding to the interconnection structure layer are marked in FIG. 2 .

Step S02 : forming a second dielectric layer on the backside of the substrate, and forming through holes downwardly connected to the metal interconnect structure through photolithography and etching.

See Figure 2. First, the composite film layer 300 and the metal layer 400 are sequentially formed on the back surface of the substrate 200; an anti-reflection dielectric layer (DARC) can also be formed on the metal layer according to a conventional process. The film layer is more clear, and the anti-reflection dielectric layer is not shown in the figure. Then, a metal shield pattern 401 and an alignment mark 402 between the pixels are formed through a patterning process.

优选为

复合膜层300结构可选用多种形式，本实施例为包括SiO₂、HfO₂、TaO和TEOS的多层叠层结构。金属屏蔽图形401用于像素之间的隔离，以减少互相的干扰。The metal layer can be made of materials such as Al, W, etc. In this embodiment, Al is selected with a thickness of 2500~

preferably

The structure of the composite film layer 300 can be in various forms, and this embodiment is a multi-layered structure including SiO ₂ , HfO ₂ , TaO and TEOS. The metal shield pattern 401 is used for isolation between pixels to reduce mutual interference.

See Figure 3. Next, a second dielectric layer 500 is formed on the composite film layer, the metal shielding pattern, and the alignment mark, and the second dielectric layer is planarized. The material of the second dielectric layer can be silicon dioxide.

，优选为

。平坦化工艺可选用化学机械抛光(CMP)方式，金属屏蔽图形上余留的二氧化硅膜层厚度可为

，优选为

。经过平坦化工艺后，二氧化硅膜层500表面平整，有助于后续工艺(如光刻)的进行。The silicon dioxide film layer (the second dielectric layer) can be formed by a plasma enhanced chemical vapor deposition process (PECVD), and the film deposition thickness can be

, preferably

. The planarization process can be selected by chemical mechanical polishing (CMP) method, and the thickness of the silicon dioxide film layer remaining on the metal shielding pattern can be

, preferably

. After the planarization process, the surface of the silicon dioxide film layer 500 is flat, which facilitates subsequent processes (eg, photolithography).

See Figure 4. Next, a through hole (RV) patterning process is performed. A photolithography process may be used to form the mask layer of the pattern of the via hole, and the critical dimension (CD) of the via hole may be 0.3-0.5 μm, preferably 0.4 μm. The silicon dioxide film layer 500 and the respective film layers below it are etched until the metal interconnection structure 101 (metal one, M1 ).

The types of film layers involved in this etching process include silicon dioxide layer 500, composite film layer 300 (TEOS, TaO, HfO ₂ and SiO ₂ ), Si substrate 200, and interlayer dielectric layer 100 in the order of etching. One-step etching process is completed.

Different types of films require corresponding etching conditions. Among them, SiO ₂ and TEOS are both oxide layers, and the etching gas can be a combination of CF ₄ and CHF ₃ , specifically CF ₄ 110-130 sccm, preferably 120 sccm; CHF ₃ 90-110 sccm, preferably 100 sccm; chamber pressure 100 ~120mtorr, preferably 110mtorr; the source power range is 700-900W, preferably 800W; the bias power range is 80-120W, preferably 100W; the etching time is determined according to the film thickness and the actual etching rate of the pattern structure.

The film layers of TaO and HfO ₂ are relatively thin, and the combination of etching gases used is BCl ₃ , Cl ₂ , O ₂ , and Ar. The process conditions are: BCl ₃ 25-35 sccm, preferably 30 sccm; Cl ₂ 40-50 sccm, preferably 45 sccm O ₂ 5～7sccm, preferably 6sccm; Ar16～20sccm, preferably 18sccm; Chamber pressure 4～6mtorr, preferably 5mtorr; Source power range is 250～350W, preferably 300W; Bias power range is 150～170W , preferably 160W.

The etching gas used for the Si substrate is Cl ₂ and O ₂ , and the process conditions are: Cl ₂ 80-120 sccm, preferably 100 sccm; O ₂ 6-14 sccm, preferably 8 sccm; chamber pressure 30-60 mtorr, preferably 40 mtorr ; The source power range is 500-700W, preferably 600W; the bias power range is 250-350W, preferably 300W.

The etching process parameters of the above-mentioned film layers can be adjusted according to the actual situation, so that the sidewall morphology of the interface of different film layers remains continuous. Then, the adhesive is removed, and the obtained through hole structure 510 is shown in FIG. 4 , and the through hole is in the form of a plurality of film layer structures.

Step S03 : filling the through hole with an organic anti-reflection layer material, and covering the surface of the second dielectric layer.

See Figure 5. Next, the through hole 510 is filled with an organic anti-reflection layer material (BARC). After the through hole is formed, BARC is filled in the hole, so that the hole is filled with BARC, and a BARC film layer is formed on the surface of the second dielectric layer 500 . Because the BARC material has a certain fluidity and the size of the through hole is large, it can fill the entire through hole; in addition, the BARC film on the surface of the oxide layer of the second dielectric layer can be flattened by spin coating, which is convenient for the subsequent photolithography process. .

Step S04 : performing photolithography on the backside channel pattern, and making the exposure area include a through hole pattern.

See Figure 5. After that, the photolithography process for forming the backside lane (BSL) of the pin (Pad) is continued. The basic size of the photoresist pattern 600 for forming the backside channel may be 4.5˜5.5 μm, preferably 5 μm; the exposure area includes a through hole pattern.

Step S05 : etching the backside channel pattern, the etching stops at the first dielectric layer, and removes the glue to form a backside channel structure connecting the through holes; wherein, during the etching process, the organic anti-reflective materials filled in the through holes are made to resist reflection. The layer material is etched simultaneously, and after the etching is completed, the remaining organic anti-reflection layer material in the through hole is removed by a degumming process.

See Figure 6. Next, the etching process of the BSL pattern is performed and the glue is removed. Similar to the RV etching process, this etching process also includes a variety of film materials, mainly including oxide layer 500, composite film layer 300 (TEOS, TaO, HfO ₂ and SiO ₂ ), Si substrate 200, and stops at M1 on the interlayer dielectric layer 100 . For the etching process conditions of the corresponding film layers, refer to the RV etching process. During the etching process, the BARC filled in the via hole is also etched simultaneously.

After the etching process is completed, the photoresist and the remaining BARCs in the through holes are removed by a stripping process. In this way, the metal interconnection layer at the bottom of the via will be bombarded by plasma only after the BARC is removed, avoiding bombardment during the entire debonding process and reducing the surface damage of the metal interconnection layer to a certain extent.

So far, the final via structure 525 in the interlayer dielectric layer 100 and the BSL pattern structure 515 involving various film layer structures have been formed.

Step S06 : forming a third dielectric layer on the surface of the backside channel structure and the via structure, using anisotropic etching to remove the third medium layer at the bottom of the via hole and the backside channel structure, while controlling the loss of the third medium layer on the sidewalls , to form the side walls of the back channel structure.

优选为

然后利用各向异性刻蚀去除通孔525及背面通道结构515底部的钝化膜层，同时控制侧壁钝化膜层的损失量，以形成通孔结构有效的电学接触。See Figure 7. Next, sidewalls 530 of the BSL structure are formed. First, a third dielectric layer is formed on the surface of the BSL and the through-hole structure as a passivation film layer. Here, the preferred material for the passivation film layer is SiO ₂ , and its thickness is

preferably

Then, anisotropic etching is used to remove the passivation film at the bottom of the through hole 525 and the backside channel structure 515, and the loss of the sidewall passivation film is controlled to form an effective electrical contact of the through hole structure.

Step S07: Filling the backside channel structure with a metal material to form a pin pattern.

Finally, the metal material is filled in the BSL structure to form a pin pattern; the pin material can be Al.

Please refer to FIG. 8 . FIG. 8 is a schematic cross-sectional structural diagram of the related process steps of the method according to FIG. 1 in the second preferred embodiment of the present invention. As shown in FIG. 8 , an interconnection process method of a back-illuminated CMOS image sensor structure of the present invention is obtained by improving on the basis of the above-mentioned first embodiment, and the specific contents are:

In step S03, a protective layer 102 is selectively grown on the surface of the metal interconnection structure 101 at the bottom of the through hole, and then an organic anti-reflection layer material is filled in the through hole.

优选为

Since the metal interconnect structure 101 is made of Cu material, the protective layer 102 can be a CoWP (cobalt tungsten phosphorous) film formed by chemical plating, or a graphene film formed by PECVD, and the film thickness is

preferably

Correspondingly, in step S05, it also includes removing the protective layer at the bottom of the through hole. Among them, the CoWP film can be removed by wet etching; the graphene film can be removed simultaneously during the degumming process without adding additional removal process steps.

By adding the above-mentioned process steps on the basis of the above-mentioned first embodiment, the plasma damage caused by the debonding of the metal interconnection layer after the etching of the BSL pattern can be further avoided.

In conclusion, by adjusting the formation sequence of the through hole and the backside channel structure, the present invention enables lithography related steps to be performed on a plane, which helps to improve the effects of lithography processes such as exposure; the process helps to improve the removal of glue residues, thereby reducing the damage to the surface of the metal interconnection layer caused by long-term degumming, and improving the reliability of electrical connections.

The above are only the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the patent protection of the present invention. Therefore, any equivalent structural changes made by using the contents of the description and the accompanying drawings of the present invention shall also include within the protection scope of the present invention.

Claims (10)

1. An interconnection process method of a back-illuminated CMOS image sensor structure is characterized by comprising the following steps:

step S01: providing a bonded back-illuminated CMOS image sensor silicon wafer, wherein the silicon wafer comprises a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnection structure is formed in the first dielectric layer;

step S02: forming a second dielectric layer on the back surface of the substrate, and forming a through hole which is connected to the metal interconnection structure downwards through photoetching and etching;

step S03: filling an organic anti-reflection layer material in the through hole, and covering the surface of the second dielectric layer;

step S04: photoetching a back channel pattern, and enabling an exposure area to comprise a through hole pattern;

step S05: etching the back channel pattern, stopping etching on the first medium layer, and removing the photoresist to form a back channel structure connected with the through hole; in the etching process, synchronously etching the organic anti-reflection layer material filled in the through hole, and removing the residual organic anti-reflection layer material in the through hole by using a photoresist removing process after the etching is finished;

step S06: forming a third dielectric layer on the surfaces of the back channel structure and the through hole structure, removing the through hole and the third dielectric layer at the bottom of the back channel structure by utilizing anisotropic etching, and simultaneously controlling the loss amount of the third dielectric layer on the side wall to form the side wall of the back channel structure;

step S07: and filling a metal material in the back channel structure to form a pin pattern.

2. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 1, wherein in step S03, a protective layer is selectively grown on the surface of the metal interconnection structure at the bottom of the via hole, and then an organic anti-reflection layer material is filled in the via hole; step S05 further includes removing the protective layer at the bottom of the via.

3. The interconnection process method of the back-illuminated CMOS image sensor structure of claim 2, wherein the protection layer is a CoWP thin film or a graphene thin film.

4. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 3, wherein in step S03, the CoWP thin film is formed by electroless plating; in step S05, the CoWP film is removed by wet etching.

5. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 3, wherein in step S03, the graphene film is formed by PECVD; in step S05, the graphene film is removed simultaneously during the photoresist stripping process.

6. The interconnection process of the backside illuminated CMOS image sensor structure of claim 1, wherein in step S02, a composite film layer and a metal layer are sequentially formed on the backside surface of the substrate, and a metal shielding pattern and an alignment mark between pixels are formed by a patterning process, and then a planarized second dielectric layer is formed on the composite film layer, the metal shielding pattern and the alignment mark.

7. The method for interconnecting process of backside illuminated CMOS image sensor structure of claim 6, wherein said composite film layer comprises SiO₂、HfO₂TaO and TEOS.

8. The method according to claim 6, wherein an anti-reflective dielectric layer is formed on the surface of the metal layer.

9. The interconnection process method of the back-illuminated CMOS image sensor structure of claim 1, wherein the first, second and third dielectric layers are made of silicon dioxide.

10. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 6, wherein the metal layer material is Al or W, the metal interconnection structure material is Cu, and the pin material is Al.

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