CN108376739B - Compound semiconductor device capacitor structure and manufacturing method thereof - Google Patents
Compound semiconductor device capacitor structure and manufacturing method thereof Download PDFInfo
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Abstract
本发明公开了一种化合物半导体器件电容结构及其制作方法，是在化合物半导体基底上依次形成下极板和介电质层后，先形成第二金属层，再形成侧壁保护层覆盖第二金属层并顶部开窗后，再制作第三金属层，第三金属层通过顶部开窗与第二金属层接触以形成上极板。通过第二金属层、第三金属层和侧壁保护层的设置改善电容中电荷集中区域的结构，减少应力作用，提高可靠度以及器件使用寿命。本发明适用于不同类型的电容结构，实用性强。
The invention discloses a capacitor structure of a compound semiconductor device and a manufacturing method thereof. After a lower electrode plate and a dielectric layer are formed on a compound semiconductor substrate in sequence, a second metal layer is formed first, and then a sidewall protection layer is formed to cover the second metal layer. After the metal layer is opened with a window on the top, a third metal layer is fabricated, and the third metal layer is in contact with the second metal layer through the window on the top to form an upper electrode plate. Through the arrangement of the second metal layer, the third metal layer and the sidewall protection layer, the structure of the charge concentration region in the capacitor is improved, the stress effect is reduced, and the reliability and the service life of the device are improved. The invention is suitable for different types of capacitor structures and has strong practicability.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly, to a compound semiconductor device capacitor structure and a method for fabricating the same.
Background
With the development of equipment technology, the process capability of a compound semiconductor is higher and higher, and the control capability of the reliability of active components such as a triode is stronger and stronger. The consequent short plates of passive components emerge. The reliability of the chip for the capacitor is also increasingly required, especially in high temperature and high humidity.
Referring to fig. 1, in a capacitor structure of a compound semiconductor device, a first metal layer M1, a dielectric layer V1 and a second metal layer M2 are generally formed in sequence on a wafer having completed a device process, and an insulating layer P1 is formed around the first metal layer M3578 to compensate for a height difference, which will form a boundary region (as shown by a circle) of an inorganic compound, a metal and an organic compound among a dielectric layer V1, a second metal layer M2 and an insulating layer P1. Because the capacitor structure is a charge concentration area, the stress is the largest due to the interaction of the combination of different materials, and the device is easy to burn out in the chip aging test process, so that the reliability of the device is failed.
Disclosure of Invention
The present invention is directed to overcome the deficiencies of the prior art and to provide a compound semiconductor device capacitor structure and a method for fabricating the same.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a manufacturing method of a compound semiconductor device capacitor structure comprises the following steps:
1) providing a compound semiconductor substrate, and forming a first metal layer on the substrate to form a capacitor lower electrode plate;
2) depositing a dielectric layer on the surface of the structure formed in the step 1), wherein the thickness of the dielectric layer is 50-200 nm;
3) forming a second metal layer on the surface of the dielectric layer above the first metal layer, wherein the width of the second metal layer is smaller than that of the first metal layer, and the thickness of the second metal layer is 100-1000 nm;
4) depositing a side wall protection layer on the surface of the structure formed in the step 3), wherein the thickness of the side wall protection layer is 100-500 nm;
5) etching the side wall protection layer on the top of the second metal layer to form an etching window;
6) and forming a third metal layer, wherein the third metal layer is in contact with the second metal layer at the etching window, and the third metal layer and the second metal layer form an upper polar plate of the capacitor.
Optionally, the sidewall protection layer is silicon nitride.
Optionally, the method further includes a step of coating an insulating material on the surface of the structure formed in the step 5) to form an insulating layer, and removing the insulating layer above the etching window to form a capacitor through hole; in step 6), the third metal layer is formed in the capacitor through hole and higher than the insulating layer.
Optionally, in step 6), a TiW layer and an Au seed layer are sequentially formed in the etching window by physical vapor deposition, the TiW layer extends to the surface of the sidewall protection layer covering the edge of the etching window, then an Au electroplating layer is sequentially formed on the Au seed layer by electroplating, a Ti layer is formed on the Au electroplating layer by evaporation, and the TiW layer/the Au seed layer/the Au electroplating layer/the Ti layer constitute the third metal layer.
Optionally, a negative photoresist is used for defining the pattern of the Au electroplated layer, the angle of the negative photoresist is 75-85 degrees, and the thickness of the negative photoresist is 3-8 μm.
Optionally, the method further comprises a step of depositing a passivation layer on the surface of the structure formed in the step 6), wherein the thickness of the passivation layer is 200-1000 nm.
Optionally, the method further comprises a step of coating a photoresist layer on the surface of the structure formed in the step 5), and removing the photoresist layer above the etching window to form a capacitor through hole; in the step 6), the third metal layer is formed in the capacitor through hole and extends to the surface of the photoresist layer towards one side, and then the photoresist layer is removed to form a metal bridge structure.
Optionally, in step 6), a TiW layer and an Au seed layer are sequentially formed on the surface of the capacitor through hole and the surface of the photoresist layer on one side of the capacitor through hole by physical vapor deposition, and an Au electroplated layer is formed on the Au seed layer by electroplating, and the TiW layer/Au seed layer/Au electroplated layer forms the third metal layer.
A compound semiconductor device capacitor structure comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer, an insulating layer, a third metal layer and a passivation layer which are sequentially arranged; the first metal layer is arranged on the substrate and forms a lower electrode plate of the capacitor, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to the surface of the dielectric layer covering two sides, the insulating layer is coated on the side wall protection layer, a capacitor through hole is formed in the top of the second metal layer, the third metal layer is arranged in the capacitor through hole and is higher than the surface of the insulating layer, the second metal layer and the third metal layer form a lower electrode plate of the capacitor, and the passivation layer covers the third metal layer and the surface of the insulating layer.
The other compound semiconductor device capacitor structure comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer, a third metal layer and a passivation layer which are sequentially arranged; the first metal layer is arranged on the substrate and forms a lower electrode plate of the capacitor, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to cover the surfaces of the dielectric layers on two sides, the third metal layer is arranged on the top of the second metal layer and forms a lower electrode plate of the capacitor with the second metal layer, and the passivation layer covers the third metal layer and extends to cover the surfaces of the side wall protection layers on two sides.
Optionally, the thickness is 100-1000 nm; the third metal layer comprises a TiW layer, an Au seed layer, an Au electroplated layer and a Ti layer which are sequentially stacked, wherein the thickness of the TiW layer is 60-600 nm, the thickness of the Au seed layer is 120-600 nm, the thickness of the Au electroplated layer is 2-6 microns, and the thickness of the Ti layer is 2-10 nm.
The capacitor structure of the compound semiconductor device comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer and a third metal layer which are sequentially arranged; the first metal layer is arranged on the substrate to form a capacitor bottom plate, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to the surface of the dielectric layer covering two sides, the third metal layer is arranged on the top of the second metal layer and extends to one side to form a metal bridge structure, and the second metal layer and the third metal layer form the capacitor bottom plate.
Optionally, the second metal layer is a Ti/Pt/Au/Ti laminated layer, and the thickness of the second metal layer is 100-1000 nm; the third metal layer comprises a TiW layer, an Au seed layer and an Au electroplating layer which are sequentially stacked, the thickness of the TiW layer is 60-600 nm, the thickness of the Au seed layer is 120-600 nm, and the thickness of the Au electroplating layer is 2-6 microns.
The invention has the beneficial effects that: the structure of a charge concentration area in the capacitor is improved through the arrangement of the second metal layer, the side wall protection layer and the third metal layer, the stress effect is reduced, the reliability is improved, and the service life of the device is prolonged; the capacitor structure is suitable for different types of capacitor structures, and the practicability is high.
Drawings
FIG. 1 is a flow chart of the manufacturing process of embodiment 1 of the present invention, which is a schematic structural diagram obtained by the steps in sequence;
FIG. 2 is a schematic structural view of embodiment 1 of the present invention;
FIG. 3 is a flow chart of the manufacturing process of embodiment 2 of the present invention, which is a schematic structural diagram obtained by the steps in sequence;
FIG. 4 is a schematic structural view of example 2 of the present invention;
FIG. 5 is a flowchart illustrating a manufacturing process according to embodiment 3 of the present invention, wherein the diagram sequentially shows a schematic structure obtained by each step;
fig. 6 is a schematic structural diagram of embodiment 3 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The relative positions of elements in the figures described herein are understood by those skilled in the art to refer to relative positions of elements, and thus all elements may be reversed to represent the same, all falling within the scope of the disclosure. In addition, the number of the elements and the structure shown in the drawings is only an example, and the number is not limited thereto, and can be adjusted according to the design requirement.
Example 1
Referring to fig. 1, a method for fabricating a capacitor structure of a compound semiconductor device includes:
1) a resist is coated on a compound semiconductor substrate 1 (e.g., GaAs) on which a device process has been completed, and exposure and development are performed to form a pattern required for metal evaporation. Depositing metal by evaporation or sputtering, stripping the photoresist by chemical liquid such as N-methyl pyrrolidone and the like, and leaving a required pattern to form a first metal layer 2, wherein the first metal layer 2 forms a capacitor lower electrode plate. The first metal layer 2 can be, for example, a Ti/Pt/Au/Ti stacked layer with a total thickness of 100-1000 nm, wherein Ti is 3-50 nm, and Pt is 20-50 nm.
2) A layer of silicon nitride is deposited by PECVD as the capacitor dielectric layer 3, with a thickness of 50nm to 200 nm.
3) Coating photoresist, exposing and developing to form a pattern required by metal evaporation, depositing metal by evaporation or sputtering, stripping the photoresist by chemical liquid such as N-methylpyrrolidone, and leaving the required pattern to form the second metal layer 4. The second metal layer 4 is located on the surface of the dielectric layer 3 above the first metal layer 2 and has a smaller width than the first metal layer 2, and is preferably located in the middle of the first metal layer 2. The second metal layer 4 can be, for example, a Ti/Pt/Au/Ti stacked layer with a total thickness of 100-1000 nm, wherein Ti is 3-50 nm and Pt is 20-50 nm.
4) Depositing a layer of silicon nitride as a side wall protective layer 5 in a PECVD (plasma enhanced chemical vapor deposition) mode, wherein the thickness is 100nm to 500 nm; coating photoresist, exposing and developing to form a pattern required by dry etching, performing dry etching on the side wall protection layer 5 to form an etching window 5a by windowing the top of the second metal layer 4, and stripping the photoresist by using chemical liquid such as N-methylpyrrolidone.
5) Coating Polyimide (PI) on the surface of the silicon nitride as an insulating layer 6, and hardening the polyimide after baking; after coating, exposing and developing the photoresist, defining the position of the capacitor through hole, etching the polyimide by ICP or RIE to form the capacitor through hole 6a corresponding to the etching window 5a, and stripping the photoresist by chemical liquid such as N-methyl pyrrolidone and the like to leave a required pattern.
6) After coating, exposing and developing the photoresist, defining the line position of the third metal layer 7, depositing metal by evaporation or sputtering, stripping the photoresist by chemical liquid such as N-methylpyrrolidone and the like, and leaving the required metal pattern to form the third metal layer 7. The third metal layer 7 is located in the capacitor via 6a and contacts the second metal layer 4, and the third metal layer 7 is higher than the surface of the insulating layer 6. The third metal layer 7 and the second metal layer 4 form a capacitor upper plate. The third metal layer 7 can be, for example, a Ti/Pt/Au/Ti laminated layer with a total thickness of 1000-5000 nm, wherein Ti: 3-50 nm, Pt: 20 to 50 nm.
7) A layer of 200nm to 1000nm silicon nitride is deposited as a passivation layer 8 by PECVD.
Referring to fig. 2, the compound semiconductor device capacitor structure of the present embodiment includes a compound semiconductor substrate 1, a first metal layer 2, a dielectric layer 3, a second metal layer 4, a sidewall protection layer 5, an insulating layer 6, a third metal layer 7 and a passivation layer 8, which are sequentially disposed; the first metal layer 2 is arranged on the substrate 1 and forms a capacitor lower electrode plate, the dielectric layer 3 covers the first metal layer 2 and the substrate 1, the second metal layer 4 is arranged on the surface of the dielectric layer 3 above the first metal layer 2, the width of the dielectric layer is smaller than that of the first metal layer 2, the side wall protection layer 5 covers the side wall of the second metal layer 2 and extends to the surfaces of the dielectric layers 3 on two sides, the insulation layer 6 is coated on the side wall protection layer 5, a capacitor through hole is formed in the top of the second metal layer 4, the third metal layer 7 is arranged in the capacitor through hole and is higher than the surface of the insulation layer 6, the second metal layer 4 and the third metal layer 7 form a capacitor lower electrode plate, and the passivation layer 8 covers the surfaces of the third metal layer 7 and the insulation layer 6. Through the arrangement, the stress concentration phenomenon generated by the junction of metal, silicon nitride and PI in the charge dense area where the lower polar plate is in contact with the dielectric layer is avoided, the stress is reduced, the aging and burning are avoided, and the service life is prolonged.
The capacitor structure of the compound semiconductor device of the embodiment is suitable for manufacturing HBT (heterojunction bipolar transistor) with insulating layer process Polyimide (Polyimide) and other compound semiconductor devices.
Example 2
Referring to fig. 3, a method for fabricating a capacitor structure of a compound semiconductor device includes:
the steps 1) to 4) refer to example 1, and are not described in detail.
5) And preparing a TiW layer 71 and a gold seed layer 72 on the surface of the structure by using a physical vapor deposition method. The TiW layer 71 is between 60nm and 600 nm; the gold seed layer 72 is between 120nm and 600nm, preferably between 200nm and 500 nm.
6) The pattern of the Au plating layer 73 is defined by negative photoresist with angle between 75 and 85 degrees and thickness between 3 μm and 8 μm, and then a layer of Au is plated on the surface of the Au seed layer 72 by electroplating method, and the thickness of the Au plating layer 73 can be from 2 μm to 6 μm. The photoresist is stripped off with a chemical solution such as N-methylpyrrolidone, leaving the desired metal pattern.
7) And removing the exposed gold seed layer 72 by using a reverse electroplating method and etching the TiW layer 71 by using a dry etching method, wherein the rest TiW layer 71 is positioned in the etching window 5a and extends to the surface of the side wall protection layer 5 covering the edge of the etching window.
8) Defining the pattern of the top Ti layer 74 with negative photoresist with thickness of 3-8 μm, depositing a Ti layer with thickness of 2-10 nm by evaporation, stripping the photoresist with chemical liquid such as N-methylpyrrolidone, etc. to leave the required metal pattern. The TiW layer 71/Au seed layer 72/Au electroplated layer 73/Ti layer 74 form the third metal layer 7 ', and the third metal layer 7' and the second metal layer 4 form the upper plate of the capacitor.
9) A layer of 200nm to 1000nm silicon nitride is deposited as a passivation layer 8 by PECVD.
Referring to fig. 4, the compound semiconductor device capacitor structure of the present embodiment includes a compound semiconductor substrate 1, a first metal layer 2, a dielectric layer 3, a second metal layer 4, a sidewall protection layer 5, a third metal layer 7' and a passivation layer 8, which are sequentially disposed; the first metal layer 2 is arranged on the substrate 1 and forms a capacitor bottom plate, the dielectric layer 3 covers the first metal layer 2 and the substrate 1, the second metal layer 4 is arranged on the surface of the dielectric layer 3 above the first metal layer 2, the width of the dielectric layer 3 is smaller than that of the first metal layer 2, the side wall protection layer 5 covers the side wall of the second metal layer 4 and extends to cover the surfaces of the dielectric layers 3 on two sides, the third metal layer 7 'is arranged on the top of the second metal layer 4 and forms a capacitor bottom plate with the second metal layer 4, and the passivation layer 8 covers the third metal layer 7' and extends to cover the surfaces of the side wall protection layers 5 on two sides. In this embodiment, the multilayer structure of the third metal layer 7' is provided to reduce the problem of TiW etch back generated in the electrode upper plate manufacturing process in the existing manufacturing process, and enhance the reliability of the capacitor.
The capacitor structure of the compound semiconductor device of the embodiment is suitable for the technological process of manufacturing the capacitor upper electrode plate by using an electroplating process in the manufacturing process of HBT and other compound semiconductor devices.
Example 3
Referring to fig. 5, a method for fabricating a capacitor structure of a compound semiconductor device includes:
the steps 1) to 4) refer to example 1, and are not described in detail.
5) A photoresist layer 9 is formed by coating, exposing and developing the photoresist, and the position of the capacitor via hole 9a corresponding to the etching window 5a is defined.
6) A TiW layer 71 and a gold seed layer 72 are prepared by physical vapor deposition. The TiW layer 71 is between 60nm and 600 nm; the gold seed layer 72 is between 120nm and 600nm, preferably between 200nm and 500 nm.
7) And coating a layer of photoresist, exposing and developing, defining the pattern of the Au electroplated layer 73, electroplating a layer of gold on the surface of the gold seed layer 72 by using an electroplating method, wherein the thickness of the Au electroplated layer 73 can be 2-6 mu m, stripping the photoresist by using chemical liquid such as N-methylpyrrolidone and the like to leave a required metal pattern, and obtaining the Au electroplated layer 73 which is arranged in the capacitor through hole 9a and extends to the surface of the photoresist layer 9 on one side.
8) Removing the exposed gold seed layer 72 by a reverse electroplating method and etching the exposed TiW layer 71 by a dry etching method;
9) stripping the photoresist layer 9 with chemical solution such as N-methyl pyrrolidone to leave the desired metal pattern, the TiW layer 71/Au seed layer 72/Au plating layer 73 forms a third metal layer 7 ", and the third metal layer 7" forms a metal bridge structure after stripping the photoresist layer 9. The third metal layer 7' and the second metal layer 4 form a capacitor upper plate.
Referring to fig. 6, the compound semiconductor device capacitor structure of the present embodiment includes a compound semiconductor substrate 1, a first metal layer 2, a dielectric layer 3, a second metal layer 4, a sidewall protection layer 5, and a third metal layer 7 ″ sequentially disposed; the first metal layer 2 is arranged on the substrate 1 to form a capacitor bottom plate, the dielectric layer 3 covers the first metal layer 2 and the substrate 1, the second metal layer 4 is arranged on the surface of the dielectric layer 3 above the first metal layer 2, the width of the dielectric layer 3 is smaller than that of the first metal layer 2, the side wall protection layer 5 covers the side wall of the second metal layer 4 and extends to cover the surfaces of the dielectric layers 3 on two sides, the third metal layer 7 'is arranged on the top of the second metal layer 4 and extends to one side to form a metal bridge structure, and the second metal layer 4 and the third metal layer 7' form the capacitor bottom plate.
The compound semiconductor device capacitor structure of the embodiment is suitable for the technological process of using the air bridge structure for the capacitor upper electrode plate in the manufacturing process of HBT and other compound semiconductor devices.
In addition, it will be appreciated by those skilled in the art that the dielectric layer in the above embodiments may also be SiN/SiO2The composite film such as/SiN, etc. can be replaced by H in dry TiW etching2O2And (4) replacing by wet etching.
The above embodiments are only used to further illustrate the compound semiconductor device capacitor structure and the method for fabricating the same of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the scope of the technical solution of the present invention.
Claims (12)
1. A method for manufacturing a capacitor structure of a compound semiconductor device is characterized by comprising the following steps:
1) providing a compound semiconductor substrate, and forming a first metal layer on the substrate to form a capacitor lower electrode plate;
2) depositing a dielectric layer on the surface of the structure formed in the step 1), wherein the thickness of the dielectric layer is 50-200 nm; the dielectric layer is silicon nitride or SiN/SiO2a/SiN laminated composite film;
3) forming a second metal layer on the surface of the dielectric layer above the first metal layer, wherein the width of the second metal layer is smaller than that of the first metal layer, and the thickness of the second metal layer is 100-1000 nm;
4) depositing a side wall protection layer on the surface of the structure formed in the step 3), wherein the thickness of the side wall protection layer is 100-500 nm, and the side wall protection layer is made of silicon nitride;
5) etching the side wall protection layer on the top of the second metal layer to form an etching window;
6) and forming a third metal layer, wherein the third metal layer is in contact with the second metal layer at the etching window, and the third metal layer and the second metal layer form an upper polar plate of the capacitor.
2. The method of manufacturing according to claim 1, wherein: coating an insulating material on the surface of the structure formed in the step 5) to form an insulating layer, and removing the insulating layer above the etching window to form a capacitor through hole; in step 6), the third metal layer is formed in the capacitor through hole and higher than the insulating layer.
3. The method of manufacturing according to claim 1, wherein: and 6) sequentially forming a TiW layer and an Au seed layer in the etching window through physical vapor deposition, wherein the TiW layer extends to the surface of the side wall protection layer covering the edge of the etching window, then sequentially electroplating the Au seed layer to form an Au electroplating layer, and performing evaporation plating on the Au electroplating layer to form a Ti layer, wherein the TiW layer/the Au seed layer/the Au electroplating layer/the Ti layer form the third metal layer.
4. The method of manufacturing according to claim 3, wherein: and defining the pattern of the Au electroplated layer by adopting a negative photoresist, wherein the angle of the negative photoresist is 75-85 degrees, and the thickness of the negative photoresist is 3-8 mu m.
5. The manufacturing method according to claim 2 or 3, characterized in that: and further comprising a step of depositing a passivation layer on the surface of the structure formed in the step 6), wherein the thickness of the passivation layer is 200-1000 nm.
6. The method of manufacturing according to claim 1, wherein: coating a light resistance layer on the surface of the structure formed in the step 5), and removing the light resistance layer above the etching window to form a capacitor through hole; in the step 6), the third metal layer is formed in the capacitor through hole and extends to the surface of the photoresist layer towards one side, and then the photoresist layer is removed to form a metal bridge structure.
7. The method of manufacturing according to claim 6, wherein: and 6) sequentially forming a TiW layer and an Au seed layer on the surfaces of the capacitor through hole and the photoresist layer on one side of the capacitor through hole through physical vapor deposition, and electroplating on the Au seed layer to form an Au electroplated layer, wherein the TiW layer/the Au seed layer/the Au electroplated layer form the third metal layer.
8. A compound semiconductor device capacitor structure, characterized by: the semiconductor device comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer, an insulating layer, a third metal layer and a passivation layer which are sequentially arranged; the first metal layer is arranged on the substrate and forms a lower electrode plate of the capacitor, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to the surface of the dielectric layer covering two sides, the insulating layer is coated on the side wall protection layer, a capacitor through hole is formed in the top of the second metal layer, the third metal layer is arranged in the capacitor through hole and is higher than the surface of the insulating layer, the second metal layer and the third metal layer form a lower electrode plate of the capacitor, and the passivation layer covers the third metal layer and the surface of the insulating layer.
9. A compound semiconductor device capacitor structure, characterized by: the semiconductor device comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer, a third metal layer and a passivation layer which are sequentially arranged; the first metal layer is arranged on the substrate and forms a lower electrode plate of the capacitor, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to cover the surfaces of the dielectric layers on two sides, the third metal layer is arranged on the top of the second metal layer and forms a lower electrode plate of the capacitor with the second metal layer, and the passivation layer covers the third metal layer and extends to cover the surfaces of the side wall protection layers on two sides.
10. The capacitive structure of claim 9, wherein: the second metal layer is a Ti/Pt/Au/Ti laminated layer, and the thickness of the second metal layer is 100-1000 nm; the third metal layer comprises a TiW layer, an Au seed layer, an Au electroplated layer and a Ti layer which are sequentially stacked, wherein the thickness of the TiW layer is 60-600 nm, the thickness of the Au seed layer is 120-600 nm, the thickness of the Au electroplated layer is 2-6 microns, and the thickness of the Ti layer is 2-10 nm.
11. A compound semiconductor device capacitor structure, characterized by: the composite semiconductor device comprises a compound semiconductor substrate, a first metal layer, a dielectric layer, a second metal layer, a side wall protection layer and a third metal layer which are sequentially arranged; the first metal layer is arranged on the substrate to form a capacitor bottom plate, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on the surface of the dielectric layer above the first metal layer, the width of the second metal layer is smaller than that of the first metal layer, the side wall protection layer covers the side wall of the second metal layer and extends to the surface of the dielectric layer covering two sides, the third metal layer is arranged on the top of the second metal layer and extends to one side to form a metal bridge structure, and the second metal layer and the third metal layer form the capacitor bottom plate.
12. The capacitive structure of claim 11, wherein: the second metal layer is a Ti/Pt/Au/Ti laminated layer, and the thickness of the second metal layer is 100-1000 nm; the third metal layer comprises a TiW layer, an Au seed layer and an Au electroplating layer which are sequentially stacked, the thickness of the TiW layer is 60-600 nm, the thickness of the Au seed layer is 120-600 nm, and the thickness of the Au electroplating layer is 2-6 microns.
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| CN111128970B (en) * | 2019-12-20 | 2022-05-10 | 厦门市三安集成电路有限公司 | Capacitor structure and method of making the same |
| CN113690369A (en) * | 2021-07-08 | 2021-11-23 | 深圳镓芯半导体科技有限公司 | Compound Semiconductor Capacitors |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103155098A (en) * | 2010-10-05 | 2013-06-12 | 国际商业机器公司 | 3D via capacitor with a floating conductive plate for improved reliability |
| CN104205389A (en) * | 2012-03-16 | 2014-12-10 | 高通Mems科技公司 | High capacitance density metal-insulator-metal capacitors |
| CN105097815A (en) * | 2014-05-23 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Capacitor structure and manufacturing method thereof, and semiconductor memory including capacitor structure |
| CN206022345U (en) * | 2016-08-16 | 2017-03-15 | 厦门市三安集成电路有限公司 | A kind of semiconductor structure with composite protection layer |
| CN107275380A (en) * | 2017-06-14 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of metal level of compound semiconductor and preparation method thereof |
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| KR101665669B1 (en) * | 2010-03-04 | 2016-10-13 | 삼성전자주식회사 | Semiconductor devices and methods of forming the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103155098A (en) * | 2010-10-05 | 2013-06-12 | 国际商业机器公司 | 3D via capacitor with a floating conductive plate for improved reliability |
| CN104205389A (en) * | 2012-03-16 | 2014-12-10 | 高通Mems科技公司 | High capacitance density metal-insulator-metal capacitors |
| CN105097815A (en) * | 2014-05-23 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Capacitor structure and manufacturing method thereof, and semiconductor memory including capacitor structure |
| CN206022345U (en) * | 2016-08-16 | 2017-03-15 | 厦门市三安集成电路有限公司 | A kind of semiconductor structure with composite protection layer |
| CN107275380A (en) * | 2017-06-14 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of metal level of compound semiconductor and preparation method thereof |
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