CN108365847B - Calibration method for parasitic capacitance of charge type SAR-ADC - Google Patents

Abstract

The invention discloses a method for calibrating parasitic capacitance of a charge-type SAR-ADC. The charge-type SAR-ADC includes an LSB capacitor array, and all upper plates of the LSB capacitor array are connected to one end of a first compensation circuit, and the first The other end of the compensation circuit is connected to any constant potential. The first compensation circuit is composed of a first fixed capacitor C _dl and a first adjustable capacitor C _dl ' in parallel, and the nonlinear error of the SAR-ADC is adjusted by adjusting the first compensation circuit. In the LSB capacitor array, the unit capacitance value is C _u , and there are L bits in total. From the low order to the high order, the relationship is increased by 2 times, and the highest capacitance value is 2 ^L‑1 C _u . When the total capacitance value of the LSB capacitor array is C _Lt , the following relation is established: C _Lt =(2 ^L -1)·C _u +C _dl +C _dl '. The calibration method for the parasitic capacitance of the charge-type SAR-ADC can achieve high linearity and gain adjustment accuracy, and is especially suitable for the design of high-precision ADCs.

Description

Calibration Method for Charge-Type SAR-ADC Parasitic Capacitance

technical field

The invention relates to the field of chip design, in particular to a calibration method for the parasitic capacitance of a charge-type SAR-ADC.

Background technique

The conversion between analog and digital signals is an important part of signal processing. The natural sound, light, electricity and other analog signals must be converted into digital signals by an analog-to-digital converter (ADC) before they can be further converted and processed by the digital system. Different systems have different requirements for ADC indicators, and different ADC indicators require corresponding ADC structures to adapt to them. With the reduction of integrated circuit process size and the improvement of manufacturing process precision, the most widely used ADC structures are SAR-ADC, sigma-delta ADC and pipeline ADC. The successive approximation converter (SAR-ADC) has the comprehensive advantages of medium speed, medium precision, low power consumption and low cost, and has been applied in a wider field.

The basic structure of a SAR-ADC consists of a comparator, a digital-to-analog converter (DAC), and a successive approximation controller (SAR). It continuously compares the sampled signal with the known voltage, completes one-bit conversion in one cycle, and completes N-bit conversion in N cycles. The resolution and conversion speed of SAR-ADC are contradictory. The accuracy of the ADC is mainly determined by the accuracy of the digital-to-analog converter. There are many structures of digital-to-analog converters, and the most widely used is the charge-type digital-to-analog converter, as shown in Figure 1. The working process of the so-called charge-based digital-to-analog converter is accomplished through the redistribution of charges in the binary proportional division capacitor array. The voltage ratio also realizes the conversion between analog and digital. Both the accuracy of a charge-type DAC and the required area are factors limiting the number of bits, where accuracy refers to the proportional accuracy of the capacitance. The proportional accuracy of the capacitor is positively related to the area of the capacitor. To achieve higher proportional accuracy, a larger area must be consumed. Under the existing process conditions, the capacitance ratio accuracy can be as low as 0.1%, and the 0.1% capacitance ratio accuracy is only applicable when the capacitance ratio is close to 1. When the ratio increases, the accuracy will decrease accordingly. Under the same conditions, the charge-type DAC without digital calibration can generally achieve 10-bit accuracy, that is to say, the ratio between the maximum capacitance and the minimum capacitance in the binary proportional capacitor array is 512:1. In order to keep the matching accuracy from decreasing as the DAC accuracy increases, a high-precision DAC can be divided into multiple sub-DACs, and each sub-DAC is connected by scaling capacitors, as shown in Figure 2. MSB and LSB are M-bit and L-bit sub-DACs respectively. Capacitor C _a is a scaling capacitor, and MSB and LSB are connected to form an M+L-bit DAC. In order to ensure the matching accuracy of each sub-DAC, the number of bits of a single sub-DAC should not be too high. When the accuracy of the entire DAC is high, in order to ensure the matching accuracy of a single sub-DAC, the entire capacitor array can be divided into multiple segments and connected through multiple scaling capacitors. In order to ensure the linear relationship between each segmented DAC, the following formula needs to be satisfied:

C _a ·C _eq /(C _a +C _eq )=k·C _u

Ideally, capacitor segmentation solves the problem that the matching accuracy decreases with the increase of DAC accuracy, but in non-ideal cases, there is parasitic capacitance between the upper and lower plates of the capacitor and the plate, as shown in Figure 3 . Top and Bottom are the two ends of the capacitor, and the Shield end is the shielding end of the capacitor (used to shield the interference between the capacitor plate and the substrate) or the substrate. C _pa is the trace parasitic capacitance at both ends of Top and Bottom. C _p1 and C _p2 are the parasitic capacitances between Top/Shield and Bottom/Shield, respectively. Since the parasitic capacitance is not considered in the design, and the parasitic capacitance will change with the change of the process angle, the existence of the parasitic capacitance will cause nonlinearity among the segmented DACs.

In order to adjust the nonlinearity between each segmented capacitance, the usual practice is to introduce an adjustable capacitance C _a ' into the circuit, as shown in Figure 4. The adjustment of C _a ' is to connect two points A and B or disconnect from two points A and B by means of MOS switch or FIB. Since the capacitance parasitics of the same batch are the same, the variable capacitance can be linearly adjusted through the measurement results after tape-out, so that the adjusted sub-DACs meet the linearity requirements.

It is easy to find the following shortcomings in the existing technology through the research on the above existing technology and the consideration of the actual circuit system application environment:

(1) In general, in order to reduce the parasitic capacitance of the scaling capacitor, the value of the scaling capacitor is relatively small. When the ADC has high requirements for linearization, the precision of the adjustable part of the scaling capacitor needs to be high enough. In order to achieve a high enough capacitance adjustment precision, a small enough capacitance is required. When the capacitance is small enough to be equivalent to the parasitic capacitance of the adjustment switch, It will not be possible to adjust to higher accuracy, resulting in limited adjustment accuracy.

(2) When the scaling capacitor is adjusted by MOS switch, point A or point B will inevitably be connected to one end of the adjustment switch, and the voltages of points A and B will change drastically during the conversion process, and the change in voltage will cause adjustment. The drastic change of the parasitic capacitance of the switch and the changes of the parasitic capacitance of A and B will seriously affect the accuracy and gain of the ADC itself.

(3) When using the FIB method to adjust the scaling capacitor, it is necessary to adjust the FIB of each chip. Since the FIB itself has economic and time costs, this method will greatly increase the cost of the chip and also seriously limit the chip's performance. capacity.

The information disclosed in this Background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a calibration method for the parasitic capacitance of a charge-type SAR-ADC, which is used in the design of a high-precision SAR-ADC.

In order to achieve the above object, the present invention provides a calibration method for the parasitic capacitance of a charge-type SAR-ADC, the charge-type SAR-ADC includes an LSB capacitor array, and all upper plates of the LSB capacitor array and the first compensation circuit are connected. One end is connected, the other end of the first compensation circuit is connected to any constant potential, the first compensation circuit is composed of a first fixed capacitor C _dl and a first adjustable capacitor C _dl ' in parallel, and the SAR-ADC is adjusted by adjusting the first compensation circuit. nonlinear error. The unit capacitance value in the LSB capacitor array is C _u , with a total of L bits, which are increased by a factor of 2 from the low order to the high order, and the highest capacitance value is 2 ^L-1 C _u . When the total capacitance value of the LSB capacitor array is C _Lt , the following relation is established: C _Lt =(2 ^L -1)·C _u +C _dl +C _dl '.

Preferably, in the above technical solution, the first adjustable capacitor C _dl ' is composed of a plurality of capacitor bank circuits in parallel. Each of the capacitor group circuits in the first adjustable capacitor C _dl ' is composed of two capacitors connected in series, and one of the capacitors is connected in parallel with a gate switch.

Preferably, in the above technical solution, the capacitors in each of the capacitor bank circuits in the first adjustable capacitors have the same value or different values.

Preferably, in the above technical solution, the charge-type SAR-ADC further includes an MSB capacitor array, and all upper plates of the MSB capacitor array are connected to one end of the second compensation circuit, and the other end of the second compensation circuit is connected One channel is connected to any constant potential through the gating switch, and the other is connected to the sampling signal through another gating switch. The second compensation circuit is composed of a second fixed capacitor and a second adjustable capacitor in parallel. The overall gain of the SAR-ADC is adjusted by adjusting the second compensation circuit. The unit capacitance value in the MSB capacitor array is C _u , with a total of M bits, which are increased by a factor of 2 from the low order to the high order, and the highest capacitance value is 2 ^M-1 C _u .

Preferably, in the above technical solution, the second adjustable capacitor is composed of N capacitor group circuits in parallel. Each capacitor group circuit in the second adjustable capacitor is composed of two capacitors connected in series, one of which is connected in parallel with a gate switch.

Preferably, in the above technical solution, the capacitors in each of the capacitor bank circuits in the second adjustable capacitors have the same value or different values.

Preferably, in the above technical solution, the charge-type SAR-ADC further includes a comparator. The sampling of the charge-type SAR-ADC is only performed for the MSB capacitor array. During the conversion process, the lower plates of each weight capacitor are connected to the reference potential one after another according to the judgment result of the comparator. When the ratio of the total capacitance to the reference potential is equal to 1, the gain of the charge-type SAR-ADC is 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is greater than 1, the gain of the charge-type SAR-ADC is less than 1. 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is less than 1, the gain of the charge-type SAR-ADC is greater than 1.

Compared with the prior art, the present invention has the following beneficial effects: high linearity and gain adjustment precision can be achieved, and it is especially suitable for the design of high precision ADC.

Description of drawings

FIG. 1 is a circuit frame diagram of a charge-type SAR-ADC according to the prior art.

FIG. 2 is a circuit block diagram of a charge-type SAR-ADC segmented by a DAC according to the prior art.

FIG. 3 is a schematic diagram of capacitance parasitics according to the prior art.

FIG. 4 is a circuit block diagram of a charge-type SAR-ADC with DAC segmentation and parasitic capacitance calibration according to the prior art.

FIG. 5 is a SAR-ADC circuit frame diagram of a method for calibrating parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention.

FIG. 6 is a structural diagram of an adjustable capacitance of a method for calibrating parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprising" or its conjugations such as "comprising" or "comprising" and the like will be understood to include the stated elements or components, and Other elements or other components are not excluded.

The purpose of the present invention is to propose a calibration method for the parasitic capacitance of the charge-type SAR-ADC. As shown in Figure 5. FIG. 5 is a SAR-ADC circuit frame diagram of a method for calibrating parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention.

First, on the basis of the circuit in which only the MSB capacitor participates in the sampling, a fixed capacitor and an adjustable capacitor are respectively introduced to adjust the linearity error and gain error caused by the parasitic capacitance of the A and B points. Among them, C _dl and C _dl ' are used to adjust the linear relationship between the sub-DACs of each segment, and C _dm and C _dm ' are used to adjust the overall gain of the ADC.

The upper plates of the first fixed capacitor C _dl and the first adjustable capacitor C _dl ' are connected to point A, and the lower plates are connected to VCM, where VCM is an arbitrary constant potential. The introduction of C _dl makes the two-terminal DAC of the scaling capacitor basically satisfy the linear relationship. However, due to the parasitic capacitance of the plate in each capacitor, only the introduction of C _dl cannot satisfy the linear relationship between the sub-DACs under all process corners. Therefore, it is necessary to introduce C _dl ' to adjust the parasitic capacitance changes in different process corners. .

In order to ensure the linear relationship between the segmented DACs, it is necessary to maintain twice the weight relationship between the adjacent bits at both ends of the scaling capacitor C _a , that is, the weight of the MSB highest bit is twice the weight of the LSB lowest bit. It can be simply understood as inputting step voltages of equal amplitude at points ① and ②, so that the voltage changes caused by point B are dV ₁ and dV ₂ respectively, and requires:

dV ₂ =2dV ₁ Equation 1

In order to meet the requirements of Equation 2, the value of each capacitor needs to satisfy the following relationship:

k·(C _a +C _Lt )=2 ^L ·C _a Formula 2

in,

C _Lt = (2 ^L -1)·C _u +C _dl +C _dl ' Equation 3

When the parasitic or mismatch of the capacitance causes nonlinearity between MSB and LSB, the nonlinearity can be compensated by adjusting C _dl and C _dl ' to make it meet the linearity requirement. C _dl is the standard value of the design, and the adjustment of C _dl ' is used to offset the nonlinear error caused by non-ideal factors such as process and parasitics.

The upper plates of the second fixed capacitor C _dm and the second adjustable capacitor C _dm ' are connected to point B, and the lower plates are respectively connected to V _IN and V _CM through two switches, where V _CM is an arbitrary constant potential.

In the present invention, the sampling of the ADC is performed only for the MSB bit. During the conversion process, the lower plates of each weight capacitor are connected to the reference potential one after another according to the judgment result of the comparator. When the ratio of the sampling capacitance to the total capacitance connected to the reference potential is 1, the gain of the ADC is 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is greater than 1, the gain of the ADC is less than 1; When the ratio of the total capacitance connected to the reference potential is less than 1, the gain of the ADC is greater than 1; therefore, the gain of the ADC can be directly adjusted by adjusting the value of the sampling capacitor without affecting the linearity of the ADC. The sampling capacitor can be adjusted by adjusting C _dm and C _dm ', C _dm is the standard value of the design, and the adjustment of C _dm ' is used to offset the gain error caused by non-ideal factors such as process and parasitics.

FIG. 6 is a structural diagram of an adjustable capacitance of a method for calibrating parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention. The two ends of Top and Bottom are the upper and lower plates of the adjustable capacitor, respectively. The upper plates of C ₁ , C ₂ ... C _n are connected to the Top ends, and the lower plates of C ₁ , C ₂ , ... C _n are respectively connected to C ₁₁ , C _The upper plates _{of 21} ... _Cn1 are connected to S1, S2... _Sn , the lower plates _{of C11} , _C21 ... _Cn1 are connected to the Bottom, and the nodes S1, _S2 ... _Sn are respectively connected through switches _SW1 , SW ₂ ...SW _n are connected to the Bottom side.

When the SW ₁ switch is closed, the capacitor C ₁ is connected to both ends of Top and Bottom; when the SW ₁ switch is open, the capacitor C ₁ ·C ₁₁ /(C ₁ +C ₁₁ ) is connected to both ends of the Top and Bottom; ₂ When the switch is closed, the capacitor C ₂ is connected to both ends of Top and Bottom. When the SW ₂ switch is open, the capacitor C ₂ ·C ₂₁ /(C ₂ +C ₂₁ ) Top and Bottom ends; and so on, when SWn When the switch is closed, the capacitor C _{n is} connected to both ends of Top and Bottom. When the switch of SW _n is turned off, the capacitor C _n ·C _n1 /(C _n +C _n1 ) is connected to both ends of Top and Bottom; through the above analysis, it can be calculated , the adjustment range of the adjustable capacitor C _tot is:

C ₁ ·C ₁₁ /(C ₁ +C ₁₁ )+C ₂ ·C ₂₁ /(C ₂ +C ₂₁ )+…+C _n ·C _n1 /(C _n +C _n1 )≤C _tot ≤C ₁ + C ₂ +…+C _n

When the process angle is determined, the parasitic capacitance is also determined. By adjusting the value of the adjustable capacitor C _dl ' under different process angles, the influence of the parasitic capacitance on the linear relationship between the sub-DACs can be eliminated. By adjusting the C _dm The value of ' can adjust the gain of the ADC.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many changes and modifications are possible in light of the above teachings. The exemplary embodiments were chosen and described for the purpose of explaining certain principles of the invention and their practical applications, to thereby enable one skilled in the art to make and utilize various exemplary embodiments and various different aspects of the invention. Choose and change. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims (6)

1. A calibration method for parasitic capacitance of a charge type SAR-ADC (synthetic aperture radar-analog converter), wherein the charge type SAR-ADC comprises an LSB (least significant bit) capacitor array, and is characterized in that all upper polar plates of the LSB capacitor array are connected with one end of a first compensation circuit, the other end of the first compensation circuit is connected with any constant potential, and the first compensation circuit is formed by a first fixed capacitor C_dlAnd a first tunable capacitor C_dl' a parallel component, adjusting a non-linearity error of the SAR-ADC by adjusting the first compensation circuit,

the unit capacitance value in the LSB capacitor array is C_uL bits, which are increased by 2 times from low bit to high bit, and the highest bit capacitance is 2^L-1C_uAnd when the total capacitance value of the LSB capacitor array is C_LtIf so, the following relationship holds:

C_Lt＝(2^L-1)·C_u+C_dl+C_dl′；

the charge type SAR-ADC also comprises an MSB capacitor array, all upper polar plates of the MSB capacitor array are connected with one end of a second compensation circuit, one path of the other end of the second compensation circuit is connected with any constant potential through a gating switch, the other path of the other end of the second compensation circuit is connected with a sampling signal through another gating switch, the second compensation circuit is formed by connecting a second fixed capacitor and a second adjustable capacitor in parallel, the overall gain of the SAR-ADC is adjusted by adjusting the second compensation circuit,

the unit capacitance value of the MSB capacitor array is C_uThe total M bits are increased by 2 times from the low bit to the high bit, and the highest bit capacitance value is 2^M-1C_u。

2. The SAR-ADC parasitic capacitance for charge type of claim 1In a calibration method, characterized in that said first adjustable capacitance C_dl' is composed of a plurality of capacitor bank circuits connected in parallel,

the first adjustable capacitor C_dl' each of the capacitor bank circuits is composed of two capacitors connected in series, and one of the capacitors is connected in parallel with one of the gate switches.

3. The calibration method for parasitic capacitance of charge-type SAR-ADC according to claim 2, wherein the capacitance in each of said capacitor bank circuits of said first tunable capacitor is equal or different.

4. The calibration method for parasitic capacitance of charge-type SAR-ADC of claim 1, wherein the second adjustable capacitance is composed of N capacitance bank circuits in parallel,

each capacitor bank circuit in the second adjustable capacitor is formed by connecting two capacitors in series, and one capacitor is connected with one gating switch in parallel.

5. The calibration method for parasitic capacitance of charge-type SAR-ADC of claim 4, wherein the capacitance in each of the capacitance group circuits in the second adjustable capacitance is the same or different.

6. The method of claim 1, wherein the SAR-ADC further comprises a comparator, wherein the sampling of the SAR-ADC is performed only for the MSB capacitor array, during the conversion, the lower plate of each weight capacitor is sequentially connected to a reference potential according to the judgment result of the comparator, and when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is equal to 1, the gain of the SAR-ADC is 1; when the ratio of the sampling capacitor to the total capacitor connected to the reference potential is greater than 1, the gain of the charge type SAR-ADC is less than 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is less than 1, the gain of the charge type SAR-ADC is more than 1.

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