CN108364928B - Integrated circuit packaging structure and processing method thereof - Google Patents
Integrated circuit packaging structure and processing method thereof Download PDFInfo
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- CN108364928B CN108364928B CN201810320806.7A CN201810320806A CN108364928B CN 108364928 B CN108364928 B CN 108364928B CN 201810320806 A CN201810320806 A CN 201810320806A CN 108364928 B CN108364928 B CN 108364928B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses an integrated circuit packaging structure and a processing method thereof, wherein the packaging structure comprises a base island, a chip and a packaging material, wherein a silver ring is formed on the front surface of the base island, a placement area for placing the chip is formed by enclosing the inner edge of the silver ring, and an isolation area is formed between the outer edge of the silver ring and the edge of the base island. The technical scheme of the invention improves the binding force between the base island and the packaging material, can avoid the invasion of water vapor from the source, and integrally improves the reliability of the integrated circuit packaging structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an integrated circuit packaging structure and a processing method thereof.
Background
In order to realize good heat dissipation, the back surface of the base island 01 of the existing integrated circuit such as EMSOP is exposed in the air, and the front surface and the side surface of the base island 01 are encapsulated by resin 02, wherein the front surface of the base island storing the chip 03 is fully plated with silver, a silver plating layer 04 is formed, and the purpose of silver plating is to weld a ground wire.
The practice shows that the bonding force between the resin and the silver surface in the packaging structure is not very good, so that the bonding between the front surface of the base island and the resin is not tight, and water vapor is easy to invade. In addition, chemical treatment for preventing conductive adhesive diffusion is carried out on the surface of the silver plating layer, and if the treatment layer is not volatilized in the high-temperature process of production before encapsulation, the binding force between the resin and the silver surface is further reduced.
Disclosure of Invention
The embodiment of the invention provides an integrated circuit packaging structure and a processing method thereof, which are used for improving the binding force between a base island and a packaging material, avoiding the invasion of water vapor and improving the reliability of the packaging structure.
The technical scheme adopted is as follows:
In one aspect, an integrated circuit package structure is provided, including a base island, a chip and a packaging material, wherein a silver ring is formed on the front surface of the base island, a placement area for placing the chip is formed by enclosing the inner edge of the silver ring, and an isolation area is formed between the outer edge of the silver ring and the edge of the base island.
In another aspect, there is provided a method for manufacturing the integrated circuit package structure as described above, including: manufacturing a lead frame, wherein the lead frame comprises a base island and an outer pin; copper plating on the surface of the lead frame to form a copper plating layer with the thickness of 0.125-0.25 micrometers; silver is plated on the front surface ring of the base island to form a silver ring, a placement area for placing the chip is formed by encircling the inner edge of the silver ring, an isolation area is formed between the outer edge of the silver ring and the edge of the base island, and the width of the isolation area is not less than 10 microns; and fixing the chip in the mounting area by using a die attach adhesive, welding leads between the chip and the outer pins, and packaging the chip, the outer pins and the leads by using packaging materials to form a specified shape.
From the above technical solutions, the embodiment of the present invention has the following advantages:
the silver ring is formed on the front surface of the base island by electroplating and is used for ground wire welding, and other areas of the front surface of the base island are still copper materials of the base island, so that only a small part of packaging materials such as resin and a contact part of the base island in the packaging structure are silver-plated, and most of packaging materials are contacted with the surface of copper, and the bonding force of copper and the resin is better than that of the combination of silver and the resin, therefore, the invasion of water vapor can be avoided, and the reliability of the packaging structure is improved.
It can be understood that if the outer edge of the silver ring, the side surface of the island and the air overlap, the bonding force between the resin and the silver is poor, so that the edge portion becomes a vapor intrusion point, the inward pushing speed is not reduced until the contact area between the resin and the copper surface of the island is encountered, but the vapor still enters the packaging structure, and the inward diffusion speed is reduced only after entering, so that the vapor intrusion problem cannot be solved well.
In the technical scheme of the invention, the isolation area is formed between the outer edge of the silver ring and the edge of the base island, and the isolation area is still made of copper material, has better binding force with the resin packaging material, can strictly prevent water vapor from invading from the edge of the base island, thus solving the problem of water vapor invasion from the source and ensuring the high reliability of the packaging structure.
Therefore, according to the technical scheme, on one hand, the silver ring is arranged on the front surface of the base island to replace full-surface silver plating, so that the contact area between silver and the packaging material is reduced, the contact area between copper materials of the base island and the packaging material is increased, the invasion of water vapor is reduced, and the reliability is improved; on the other hand, the silver ring is arranged in the area of the inner side edge of the front side of the base island, an isolation area is reserved between the silver ring and the edge of the base island, and the copper material of the isolation area is tightly combined with the packaging material to prevent water vapor invasion, so that the problem of water vapor invasion is solved from the source; therefore, the technical problems of improving the binding force of the base island and the packaging material, avoiding the invasion of water vapor and improving the reliability of the packaging structure are realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments and the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional EMSOP integrated circuit package structure;
FIG. 2 is a schematic diagram of an integrated circuit package structure according to an embodiment of the present invention;
Fig. 3 is a flowchart of a processing method of an integrated circuit package structure according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The terms first, second, third and the like in the description and in the claims and in the above drawings, are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The following will each explain in detail by means of specific examples.
Referring to fig. 2, an integrated circuit package structure is provided in an embodiment of the present invention, and includes a base island 11, a chip 12 and a packaging material 13. In particular, a silver ring 17 is formed on the front surface of the base island 11, a placement area 21 for placing the chip is formed around the inner edge of the silver ring 17, and an isolation area 22 is formed between the outer edge of the silver ring 17 and the edge of the base island.
It should be noted that, the chip 12 is disposed on the front surface of the base island 11, the encapsulation material 13 is used to encapsulate the base island 11 and the chip 12, the front surface and the side surface of the base island 11 are encapsulated inside the encapsulation material 13, but the back surface of the base island 11 is exposed outside the encapsulation material 13. The integrated circuit package further comprises outer leads 14, the outer leads 14 and the islands 11 together forming what is known in the art as a leadframe, or leadframe. The outer leads 14 and the chip 12 may be electrically connected by bonding wires 15, and the chip 12 may be grounded by grounding wires 16 to the front surface of a silver ring 17 on the submount 11. The lead frame, including the base island 11 and the outer leads 14 are generally made of copper, the packaging material 13 is generally made of resin, and the chip 12 is generally a semiconductor chip. The leads 15 and ground 16 may be silver or copper wires or other wires. The chip 12 may be fixed on the front surface of the island 11 by silver paste 18.
The silver ring 17 is formed on the front surface of the island 11 for the purpose of soldering the ground wire 16, and it is indispensable to solder the ground wire between the ground terminal of the chip 12 and the silver ring 17. However, the bonding force between silver and the packaging material such as resin is not very good, and the silver and the packaging material are easy to be invaded by water vapor; the binding force of silver and copper is good, and the silver and copper cannot be invaded by water vapor. Therefore, in the scheme of the invention, the width of the silver ring can be limited to achieve better balance. In one aspect, to ensure soldering requirements, it is preferred that the silver ring has a width a1 of not less than 100 microns. On the other hand, in order to improve the bonding force with the encapsulation material, the area of the silver ring should be reduced, and the width of the silver ring a1 is preferably not more than 300 μm.
In the present invention, an isolation region 22 is formed between the outer edge of the silver ring 17 and the edge of the island to prevent the formation of a vapor intrusion point at the edge of the island, and the width a2 of the isolation region is preferably not less than 10 μm to ensure the achievement of the object. Preferably, the width a2 of the isolation region is between 10 micrometers and 200 micrometers.
In order to further increase the bonding force of the resin encapsulation material and the copper surface, it is preferable that the front surface of the island, including the surface of the bottom of the silver ring 17 and the placement region 21 and the isolation region 22, have a copper plating layer formed electrochemically. Further, the copper plating layer has a thickness of between 0.125 and 0.25 microns. Further, the copper plating layer has been treated with a copper peeling preventing chemical solution to further improve the bonding force.
As described above, the silver ring for bonding wire is formed on the front surface of the island, and is more than 10 micrometers away from the edge of the island, but not more than half of the width of the island in the same direction, typically about 10 micrometers to 200 micrometers; the silver plating ring has a width of over 100 microns, typically between 100 microns and 300 microns, but no more than half the width of the co-directional islands; to ensure that: the silver ring has a sufficient width for soldering, the silver ring surrounding area has a sufficient area for mounting the chip, and the area of the silver ring is as small as possible so as to avoid reducing the bonding force with the packaging material. In order to further increase the binding force between the resin packaging material and the copper surface, a layer of copper is plated on the copper surface by an electrochemical method, the thickness is 0.125-0.25 mu m, the copper surface is smoother, then copper stripping prevention chemical liquid treatment is carried out, the binding force with a silver ring at the back is increased, and meanwhile, the binding force between the resin and the front surface of the base island is increased.
Therefore, the invention can reduce the intrusion of water vapor into the integrated circuit packaging structure from the source.
Referring to fig. 3, an embodiment of the present invention further provides a method for processing an integrated circuit package structure as described above, where the method includes:
31. manufacturing a lead frame, wherein the lead frame comprises a base island and an outer pin;
32. copper plating on the surface of the lead frame to form a copper plating layer with the thickness of 0.125-0.25 micrometers;
33. Silver is plated on the front surface ring of the base island to form a silver ring, a placement area for placing the chip is formed by encircling the inner edge of the silver ring, an isolation area is formed between the outer edge of the silver ring and the edge of the base island, and the width of the isolation area is not less than 10 microns;
34. And fixing the chip in the mounting area by using a die attach adhesive, welding leads between the chip and the outer pins, and packaging the chip, the outer pins and the leads by using packaging materials to form a specified shape.
Optionally, after step 32, before step 33, the method further includes: and (3) carrying out copper stripping prevention chemical liquid treatment on the copper plating layer.
As described above, in some examples, specific implementations of the method of this example may be:
a) Generating lead frame base islands, lead frame outer pin structures and the like in the mechanism by using a mechanical die method;
b) Plating a layer of copper on the surface of the mechanism, wherein the thickness of the copper is 0.125-0.25 mu m, so that the copper surface is smoother, and then carrying out copper stripping prevention chemical liquid treatment, thereby increasing the combination with a rear silver ring and simultaneously increasing the combination force between resin and the front surface of a base island;
c) Plating silver on the position which is more than 10 microns away from the edge of the base island, wherein the silver ring is only used for welding connecting wires and is not contacted with conductive adhesive, so that the common chemical treatment for preventing the diffusion of the chip-mounting adhesive is removed; d) Spot-mounting a piece of glue on the front surface of the base island;
e) Pressing the semiconductor chip on the chip mounting adhesive, and performing adhesive hinge reaction in a high-temperature oven;
f) Metal lead wire welding is carried out between the semiconductor chip and the lead pins;
g) Packaging the base island, the chip and the outer pins in the die by using resin;
h) The machine is formed into a predetermined shape by a mold or the like.
The base island must be welded with a grounded lead wire, namely a ground wire, and the welding place of the ground wire must be silver-plated, but the bonding force between resin and silver-plated surface in the structure is not large, so that water vapor is easy to invade, the resin and the base island surface are layered, the layered water vapor can be diffused to the chip surface if serious, and the layered water vapor can expand when the circuit works, so that the product welding point is disconnected on one hand; on the other hand, pressure is generated in the packaging structure, so that the working voltage of the circuit is changed. And the bonding force between the resin in the packaging structure and the surface of the copper island is better than that between the resin and the surface of silver. Therefore, under the condition of meeting the welding condition, firstly, the area of silver is reduced as much as possible, and the area of the copper surface is increased; secondly, the silver plating layer is prevented from appearing at the interface between the resin, air and metal islands in the mechanism as much as possible, and the bonding force of the interface is increased, so that the invasion of water vapor is controlled at the source.
In summary, the embodiment of the invention discloses an integrated circuit packaging structure and a processing method thereof, and by adopting the technical scheme, the following technical effects are achieved:
the silver ring is formed on the front surface of the base island by electroplating and is used for ground wire welding, and other areas of the front surface of the base island are still copper materials of the base island, so that only a small part of packaging materials such as resin and a contact part of the base island in the packaging structure are silver-plated, and most of packaging materials are contacted with the surface of copper, and the bonding force of copper and the resin is better than that of the combination of silver and the resin, therefore, the invasion of water vapor can be avoided, and the reliability of the packaging structure is improved.
It can be understood that if the outer edge of the silver ring, the side surface of the island and the air overlap, the bonding force between the resin and the silver is poor, so that the edge portion becomes a vapor intrusion point, the inward pushing speed is not reduced until the contact area between the resin and the copper surface of the island is encountered, but the vapor still enters the packaging structure, and the inward diffusion speed is reduced only after entering, so that the vapor intrusion problem cannot be solved well.
In the technical scheme of the invention, the isolation area is formed between the outer edge of the silver ring and the edge of the base island, and the isolation area is still made of copper material, has better binding force with the resin packaging material, can strictly prevent water vapor from invading from the edge of the base island, thus solving the problem of water vapor invasion from the source and ensuring the high reliability of the packaging structure.
Therefore, according to the technical scheme, on one hand, the silver ring is arranged on the front surface of the base island to replace full-surface silver plating, so that the contact area between silver and the packaging material is reduced, the contact area between copper materials of the base island and the packaging material is increased, the invasion of water vapor is reduced, and the reliability is improved; on the other hand, the silver ring is arranged in the area of the inner side edge of the front side of the base island, an isolation area is reserved between the silver ring and the edge of the base island, and the copper material of the isolation area is tightly combined with the packaging material to prevent water vapor invasion, so that the problem of water vapor invasion is solved from the source; therefore, the technical problems of improving the binding force of the base island and the packaging material, avoiding the invasion of water vapor and improving the reliability of the packaging structure are realized.
In the foregoing embodiments, the descriptions of the embodiments are each focused, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; those of ordinary skill in the art will appreciate that: the technical scheme described in the above embodiments can be modified or some technical features thereof can be replaced equivalently; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (2)
1. An integrated circuit package structure comprises a base island, a chip and a packaging material, and is characterized in that,
A silver ring is formed on the front surface of the base island, a placement area for placing the chip is formed by encircling the inner edge of the silver ring, and an isolation area is formed between the outer edge of the silver ring and the edge of the base island;
the width of the isolation region is between 10 micrometers and 200 micrometers;
the width of the silver ring is not less than 100 microns and not more than 300 microns;
The surface of the bottom of the placement area, the isolation area, other areas of the lead frame and the silver ring is provided with a copper plating layer formed by an electrochemical method;
the copper plating layer has a thickness of between 0.125 and 0.25 microns;
The copper plating layer has been treated with a copper peeling-preventing chemical solution.
2. A method of processing the integrated circuit package of claim 1, the method comprising:
Manufacturing a lead frame, wherein the lead frame comprises a base island and an outer pin;
Copper plating on the surface of the lead frame to form a copper plating layer with the thickness of 0.125-0.25 micrometers;
Silver is plated on the front surface ring of the base island to form a silver ring, a placement area for placing the chip is formed by encircling the inner edge of the silver ring, an isolation area is formed between the outer edge of the silver ring and the edge of the base island, and the width of the isolation area is between 10 microns and 200 microns; the width of the silver ring is not less than 100 microns and not more than 300 microns;
Fixing a chip in the placement area by using a die attach adhesive, welding leads between the chip and the outer pins, and encapsulating the chip, the outer pins and the leads with an encapsulating material to form a specified shape;
before the front ring of the base island is plated with silver, the method further comprises:
and (3) carrying out copper stripping prevention chemical liquid treatment on the copper plating layer.
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| CN201810320806.7A CN108364928B (en) | 2018-04-11 | 2018-04-11 | Integrated circuit packaging structure and processing method thereof |
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| CN201810320806.7A CN108364928B (en) | 2018-04-11 | 2018-04-11 | Integrated circuit packaging structure and processing method thereof |
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| CN110137342A (en) * | 2019-05-07 | 2019-08-16 | 合肥久昌半导体有限公司 | A kind of high-power hall device lead frame, encapsulating structure and its packaging technology |
| CN114190009A (en) * | 2021-11-19 | 2022-03-15 | 气派科技股份有限公司 | Surface-mounted device packaging structure and upper plate welding method thereof |
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| US6667073B1 (en) * | 2002-05-07 | 2003-12-23 | Quality Platers Limited | Leadframe for enhanced downbond registration during automatic wire bond process |
| CN208045487U (en) * | 2018-04-11 | 2018-11-02 | 气派科技股份有限公司 | A kind of integrated circuit package structure |
| CN108831874A (en) * | 2018-08-07 | 2018-11-16 | 广东气派科技有限公司 | Integrated circuit packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108364928A (en) | 2018-08-03 |
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Denomination of invention: An integrated circuit packaging structure and its processing method Granted publication date: 20240621 Pledgee: Shenzhen Rural Commercial Bank Co.,Ltd. Nanshan Sub branch Pledgor: China Chippacking Technology Co.,Ltd. Registration number: Y2024980040493 |
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