CN108346615A - A kind of groove forming method and semiconductor devices - Google Patents
A kind of groove forming method and semiconductor devices Download PDFInfo
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- CN108346615A CN108346615A CN201810089222.3A CN201810089222A CN108346615A CN 108346615 A CN108346615 A CN 108346615A CN 201810089222 A CN201810089222 A CN 201810089222A CN 108346615 A CN108346615 A CN 108346615A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 230000000694 effects Effects 0.000 abstract description 11
- 238000011068 loading method Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
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- Microelectronics & Electronic Packaging (AREA)
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- Solid State Image Pick-Up Elements (AREA)
- Drying Of Semiconductors (AREA)
Abstract
本发明提供一种沟槽形成方法，包括提供一基底及基底下面的氧化层；在基底的上面涂覆光刻胶，用一掩模板对基底上的光刻胶进行曝光显影，以在基底上形成第一和第二图案；掩模板上有第一和第二掩模图案，第一掩模图案的面积大于第二掩模图案；据第一图案和第二图案对基底刻蚀，除去基底上的光刻胶，在基底上形成第一和第二沟槽，第一沟槽的深度大于第二沟槽。还提供一种半导体器件，包括基底和基底下面的氧化层，在基底上用上述沟槽形成方法形成第一和第二沟槽。本发明根据刻蚀的loading effect现象，利用一张掩模板上同时具面积不同的第一和第二掩模图案，用一次曝光显影刻蚀形成深度不同的第一和第二沟槽，简化了工艺，降低了成本。
The invention provides a method for forming a trench, comprising providing a substrate and an oxide layer under the substrate; coating photoresist on the substrate, exposing and developing the photoresist on the substrate with a mask, so that Forming first and second patterns; there are first and second mask patterns on the mask plate, and the area of the first mask pattern is larger than that of the second mask pattern; etching the substrate according to the first pattern and the second pattern to remove the substrate The photoresist on the substrate forms first and second grooves on the substrate, and the depth of the first groove is greater than that of the second groove. Also provided is a semiconductor device comprising a substrate and an oxide layer under the substrate, the first and second trenches are formed on the substrate by the above trench forming method. According to the loading effect phenomenon of etching, the present invention utilizes first and second mask patterns with different areas on a mask to form first and second grooves with different depths by one-time exposure, development and etching, which simplifies process, reducing costs.
Description
技术领域technical field
本发明涉及半导体技术领域，具体涉及一种沟槽形成方法及半导体器件。The invention relates to the technical field of semiconductors, in particular to a trench forming method and a semiconductor device.
背景技术Background technique
深沟槽隔离(Deep trench isolation，DTI)技术在当前图像处理中已占据重要地位，当前日趋复杂和高性能的工艺也要求在产品中加入DTI，以获得更好的隔离效果。Deep trench isolation (DTI) technology has occupied an important position in current image processing, and the current increasingly complex and high-performance processes also require adding DTI to products to obtain better isolation effects.
传统CMOS型图像传感器的制备工艺中，存在背面接线区(BSL area)，背面接线区的沟槽的加工工艺是通过在掩模板上设置背面接线图案，经过曝光显影刻蚀工艺形成贯穿硅基底延伸至氧化层的沟槽。为了提升CMOS型图像传感器的光学性能和电学性能，在CMOS型图像传感器的像素单元区引入深沟槽隔离(DTI)工艺，该工艺需要另用一张掩模板，掩模板上设置对应的图案，经过曝光显影刻蚀工艺在硅基底上形成用于像素单元之间隔离的沟槽，从而达到防止相邻像素单元之间电子串扰的目的。In the manufacturing process of the traditional CMOS image sensor, there is a back wiring area (BSL area). The processing technology of the groove in the back wiring area is to set the back wiring pattern on the mask plate, and form the extending through the silicon substrate through the exposure, development and etching process. trenches to the oxide layer. In order to improve the optical performance and electrical performance of the CMOS image sensor, a deep trench isolation (DTI) process is introduced in the pixel unit area of the CMOS image sensor. This process requires another mask, and a corresponding pattern is set on the mask. A trench for isolation between pixel units is formed on the silicon substrate through an exposure, development and etching process, thereby achieving the purpose of preventing electronic crosstalk between adjacent pixel units.
可见，为了形成上述两种深度不同沟槽，需要两个掩模板、用两次曝光、显影和刻蚀工艺分别形成，工艺复杂，增加了产品本身的成本。It can be seen that in order to form the above two types of grooves with different depths, two masks are required to be formed respectively by two exposure, development and etching processes. The process is complicated and increases the cost of the product itself.
发明内容Contents of the invention
针对现有技术中的缺陷，本发明实施例提供了一种沟槽形成方法及半导体器件。Aiming at the defects in the prior art, embodiments of the present invention provide a method for forming a trench and a semiconductor device.
第一方面，本发明实施例提供一种沟槽形成方法，包括：In a first aspect, an embodiment of the present invention provides a trench forming method, including:
提供一基底以及所述基底下面的氧化层；providing a substrate and an oxide layer beneath the substrate;
在所述基底的上面涂覆光刻胶，利用一掩模板对所述基底上的光刻胶进行曝光显影，以在所述基底的光刻胶上形成第一图案和第二图案；所述掩模板上具有与第一图案对应的第一掩模图案和与第二图案对应的第二掩模图案，所述第一掩模图案的面积大于所述第二掩模图案的面积；Coating photoresist on the substrate, using a mask to expose and develop the photoresist on the substrate, so as to form a first pattern and a second pattern on the photoresist of the substrate; The mask plate has a first mask pattern corresponding to the first pattern and a second mask pattern corresponding to the second pattern, and the area of the first mask pattern is larger than the area of the second mask pattern;
根据所述基底的光刻胶上形成的第一图案和第二图案对所述基底进行刻蚀，除去所述基底上的光刻胶，在所述基底上形成第一沟槽和第二沟槽，所述第一沟槽的深度大于所述第二沟槽的深度。Etching the substrate according to the first pattern and the second pattern formed on the photoresist of the substrate, removing the photoresist on the substrate, and forming a first groove and a second groove on the substrate grooves, the depth of the first groove is greater than the depth of the second groove.
本发明还提供一种半导体器件，所述半导体器件包括基底和所述基底下面的氧化层，在所述基底上采用所述的沟槽形成方法形成有第一沟槽和第二沟槽。The present invention also provides a semiconductor device. The semiconductor device includes a base and an oxide layer under the base. A first trench and a second trench are formed on the base by using the trench forming method.
优选的，所述第一沟槽的深度为所述第二沟槽的深度的1.1-2.0倍。Preferably, the depth of the first groove is 1.1-2.0 times the depth of the second groove.
优选的，所述第二沟槽的宽度范围为70-150nm，所述第二沟槽的深度范围为1500-2500nm。Preferably, the width of the second groove is in the range of 70-150 nm, and the depth of the second groove is in the range of 1500-2500 nm.
优选的，所述半导体器件为CMOS型图像传感器。Preferably, the semiconductor device is a CMOS image sensor.
优选的，所述第一沟槽贯穿所述基底和部分所述氧化层，所述第二沟槽的底部与所述基底的底面之间具有预设距离。Preferably, the first trench penetrates through the substrate and part of the oxide layer, and there is a predetermined distance between the bottom of the second trench and the bottom surface of the substrate.
优选的，所述第一沟槽为用于形成背面接线区域的沟槽。Preferably, the first trench is a trench for forming a wiring region on the back side.
优选的，所述第二沟槽为用于像素单元之间隔离的沟槽。Preferably, the second trench is a trench for isolation between pixel units.
优选的，包括至少四个所述第二沟槽，所述至少四个所述第二沟槽中的每四个所述第二沟槽组成一个矩形区域，每个所述矩形区域将一个像素单元包围在其中。Preferably, at least four second grooves are included, and every four second grooves in the at least four second grooves form a rectangular area, and each rectangular area forms a pixel The unit is surrounded by it.
优选的，所述基底为硅基底。Preferably, the substrate is a silicon substrate.
本发明提供的沟槽形成方法根据刻蚀的loading effect现象(负载效应，因为刻蚀速率和刻蚀剖面与图形尺寸和密度有关而产生与深宽比相关的刻蚀或微负载效应，即图案面积越大，刻蚀形成的沟槽越深，图案面积越小，刻蚀形成的沟槽越浅)，利用第一掩模图案和第二掩模图案面积不同，在一张掩模板上同时印刷第一掩模图案和第二掩模图案，用一次曝光、显影、刻蚀形成深度不同的第一沟槽和第二沟槽，简化了工艺，降低了成本。利用本发明沟槽形成方法形成的半导体器件制作工艺简单，成本低。The trench forming method provided by the present invention is based on the loading effect phenomenon (loading effect) of etching, because etching rate and etching profile are related to pattern size and density and produce etching or micro-loading effect relevant to aspect ratio, i.e. pattern The larger the area, the deeper the groove formed by etching, the smaller the pattern area, the shallower the groove formed by etching), using the different areas of the first mask pattern and the second mask pattern, on a mask at the same time The first mask pattern and the second mask pattern are printed, and the first groove and the second groove with different depths are formed by one exposure, development, and etching, which simplifies the process and reduces the cost. The manufacturing process of the semiconductor device formed by using the groove forming method of the invention is simple and the cost is low.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明实施例提供的一种沟槽形成方法的流程图；FIG. 1 is a flow chart of a trench forming method provided by an embodiment of the present invention;
图2为未形成第一沟槽和第二沟槽的基底和氧化层的结构示意图；2 is a schematic structural view of a substrate and an oxide layer without forming a first trench and a second trench;
图3为形成有第一沟槽和第二沟槽的基底和氧化层的结构示意图；3 is a schematic structural view of a substrate and an oxide layer formed with a first trench and a second trench;
图4为本发明一种具体实施例提供的一个矩形区域和像素单元的关系示意图。Fig. 4 is a schematic diagram of the relationship between a rectangular area and pixel units provided by a specific embodiment of the present invention.
附图标记说明Explanation of reference signs
其中，基底-1氧化层-2金属层-3第一沟槽-4第二沟槽-5第一第二沟槽-51第二第二沟槽-52第三第二沟槽-53第四第二沟槽-54像素单元-6Among them, substrate-1 oxide layer-2 metal layer-3 first trench-4 second trench-5 first second trench-51 second second trench-52 third second trench-53 Four second grooves - 54 pixel units - 6
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the following will clearly and completely describe the technical solutions of the embodiments of the present invention in conjunction with the drawings of the embodiments of the present invention. Apparently, the described embodiments are some, not all, embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present invention belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
图1为本发明实施例提供的一种沟槽形成方法的流程图。FIG. 1 is a flowchart of a trench forming method provided by an embodiment of the present invention.
如图1所示的一种沟槽形成方法，包括：A method for forming a groove as shown in Figure 1, comprising:
S101、如图2所示，提供一基底1以及所述基底1下面的氧化层2；S101, as shown in FIG. 2 , providing a substrate 1 and an oxide layer 2 under the substrate 1;
S102、在所述基底1的上面涂覆光刻胶，利用一掩模板对所述基底进行曝光显影，以在所述基底1的光刻胶上形成第一图案和第二图案；所述掩模板上具有与第一图案对应的第一掩模图案和与第二图案对应的第二掩模图案，所述第一掩模图案的面积大于所述第二掩模图案的面积；S102. Coating photoresist on the substrate 1, using a mask to expose and develop the substrate, so as to form a first pattern and a second pattern on the photoresist of the substrate 1; the mask The template has a first mask pattern corresponding to the first pattern and a second mask pattern corresponding to the second pattern, and the area of the first mask pattern is larger than the area of the second mask pattern;
S103、如图3所示，根据所述基底1的光刻胶上形成的第一图案和第二图案对所述基底1进行刻蚀，除去所述基底1上的光刻胶，在所述基底1上形成第一沟槽4和第二沟槽5，所述第一沟槽4的深度大于所述第二沟槽5的深度。S103, as shown in FIG. 3 , etch the substrate 1 according to the first pattern and the second pattern formed on the photoresist of the substrate 1, remove the photoresist on the substrate 1, and A first groove 4 and a second groove 5 are formed on the substrate 1 , the depth of the first groove 4 is greater than the depth of the second groove 5 .
具体地，可采用例如空气刻蚀法进行刻蚀，也可以采用其他现有刻蚀方法，本发明对此不做限制。Specifically, for example, an air etching method may be used for etching, or other existing etching methods may be used, which is not limited in the present invention.
本实施例根据刻蚀的loading effect现象(负载效应，因为刻蚀速率和刻蚀剖面与图形尺寸和密度有关而产生与深宽比相关的刻蚀或微负载效应，即图案面积越大，刻蚀形成的沟槽越深，图案面积越小，刻蚀形成的沟槽越浅)，利用第一掩模图案和第二掩模图案面积不同，在一张掩模板上同时具有第一掩模图案和第二掩模图案，用一次曝光、显影、刻蚀形成深度不同的第一沟槽和第二沟槽，简化了工艺，降低了成本。This embodiment is based on the loading effect phenomenon of etching (loading effect, because the etching rate and etching profile are related to the pattern size and density and produce the etching or micro-loading effect relevant to the aspect ratio, that is, the larger the pattern area, the more the etching The deeper the groove formed by etching, the smaller the pattern area, and the shallower the groove formed by etching), using the different areas of the first mask pattern and the second mask pattern, there is a first mask on one mask pattern and the second mask pattern, the first groove and the second groove with different depths are formed by one exposure, development and etching, which simplifies the process and reduces the cost.
如图3所示，所述第二沟槽5为上宽下窄的结构。As shown in FIG. 3 , the second groove 5 is a structure with a wide top and a narrow bottom.
图3为形成有第一沟槽和第二沟槽的基底和氧化层的结构示意图。FIG. 3 is a schematic structural view of a substrate and an oxide layer formed with a first trench and a second trench.
本发明还提供一种半导体器件，所述半导体器件包括图3所示的基底1和和所述基底1下面的氧化层2，在所述基底1上采用所述的沟槽形成方法形成有第一沟槽4和第二沟槽5。The present invention also provides a semiconductor device. The semiconductor device includes the substrate 1 shown in FIG. 3 and the oxide layer 2 under the substrate 1. A groove 4 and a second groove 5.
根据上文可知，本实施例的第一沟槽和第二沟槽根据刻蚀的loadingeffect现象仅通过一张掩模板，经过一次曝光、显影、刻蚀就可形成，工艺简单，因此，利用本发明沟槽形成方法形成的半导体器件制作工艺简单，成本低。According to the above, according to the loading effect phenomenon of etching, the first groove and the second groove of this embodiment can be formed only through one mask, after one exposure, development, and etching, and the process is simple. Therefore, using this The manufacturing process of the semiconductor device formed by the groove forming method of the invention is simple and the cost is low.
在一种具体实施例中，所述第一沟槽4的深度为所述第二沟槽5的深度的1.1-2.0倍。优选为1.5倍。当然，还可以根据需要设置不同的倍数，本发明对此不做限制，可调整第一掩模图案和第二掩模图案的面积，以使第一沟槽4和第二沟槽5具有不同的深度。In a specific embodiment, the depth of the first groove 4 is 1.1-2.0 times the depth of the second groove 5 . Preferably it is 1.5 times. Of course, different multiples can also be set according to needs, and the present invention is not limited to this. The areas of the first mask pattern and the second mask pattern can be adjusted so that the first trench 4 and the second trench 5 have different depth.
在一种具体实施例中，所述第二沟槽5的宽度范围可为70-150nm，具体可为100nm，所述第二沟槽5的深度范围可为1500-2500nm，具体可为2000nm。第二沟槽5的宽度和深度可根据需要具体设置，本发明对此不做限制。In a specific embodiment, the width of the second trench 5 may be in the range of 70-150 nm, specifically 100 nm, and the depth of the second trench 5 may be in the range of 1500-2500 nm, specifically 2000 nm. The width and depth of the second groove 5 can be specifically set according to needs, which is not limited in the present invention.
优选地，所述半导体器件可以为CMOS型图像传感器，当所述半导体器件为CMOS型图像传感器时，可包括至少四个所述第二沟槽5，所述至少四个所述第二沟槽5中的每四个所述第二沟槽5组成一个矩形区域，每个所述矩形区域将一个像素单元包围在其中。值得说明的是，深沟槽的数量可根据需要具体设置，本发明对此不做限制。如图3所示，在一种具体实施例中，所述第一沟槽4贯穿所述基底1和部分所述氧化层2，所述第二沟槽5的底部与所述基底1的底面之间具有预设距离。在图2和图3所示的具体实施例中，还可在氧化层2中形成有金属层3。Preferably, the semiconductor device may be a CMOS image sensor, and when the semiconductor device is a CMOS image sensor, it may include at least four second grooves 5, and the at least four second grooves Every four of the second grooves 5 in 5 form a rectangular area, each of which surrounds a pixel unit. It should be noted that the number of deep grooves can be specifically set according to needs, which is not limited in the present invention. As shown in FIG. 3 , in a specific embodiment, the first trench 4 runs through the substrate 1 and part of the oxide layer 2 , and the bottom of the second trench 5 is in contact with the bottom surface of the substrate 1 There is a preset distance between them. In the specific embodiments shown in FIGS. 2 and 3 , a metal layer 3 may also be formed in the oxide layer 2 .
优选地，所述基底可为硅基底。Preferably, the substrate may be a silicon substrate.
当然，所述半导体器件除了可以为CMOS型图像传感器外，还可以是其他半导体器件，本发明对此不做限制。Certainly, the semiconductor device may be other semiconductor devices besides the CMOS image sensor, which is not limited in the present invention.
下面结合图4以半导体器件为CMOS型图像传感器、所述第一沟槽4为用于形成背面接线区域的沟槽。所述第二沟槽5为用于像素单元之间隔离的沟槽为例对本发明进行说明。Referring to FIG. 4 below, the semiconductor device is a CMOS image sensor, and the first trench 4 is a trench for forming a rear wiring region. The present invention will be described by taking the second trench 5 as a trench for isolation between pixel units as an example.
一种沟槽形成方法，包括：A trench forming method, comprising:
S201、提供一硅基底以及所述硅基底下面的氧化层；S201, providing a silicon substrate and an oxide layer under the silicon substrate;
S202、在所述硅基底的上面涂覆光刻胶，利用一掩模板对所述硅基底上的光刻胶进行曝光显影，以在所述硅基底的光刻胶上形成第一图案和第二图案；所述掩模板上具有第一掩模图案和第二掩模图案，所述第一掩模图案为与背面接线区域的沟槽对应的图案，所述第二掩模图案为与用于像素单元之间隔离的沟槽对应的图案，所述第一掩模图案的面积大于所述第二掩模图案的面积；S202, coating photoresist on the silicon substrate, using a mask to expose and develop the photoresist on the silicon substrate, so as to form a first pattern and a second pattern on the photoresist of the silicon substrate Two patterns; the mask plate has a first mask pattern and a second mask pattern, the first mask pattern is a pattern corresponding to the groove of the back wiring area, and the second mask pattern is used for a pattern corresponding to a trench isolated between pixel units, the area of the first mask pattern is larger than the area of the second mask pattern;
S203、根据所述硅基底的光刻胶上形成的第一图案和第二图案对所述硅基底进行刻蚀除去所述硅基底上的光刻胶，在所述硅基底上形成一个第一沟槽4和多个第二沟槽5，所述第一沟槽4的深度大于所述第二沟槽5的深度。所述第一沟槽4为用于形成背面接线区域的沟槽，所述第一沟槽4贯穿所述硅基底1和部分所述氧化层2，多个第二沟槽5形成在CMOS型图像传感器的像素区，所述第二沟槽5的宽度为100nm，深度为2000nm，所述第二沟槽5的底部与所述硅基底1的底面之间具有预设距离，多个所述第二沟槽5形成为多个矩形区域，每个矩形区域包围一个像素单元，图4中显示出一个矩形区域，图4中的第一第二沟槽51、第二第二沟槽52、第三第二沟槽53、第四第二沟槽54组成一个矩形区域，将像素单元6(R、G、B中的任何一个)包围在其中，从而使像素单元6与相邻的像素单元隔离，如图4所示。具体地，可采用例如空气刻蚀法进行刻蚀，也可以采用其他现有刻蚀方法，本发明对此不做限制。S203. Etch the silicon substrate according to the first pattern and the second pattern formed on the photoresist of the silicon substrate to remove the photoresist on the silicon substrate, and form a first pattern on the silicon substrate A groove 4 and a plurality of second grooves 5 , the depth of the first groove 4 is greater than the depth of the second groove 5 . The first trench 4 is a trench for forming a back wiring area, the first trench 4 penetrates the silicon substrate 1 and part of the oxide layer 2, and a plurality of second trenches 5 are formed in a CMOS type In the pixel area of the image sensor, the width of the second groove 5 is 100nm, and the depth is 2000nm. There is a preset distance between the bottom of the second groove 5 and the bottom surface of the silicon substrate 1, and a plurality of the The second groove 5 is formed into a plurality of rectangular areas, each rectangular area surrounds a pixel unit, a rectangular area is shown in Figure 4, the first second groove 51, the second second groove 52, The third second groove 53 and the fourth second groove 54 form a rectangular area, which surrounds the pixel unit 6 (any one in R, G, B), so that the pixel unit 6 and the adjacent pixel unit isolation, as shown in Figure 4. Specifically, for example, an air etching method may be used for etching, or other existing etching methods may be used, which is not limited in the present invention.
当然，所述第一沟槽和第二沟槽不局限于该两种沟槽，还可以是具有其他用途的沟槽，本发明不再一一详述。Of course, the first groove and the second groove are not limited to these two kinds of grooves, and may also be grooves with other purposes, which will not be described in detail in the present invention.
本实施例提供的沟槽形成方法根据刻蚀的loading effect现象，利用第一掩模图案(背面接线区域的沟槽对应的图案)和第二掩模图案(与用于像素单元之间隔离的沟槽对应的图案)面积不同，在一张掩模板上同时具有第一掩模图案和第二掩模图案，用一次曝光、显影、刻蚀形成深度不同的第一沟槽(用于形成背面接线区域的沟槽)和第二沟槽(用于像素单元之间隔离的沟槽)，简化了工艺，降低了成本。利用本发明沟槽形成方法形成的CMOS型图像传感器制作工艺简单，成本低。According to the loading effect phenomenon of etching, the trench forming method provided in this embodiment utilizes the first mask pattern (the pattern corresponding to the trench in the wiring region on the back) and the second mask pattern (the pattern corresponding to the pattern used for isolation between pixel units) The pattern corresponding to the groove) has different areas, and has the first mask pattern and the second mask pattern on a mask plate, and forms the first groove with different depths (for forming the back surface) with one exposure, development, and etching. The trench in the wiring region) and the second trench (the trench used for isolation between pixel units) simplify the process and reduce the cost. The CMOS image sensor formed by the groove forming method of the present invention has simple manufacturing process and low cost.
值得说明的是，第二沟槽的隔离作用因第二沟槽中填充的物质不同而不同，所述隔离可分为光学隔离与电子隔离，在第二沟槽中填充不透光的金属可用于光学隔离，在第二沟槽中填充不导电的氧化硅可用于电子隔离。It is worth noting that the isolation effect of the second trench is different due to the different substances filled in the second trench. The isolation can be divided into optical isolation and electronic isolation. Filling the second trench with opaque metal can be For optical isolation, the second trench is filled with non-conductive silicon oxide for electrical isolation.
以上所述，仅为本发明的具体实施方式，但是，本发明的保护范围不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替代，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention, All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
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