CN108346440B - Bias generating circuit and control circuit of memory - Google Patents
Bias generating circuit and control circuit of memory Download PDFInfo
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Abstract
The invention provides a bias voltage generating circuit and a control circuit of a memory, comprising: a first power-up sequence and a second power-up sequence. In a first power-up sequence, a first voltage signal is generated through a first power-up circuit, and when the first voltage signal reaches a first preset voltage, a charge pump generates a pump bias voltage; in a second power-up sequence, a second voltage signal is generated through the second power-up sequence, and when the second voltage signal reaches a second predetermined voltage, a bias switch is opened, and a pump bias voltage generated by the charge pump is output through the bias switch to form an output bias voltage. Wherein the time when the second voltage signal reaches the second predetermined voltage is later than the time when the first voltage signal reaches the first predetermined voltage. In the bias generation circuit provided by the invention, the purpose of forming stable output bias more quickly is realized through two power-on sequences.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a bias generation circuit and a control circuit of a memory.
Background
When the memory performs corresponding operations, such as read operations, erase operations, etc., a bias voltage is applied to the memory cell array, and the bias voltage is generally provided by a bias voltage generating circuit.
The bias voltage generating circuit generates a bias voltage according to a voltage signal. That is, when the voltage signal reaches its predetermined voltage, the bias generation circuit is turned on, so that a bias can be generated. The voltage value of the generated voltage signal is not directly up to the predetermined voltage value, that is, when the voltage signal starts to be generated, the voltage value is usually lower, and at this time, the bias generation circuit is not conducted; the voltage value of the generated voltage signal gradually rises along with the time and reaches a preset voltage, and the bias voltage generating circuit is conducted and starts to provide bias voltage.
However, since the device for controlling the turn-on of the bias voltage generating circuit is affected by various factors (e.g., the forming process or the ambient temperature), the turn-on state of the device is not stable in the initial state, so that the bias voltage generating circuit cannot provide a stable bias voltage in the initial stage of the turn-on, and if the unstable bias voltage is directly applied to the memory cell array, the phenomenon of malfunction is easily caused.
Disclosure of Invention
The present invention provides a bias voltage generating circuit and a control circuit of an MTP device to solve the problem that the conventional bias voltage generating circuit cannot generate a stable bias voltage quickly.
To solve the above technical problem, the present invention provides a bias voltage generating circuit, including:
a first power-up sequence comprising a first power-up circuit and a charge pump, the first power-up circuit generating a first voltage signal, the charge pump generating a pump bias voltage when the first voltage signal reaches a first predetermined voltage;
a second power-up sequence comprising a second power-up circuit and a bias switch, the second power-up circuit generating a second voltage signal, the bias switch being open when the second voltage signal reaches a second predetermined voltage, the pump bias generated by the charge pump being output via the bias switch to form an output bias;
wherein the time when the second voltage signal reaches the second predetermined voltage is later than the time when the first voltage signal reaches the first predetermined voltage.
Optionally, the first power-up sequence further includes a first transistor, a gate of the first transistor is connected to an output terminal of the first power-up circuit, a source of the first transistor is connected to the charge pump, and a drain of the first transistor is grounded.
Optionally, the first transistor is an N-type transistor.
Optionally, the second power-up sequence further includes a second transistor, a gate of the second transistor is connected to an output terminal of the second power-up circuit, a source of the second transistor is connected to the bias switch, and a drain of the second transistor is grounded.
Optionally, the second transistor is an N-type transistor.
Optionally, the first power-up sequence further includes a first inverter, and the first inverter is connected between the first power-up circuit and the charge pump.
Optionally, the second power-up sequence further includes a second inverter, and the second inverter is connected between the second power-up circuit and the bias switch.
Optionally, the first power-up sequence further includes a clock generator, an output end of the clock generator is connected to the charge pump, when the first voltage signal reaches a first predetermined voltage, the clock generator generates a clock signal, and the charge pump generates a pump bias voltage by using the clock signal.
Optionally, the charge pump is a negative charge pump or a positive charge pump.
Optionally, the bias switch is a positive bias switch or a negative bias switch.
It is still another object of the present invention to provide a control circuit of a memory, which includes the bias voltage generating circuit and a memory cell array, wherein the bias voltage generating circuit generates a bias voltage and applies the bias voltage to the memory cell array.
Optionally, the memory is an MTP memory.
Optionally, the memory cell array is a P-type memory cell array.
Optionally, when performing a read operation, the bias generation circuit generates a negative bias and applies the negative bias to the select gate of the memory cell array.
Optionally, when performing an erase operation, the bias voltage generation circuit generates a positive bias voltage and applies the positive bias voltage to the select gate of the memory cell array.
The bias voltage generating circuit provided by the invention is provided with two power-on sequences, wherein a first voltage signal of a first power-on circuit reaches a first preset voltage (a first power-on reset signal) preferentially, so that a charge pump starts to generate pump bias voltage; after the pump bias can generate a stable bias, the second voltage signal of the second power-on circuit reaches a second predetermined voltage (a second power-on reset signal), and the bias switch is controlled to be turned on to output the stable output bias. And, the time difference of the first power-up sequence and the second power-up sequence for performing the power-up process can be adjusted by setting the voltage values of the first predetermined voltage and the second predetermined voltage. And the voltage value of the first power-on reset signal is set, so that the charge pump can start to execute the pump operation earlier, and the aim of forming stable output bias voltage more quickly is fulfilled. Because the output bias voltage generated by the bias voltage generating circuit is stable bias voltage, when the bias voltage generating circuit is applied to the memory to realize the corresponding operation of the memory, the phenomenon of misoperation can be effectively avoided.
Drawings
FIG. 1 is a schematic diagram of a control circuit of a memory;
FIG. 2 is a schematic diagram of a bias voltage generation circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a bias voltage generated by a conventional bias voltage generating circuit;
FIG. 4 is a timing diagram of the bias voltage generation circuit in the present invention;
FIG. 5 is a diagram illustrating a control circuit of a memory according to an embodiment of the invention.
Detailed Description
As described in the background, the conventional bias voltage generation circuit cannot provide a stable bias voltage at the initial stage of the turn-on. Therefore, when an unstable bias is directly applied to the memory cell array, the phenomenon of misoperation is easily caused.
Fig. 1 is a control circuit of a memory, which includes a bias voltage generating circuit 10 and a memory cell array 20, wherein a bias voltage is generated by the bias voltage generating circuit 10 and applied to the memory cell array 20 to perform a corresponding operation on the memory. Wherein, the bias voltage generating circuit 10 includes: a Power Up Circuit (Power Up Circuit)11, wherein the Power Up Circuit 11 generates a voltage signal Vpw, and when the voltage signal Vpw reaches a predetermined voltage, the predetermined voltage Vpw forms a Power-on reset signal POR to turn on the bias voltage generating Circuit 10; a Charge Pump (Charge Pump)12, the Charge Pump 12 generating a Pump bias voltage Vp according to a voltage signal generated by the power-on circuit 11.
When the bias generation circuit 10 starts operating, the power-up circuit 11 generates a gradually increasing voltage signal Vpw, and when the voltage signal Vpw rises to a predetermined voltage (power-on reset signal POR), the charge pump 12 starts performing a pumping operation (Starting pump) and generates a pump bias voltage Vp. Due to the influence of the forming process or the ambient temperature, the on-state of the device for controlling the turn-on of the bias voltage generation circuit is unstable, so that the power-on reset signal POR cannot be well controlled or even varies, and the on-state of the bias voltage generation circuit 10 is affected, thereby causing the instability of the pump bias voltage Vp generated at the initial stage of the pump operation. In addition, in the bias generation circuit shown in fig. 1, it takes a long time to generate a stable bias.
To this end, the present invention provides a bias voltage generating circuit, comprising:
a first power-up sequence comprising a first power-up circuit and a charge pump, an output of the first power-up circuit being connected to the charge pump, the first power-up circuit generating a first voltage signal, the charge pump generating a pump bias voltage when the first voltage signal reaches a first predetermined voltage;
a second power-up sequence, wherein the second power-up sequence comprises a second power-up circuit and a bias switch, an output end of the second power-up circuit is connected with the bias switch, the second power-up circuit generates a second voltage signal, the bias switch is turned on when the second voltage signal reaches a second predetermined voltage, and a pump bias voltage generated by the charge pump is output through the bias switch to form an output bias voltage;
wherein the time when the second voltage signal reaches the second predetermined voltage is later than the time when the first voltage signal reaches the first predetermined voltage.
The bias generating circuit provided by the invention is provided with two power-on sequences, the pump bias is generated through the first power-on sequence, and the output of the bias is controlled through the second power-on sequence to form the output bias. Wherein, the first voltage signal of the first power-on circuit reaches the first predetermined voltage (the first power-on reset signal) preferentially, the charge pump starts to generate the pump bias voltage, and the unstable bias voltage generated in the initial stage of the pump operation executed by the charge pump is not output; as the pump bias generated by the charge pump tends to stabilize, the second voltage signal of the second power-on circuit reaches a second predetermined voltage (a second power-on reset signal), and the bias switch opens to cause the stabilized pump bias output to form the output voltage. That is, the present invention can filter the unstable pump bias generated by the charge pump at its initial stage by using two power-up sequences, thereby ensuring that the output bias is a stable bias.
The bias generation circuit and the control circuit of the memory according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a schematic diagram of a bias voltage generating circuit according to an embodiment of the invention, and as shown in fig. 2, the bias voltage generating circuit 100 includes:
a first power-up sequence 110, the first power-up sequence 110 comprising a first power-up circuit 111 and a charge pump 112, an output of the first power-up circuit 111 being connected to the charge pump 112, the first power-up circuit 111 generating a first voltage signal Vpw1, the charge pump 112 generating a pump bias voltage when the first voltage signal Vpw1 reaches a first predetermined voltage; that is, when the first voltage signal Vpw1 reaches a first predetermined voltage, the first voltage signal serves as a first power-on reset signal POR1, so that the first power-on sequence is turned on;
a second power-up sequence 120, the second power-up sequence 120 including a second power-up circuit 121 and a bias switch 122, an output terminal of the second power-up circuit 121 being connected to the bias switch 122, the second power-up circuit 121 generating a second voltage signal Vpw2, the bias switch 122 being turned on when the second voltage signal Vpw2 reaches a second predetermined voltage, the pump bias voltage Vp generated by the charge pump 112 being output via the bias switch 122 to form an output bias voltage Vout; that is, when the second voltage signal Vpw2 reaches the second predetermined voltage, the second voltage signal serves as the second power-on reset signal POR2, so that the second power-on sequence is turned on.
The time when the second voltage signal Vpw2 reaches the second predetermined voltage is later than the time when the first voltage signal Vpw1 reaches the first predetermined voltage, so that the first power-up sequence 110 can perform a power-up procedure prior to the second power-up sequence 120, such that the unstable bias voltage generated by the charge pump 112 in the initial stage of the pump operation cannot be output; the second power-up sequence 120 begins to perform the power-up process as the voltage signal applied to the charge pump 112 becomes stable so that the pump charge 112 can generate a stable bias voltage, which ensures that the output bias voltage is a stable bias voltage.
It can be seen that the first power-on circuit 111 generates the first predetermined voltage Vpw1 earlier than the second power-on circuit 121 generates the second predetermined voltage Vpw2, i.e., there is a time difference between the formation of the first power-on reset signal POR1 and the formation of the second power-on reset signal POR2, so that the output bias voltage can be ensured to be a stable bias voltage. Of course, in an actual application process, the time for forming the first power-on reset model POR1 and the time for forming the second power-on reset signal POR2 may be set according to actual requirements. For example, the first power-on circuit 111 and the second power-on circuit 121 generate positive voltage signals as the first voltage signal Vpw1 generated by the first power-on circuit 111 gradually increases and reaches a first predetermined voltage (the first power-on reset signal POR 1); as the voltage rises, the second voltage signal Vpw2 generated by the second power-on circuit 121 gradually increases and reaches a second predetermined voltage (the second power-on reset signal POR 2). Therefore, the two power-up sequences can perform the power-up process at different times by setting the first predetermined voltage Vpw1 and the second predetermined voltage Vpw2 to have a certain voltage difference, so that the time for forming the first power-on reset signal POR1 is different from the time for forming the second power-on reset signal POR 2. Alternatively, the voltage value of the first predetermined voltage Vpw1 may be decreased to generate the first power-on reset signal POR1 more quickly, so that the charge pump 112 starts to perform the pumping operation earlier, and thus a stable bias voltage may be formed in a shorter time, thereby achieving the purpose of generating the stable bias voltage quickly.
With continued reference to fig. 2, the first power-up sequence 110 further includes a first transistor 113, a gate of the first transistor 113 is connected to the output terminal of the first power-up circuit 111, and a source of the first transistor 113 is connected to the charge pump 112. That is, the first power-up circuit 111, the charge pump 112 and the first transistor 113 form a conductive loop, and the power-up process of the first power-up sequence 110 can be realized by controlling the conduction of the first transistor 113. Specifically, when the first voltage signal Vpw1 applied to the gate of the first transistor 113 reaches its threshold voltage, and the first voltage signal Vpw1 generated by the first power-up circuit 110 reaches its first predetermined voltage, the first transistor 113 is turned on, and the first power-up sequence 110 begins to perform a power-up process. Further, the first transistor may be an N-type transistor.
Further, the first power-up sequence 110 further includes a first inverter 114, and the first inverter 114 is connected between the first power-up circuit 110 and the charge pump 112. Further, the first power-up sequence 110 further comprises a clock generator 115. In this embodiment, an input end of the first inverter 114 is connected to an output end of the first power-on circuit 111, an output end of the first inverter 114 is connected to an input end of the clock generator 115, and an output end of the clock generator 115 is connected to an input end of the charge pump 112. In operation, the first voltage signal Vpw1 generated by the first power-up circuit 111 is applied to the clock generator 115 through the first inverter 114, such that the clock generator 115 generates a clock signal, and the clock signal is applied to the charge pump 112, such that the charge pump 112 can generate the pump bias voltage Vp using the clock signal.
With continued reference to fig. 2, the output terminal of the charge pump 112 is connected to the input terminal of the bias switch 122, i.e., when the bias switch 122 is turned on, the pump bias voltage Vp generated by the charge pump 112 is output through the bias switch 122. The bias voltage generating circuit 100 can be used for generating a positive bias voltage and can also be used for generating a negative bias voltage. When used to generate a negative bias, a negative charge pump may be provided for generating a negative pump bias; accordingly, when used to generate a positive bias voltage, a positive charge pump may be provided for generating the positive pump bias voltage.
In this embodiment, the first power-up sequence 110 is implemented by controlling the conduction of the transistor. Therefore, in the first power-up sequence 110, when the first voltage signal Vpw1 reaches the first predetermined signal, the conduction of the first transistor 113 is unstable due to the influence of the process, temperature, and the like of the first transistor 113, and thus the charge pump 112 cannot generate a stable pump bias voltage in the initial stage of the pump operation. By controlling the bias switch 122 to be turned on and off through the second power-up sequence 120, the unstable bias generated by the charge pump is not output, and only the stable bias is output, thereby avoiding the influence of the transistor switch.
Similar to the first power-up sequence 110, the second power-up sequence 120 may also include a second transistor 123, and the power-up process of the second power-up sequence 120 is implemented by controlling the conduction of the second transistor 123. As shown in fig. 2, a gate of the second transistor 123 is connected to the output terminal of the second power-up circuit 121, and a source of the second transistor 123 is connected to the bias switch 122. That is, when the second voltage signal Vpw2 generated by the second power-up circuit 121 reaches a second predetermined voltage, the second transistor 123 is turned on, and the bias switch 122 is turned on. Specifically, the second transistor 123 may be an N-type transistor.
In this embodiment, the second power-up sequence 120 also includes a second inverter 124, and the second inverter 124 is connected between the second power-up circuit 121 and the bias switch 122. That is, the second voltage signal Vpw2 generated by the second power-up circuit 120 is applied to the bias switch 122 through the second inverter 124, so as to control the bias switch 122 to be turned on or off. Further, in this embodiment, the bias switch 122 may be a positive bias switch or a negative bias switch, as long as the bias switch 122 is turned on after the charge pump 112 performs the pumping operation to output the stable output bias.
FIG. 3 is a timing diagram illustrating the generation of a bias voltage by a bias voltage generation circuit according to the prior art, and FIG. 4 is a timing diagram illustrating the generation of a bias voltage by a bias voltage generation circuit according to the present invention, wherein VDD is a power voltage applied to a first power-up circuit and a second power-up circuit, so as to generate a first voltage signal Vpw1 and a second voltage signal Vpw2, respectively; the abscissa represents time and the ordinate represents voltage value. As can be seen from fig. 3 and 4, in the conventional bias voltage generating circuit, when the power-on circuit generates the voltage signal Vpw to form the power-on reset signal POR, the power-on reset signal POR may generate a certain fluctuation, so that the charge pump forms an unstable bias voltage. In the bias voltage generating circuit of the present invention, the first power-on reset signal POR1 is preferentially generated, and the second power-on reset signal POR2 starts to be generated on the basis of the stability of the first power-on reset signal POR1, so that the output voltage Vout is a stable voltage. In addition, in the present invention, the voltage value of the first predetermined voltage Vpw1 is adjusted to be lower, so that the first power-on reset signal POR1 can be formed earlier and a pumping operation (starting pump) is performed, thereby achieving the purpose of generating a stable bias voltage quickly.
Based on the bias voltage generating circuit, the invention also provides a control circuit of the MTP device, which comprises the bias voltage generating circuit and the memory cell array, wherein the bias voltage generating circuit generates a bias voltage and applies the bias voltage to the memory cell array.
Fig. 5 is a schematic diagram of a control circuit of a memory according to an embodiment of the invention, and as shown in fig. 5, the control circuit of the memory includes a bias voltage generating circuit and a memory cell array 200. Wherein the bias voltage generating circuit includes:
a first power-up sequence 110, the first power-up sequence 110 comprising a first power-up circuit 111 and a charge pump 112, an output of the first power-up circuit 111 being connected to the charge pump 112, the first power-up circuit 111 generating a first voltage signal Vpw1, the charge pump 112 generating a pump bias voltage when the first voltage signal Vpw1 reaches a first predetermined voltage;
a second power-up sequence 120, the second power-up sequence 120 including a second power-up circuit 121 and a bias switch 122, an output terminal of the second power-up circuit 121 being connected to the bias switch 122, the second power-up circuit 121 generating a second voltage signal Vpw2, the bias switch 122 being turned on when the second voltage signal Vpw2 reaches a second predetermined voltage, the pump bias voltage Vp generated by the charge pump 112 being output via the bias switch 122 to form an output bias voltage Vout;
wherein the time when the second voltage signal Vpw2 reaches the second predetermined voltage is later than the time when the first voltage signal Vpw1 reaches the first predetermined voltage.
As described above, the bias voltage generating circuit can rapidly generate a stable output bias voltage, which is applied to the memory cell array 200, so as to realize precise operation of the memory cells, and avoid the problem of misoperation caused by the large fluctuation of the first power-on reset signal POR 1. The memory cells in the memory cell array 200 include select gates SG, word lines WL, source lines SL, and bit lines BL.
Specifically, the bias voltage generating circuit can be used for generating a negative bias voltage and can also be used for generating a positive bias voltage, so that the bias voltage generating circuit can be applied to different occasions according to actual memory types or different operations. In this embodiment, the bias voltage generation circuit is applied to an MTP device, and is used to implement a read operation or an erase operation of the MTP device. Taking the memory cell array in the MTP device as a P-type memory cell array as an example, when the MTP device needs to perform a read operation, a negative bias voltage can be generated by a bias voltage generating circuit and applied to a select gate of the memory cell array 200; when the MTP device needs to perform a read operation, a positive bias voltage can be generated by a bias voltage generating circuit and applied to a selection grid of the memory cell array. In this embodiment, the memory is an MTP memory, but in other embodiments, the memory may be other types of memories, such as an OTP (one time programmable memory) and the like, which is not limited herein.
In summary, the bias voltage generating circuit provided by the present invention has two power-up sequences, the first power-up sequence controls the pump charge to generate the pump bias voltage, and the second power-up sequence controls the bias switch to turn on to output the stable output bias voltage after the pump bias voltage can generate the stable bias voltage. Specifically, the time difference between the first power-on sequence and the second power-on sequence in the power-on process can be adjusted by setting the voltages of the first power-on reset signal and the second power-on reset signal. In addition, the voltage value of the first power-on reset signal can be set, so that the charge pump can start to execute the pump operation earlier, and the purpose of forming stable output bias voltage more quickly is achieved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (17)
1. A bias voltage generation circuit, comprising:
a first power-up sequence comprising a first power-up circuit and a charge pump, the first power-up circuit generating a first voltage signal, the charge pump generating a pump bias voltage when the first voltage signal reaches a first predetermined voltage;
a second power-up sequence comprising a second power-up circuit and a bias switch, the second power-up circuit generating a second voltage signal, the bias switch being open when the second voltage signal reaches a second predetermined voltage, the pump bias generated by the charge pump being output via the bias switch to form an output bias;
wherein the time when the second voltage signal reaches the second predetermined voltage is later than the time when the first voltage signal reaches the first predetermined voltage.
2. The bias voltage generation circuit according to claim 1, wherein the first power-up sequence further comprises a first transistor, a gate of the first transistor is connected to an output of the first power-up circuit, a source of the first transistor is connected to the charge pump, and a drain of the first transistor is connected to ground.
3. The bias voltage generating circuit according to claim 2, wherein the first transistor is an N-type transistor.
4. The bias voltage generation circuit according to claim 1, wherein the second power-up sequence further comprises a second transistor, a gate of the second transistor is connected to the output of the second power-up circuit, a source of the second transistor is connected to the bias switch, and a drain of the second transistor is connected to ground.
5. The bias voltage generating circuit according to claim 4, wherein the second transistor is an N-type transistor.
6. The bias voltage generating circuit according to claim 1, wherein the first power-up sequence further comprises a first inverter connected between the first power-up circuit and the charge pump.
7. The bias voltage generation circuit according to claim 1, wherein the second power-up sequence further includes a second inverter connected between the second power-up circuit and the bias switch.
8. The bias voltage generation circuit according to claim 1, wherein the first power-up sequence further comprises a clock generator, an output of the clock generator being connected to the charge pump, the clock generator generating a clock signal when the first voltage signal reaches a first predetermined voltage, the charge pump generating a pump bias voltage using the clock signal.
9. The bias voltage generating circuit according to claim 1, wherein the charge pump is a negative charge pump.
10. The bias voltage generating circuit according to claim 1, wherein the charge pump is a positive charge pump.
11. The bias voltage generation circuit of claim 1, wherein the bias switch is a positive bias switch.
12. The bias voltage generating circuit according to claim 1, wherein the bias switch is a negative bias switch.
13. A control circuit of a memory, comprising the bias generation circuit according to any one of claims 1 to 12 and a memory cell array, wherein the bias generation circuit generates a bias voltage and applies the bias voltage to the memory cell array.
14. The control circuit of memory as claimed in claim 13, wherein the memory is an MTP memory.
15. The control circuit of a memory as claimed in claim 14, wherein the memory cell array is a P-type memory cell array.
16. The control circuit of claim 15, wherein the bias generation circuit generates a negative bias and applies the negative bias to the select gate of the memory cell array when performing a read operation.
17. The memory control circuit of claim 15, wherein the bias voltage generating circuit generates a positive bias voltage and applies the positive bias voltage to the select gate of the memory cell array when performing an erase operation.
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| Switched positive/negative charge pump design using standard CMOS transistors;M. Gh. Mohammad等;《 IET Circuits, Devices & Systems 》;20100112;全文 * |
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| CN108346440A (en) | 2018-07-31 |
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