CN108345506A - A kind of SSD hard disks under multiple CPU - Google Patents
A kind of SSD hard disks under multiple CPU Download PDFInfo
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- CN108345506A CN108345506A CN201810279120.8A CN201810279120A CN108345506A CN 108345506 A CN108345506 A CN 108345506A CN 201810279120 A CN201810279120 A CN 201810279120A CN 108345506 A CN108345506 A CN 108345506A
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- 238000007739 conversion coating Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 9
- 238000013468 resource allocation Methods 0.000 abstract description 9
- 239000002699 waste material Substances 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 description 10
- 238000013461 design Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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Abstract
The present invention provides the SSD hard disks under a kind of multiple CPU, the SSD hard disks include：First processor, the first processor are responsible for the data processing of the front ends Host NVMe；Second processor, the second processor are responsible for the data processing of flash memory conversion coating；Third processor, the third processor are responsible for the data processing of the rear ends NAND, wherein the SSD hard disks further include：Fourth processor, wherein the fourth processor is responsible for the data processing of non-cpu resource.When solving lower of certain read-write mode of host in the prior art and especially being weighed there are one cpu load, host cannot obtain the resources such as the SRAM that another CPU occupies, the technical issues of resulting in waste of resources, the resource allocation realized for multi -CPU layer optimizes, it is suitble to some loads not heavy task simultaneously, only need a cpu resource, but when needing other resources such as many SRAM, it can obtain enough non-cpu resources and accelerate task processing, multiple CPU layers can be responsible for scheduling of resource, the technique effect of logical centralization there are one CPU.
Description
Technical field
The present invention relates to the SSD hard disks under field of computer technology more particularly to a kind of multiple CPU.
Background technology
The SSD controller SOC (solid-state hard disk controller System on Chip/SoC) of mainstream generally comprise three processors, and 1
A responsible relevant business of the front ends Host NVMe, is properly termed as Host CPU (host server)；1 is responsible for processing FTL
(Flash transform layer) flash memory conversion coating, converts to NAND Flash the access of the sectors host LBA form to
(flash memory memory) block, the access of page form are properly termed as Core CPU (core processor)；Last 1 is responsible for management NAND
The CPU of rear end is properly termed as Media CPU (Media Processor).With the continuous promotion that host needs SSD performances, 3
The processing capacity of CPU has not reached requirement, so there are the SSD controller (solid-state hard disk controller) of 4 CPU
The processing capacity of framework, each CPU of framework of 4 CPU of mainstream is identical design symmetry.
But present inventor has found above-mentioned technology extremely during inventive technique scheme in realizing the embodiment of the present application
It has the following technical problems less：
The read-write mode of host in the prior art is very random, there are one under certain read-write mode in host only
When cpu load is especially heavy, host cannot obtain the resources such as the SRAM (random access memory) that another CPU occupies, and cause resource
Waste.
Invention content
An embodiment of the present invention provides the SSD hard disks under a kind of multiple CPU, solve the read-write mode of host in the prior art
Very random, when only especially heavy there are one cpu load under certain read-write mode in host, host cannot obtain another
The resources such as the SRAM that CPU occupies the technical issues of resulting in waste of resources, realize the resource allocation optimization for multi -CPU layer,
It is very suitable for the task that some loading are not weighed simultaneously, it is only necessary to a cpu resource, but need other moneys such as many SRAM
When source, enough non-cpu resources can be obtained and accelerate task processing, multiple CPU layers can be responsible for scheduling of resource there are one CPU, patrol
Technique effect in compiling.
In view of the above problems, it is proposed that the embodiment of the present application is in order to provide the SSD hard disks under a kind of multiple CPU.
The present invention provides the SSD hard disks under a kind of multiple CPU, the SSD hard disks include：
First processor, the first processor are responsible for the data processing of the front ends Host NVMe；Second processor, described
Two processors are responsible for the data processing of flash memory conversion coating；Third processor, the third processor are responsible for the rear ends NAND
Data processing, wherein the SSD hard disks further include：Fourth processor, wherein the fourth processor is responsible for non-cpu resource
Data processing.
Preferably, the fourth processor is in layer where the first processor, and, the fourth processor with it is described
The asymmetric setting of first processor.
Preferably, the fourth processor is in layer where the second processor, and, the fourth processor with it is described
The asymmetric setting of second processor.
Preferably, the fourth processor is in layer where the third processor, and, the fourth processor with it is described
The asymmetric setting of third processor.
Said one in the embodiment of the present application or multiple technical solutions at least have following one or more technology effects
Fruit：
1. the SSD hard disks under a kind of multiple CPU provided by the embodiments of the present application, the SSD hard disks include：First processing
Device, the first processor are responsible for the data processing of the front ends Host NVMe；Second processor, the second processor are responsible for flash memory
The data processing of conversion coating；Third processor, the third processor are responsible for the data processing of the rear ends NAND, wherein institute
Stating SSD hard disks further includes：Fourth processor, wherein the fourth processor is responsible for the data processing of non-cpu resource.It solves existing
There is the read-write mode of host in technology very random, when only there are one CPU loading spies under certain read-write mode in host
Not Chong when, host cannot obtain the resources such as the SRAM that another CPU occupies, and the technical issues of resulting in waste of resources, realize
It is optimized for the resource allocation of multi -CPU layer, while being very suitable for the task that some loading are not weighed, it is only necessary to a CPU moneys
Source, but when other resources such as many SRAM of needs, enough non-cpu resources can be obtained and accelerate task processing, it is CPU layers multiple
It can be responsible for scheduling of resource, the technique effect of logical centralization there are one CPU.
Layer where 2. the embodiment of the present application is in the first processor by the fourth processor, and, the described 4th
Processor and the asymmetric setting of the first processor.It further is designed as asymmetric design by every layer, enhancing exists simultaneously more
The resource occupation of wherein 1 CPU of a that layers of CPU, the flexible technique effect of resource allocation.
Above description is only the general introduction of technical solution of the present invention, in order to better understand the technical means of the present invention,
And can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, below the special specific implementation mode for lifting the present invention.
Description of the drawings
Fig. 1 is a kind of double host server schematic diagrames of the SSD hard disks under multiple CPU in the embodiment of the present invention；
Fig. 2 is a kind of double-core central server schematic diagram of the SSD hard disks under multiple CPU in the embodiment of the present invention；
Fig. 3 is a kind of double media server schematic diagrames of the SSD hard disks under multiple CPU in the embodiment of the present invention.
Specific implementation mode
An embodiment of the present invention provides the SSD hard disks under a kind of multiple CPU, technical solution general thought provided by the invention
It is as follows：First processor, the first processor are responsible for the data processing of the front ends Host NVMe；Second processor, described second
Processor is responsible for the data processing of flash memory conversion coating；Third processor, the third processor are responsible for the number of the rear ends NAND
According to processing, wherein the SSD hard disks further include：Fourth processor, wherein the fourth processor is responsible for the number of non-cpu resource
According to processing.The read-write mode for solving host in the prior art is very random, there are one under certain read-write mode in host only
When CPU loading are especially heavy, host cannot obtain the resources such as the SRAM that another CPU occupies, the skill to result in waste of resources
Art problem realizes the resource allocation optimization for multi -CPU layer, while being very suitable for the task that some loading are not weighed, only
When needing a cpu resource, but needing other resources such as many SRAM, enough non-cpu resources can be obtained and accelerate task
Processing, multiple CPU layers can be responsible for scheduling of resource, the technique effect of logical centralization there are one CPU.
Technical solution of the present invention is described in detail below by attached drawing and specific embodiment, it should be understood that the application
Specific features in embodiment and embodiment are the detailed description to technical scheme, rather than to present techniques
The restriction of scheme, in the absence of conflict, the technical characteristic in the embodiment of the present application and embodiment can be combined with each other.
In order to become apparent from the SSD hard disks under a kind of multiple CPU that open the embodiment of the present application is provided, correlation is described below
Term.
Hard disk, that is, solid-state hard disk SSD (Solid State Drives), referred to as consolidates disk, and solid state disk is stored with solid-state electronic
Chip array and manufactured hard disk, are made of control unit and storage unit (FLASH chip, dram chip).The SSD hard disks
Have the characteristics that read or write speed is fast, low-power consumption, noiseless, anti-vibration, low in calories, small, operating temperature range is big.
NVMe (Non-Volatile Memory express) is the one of a kind of similar AHCI of the foundation on M.2 interface
Kind agreement, is the agreement exclusively for flash-type design Storage.Communication link of the NVMe specifications between SSD controller and operating system
It connects, improves the performance and reliable characteristic of SSD.The specific advantages of NVMe include：Performance has the promotion of several times；It can reduce and be delayed over
50%；The available IOPs of NVMe PCIe SSD decuple high-end enterprise grade SATA SSD；Automatic power consumption state switching and dynamic
Managing power consumption function substantially reduces power consumption；Support the expandability of following 10 years technologies development.
NAND is computer flash memory device, is a kind of storage scheme more better than hard disk drive, low no more than 4GB
It shows to be still apparent in capacity applications.Nand flash memory is a kind of nonvolatile storage technologies, that is, remains to preserve data after powering off.
The developing goal of nand flash memory is exactly to reduce per bit storage cost, improve memory capacity.
FTL is referred to as flash translation layer (FTL) (Flash Translation Layer are referred to as " FTL ").FTL is a NAND
A conversion layer between flash chip and base file system, it enables operating system and file system as access hard disk one
Sample accesses NAND flash memory equipment.
Embodiment one
Fig. 1 to Fig. 3 is a kind of schematic diagram of the SSD hard disks under multiple CPU in the embodiment of the present invention.Such as Fig. 1 to Fig. 3 institutes
Show, the SSD hard disks include：
First processor, the first processor are responsible for the data processing of Host (host) front end NVMe.Wherein, described
SSD hard disks further include：Fourth processor, wherein the fourth processor is responsible for the data processing of non-cpu resource.
Further, the fourth processor is in layer where the first processor, and, the fourth processor and institute
State the asymmetric setting of first processor.
Specifically, the SSD hard disks include：First processor, second processor, third processor and fourth process
Device.The first processor is responsible for the data processing of the front ends Host NVMe, is properly termed as Host CPU (host server)；It is described
Fourth processor is responsible for the data processing of non-cpu resource；Layer where the fourth processor is in the first processor,
And the fourth processor and the asymmetric setting of the first processor.2 CPU, which are used, when the SSD hard disks handles same industry
The layer is designed as asymmetric design by the layer of business, and the resource that enhancing exists simultaneously wherein 1 CPU of this layer of multiple CPU accounts for
With, and in the resource scheduling algorithm for operating above this layer, the loading condition of this layer of each CPU is responsible for when being read and write according to host
Other resources of the dispatching distribution in addition to cpu resource, resource allocation are flexible.The first processor is designed as host CPU, it is described
Fourth processor is designed as from CPU, can be obtained enough non-cpu resources and be accelerated task processing.
Second processor, the second processor are responsible for the data processing of flash memory conversion coating.
Further, the fourth processor is in layer where the second processor, and, the fourth processor and institute
State the asymmetric setting of second processor.
Specifically, the second processor is responsible for the data of FTL (Flash transform layer) flash memory conversion coating
Processing, converts the access of the sectors host LBA form to the access to NAND Flash (flash memory memory) blocks or page form, can be with
Referred to as Core CPU (Core server)；It designs the fourth processor and is in layer where the second processor, and, described the
Four processors and the asymmetric setting of the second processor.Wherein, the second processor is host CPU, the fourth processor
For from CPU, host CPU is responsible for the non-cpu resource of this layer of unified allocation of resources, logical centralization.
Third processor, the third processor are responsible for the data processing of the rear ends NAND.
Further, the fourth processor is in layer where the third processor, and, the fourth processor and institute
State the asymmetric setting of third processor.
Specifically, the third processor is responsible for the data processing of the rear ends NAND, it is properly termed as Media CPU
(Media Processor).The fourth processor is in layer where the third processor, and, the fourth processor with it is described
The asymmetric setting of third processor.Wherein, the third processor is host CPU, and the fourth processor is that can make from CPU
CPU layers of resource allocation is obtained to optimize.
Said one in the embodiment of the present application or multiple technical solutions at least have following one or more technology effects
Fruit：
1. the SSD hard disks under a kind of multiple CPU provided by the embodiments of the present application, the SSD hard disks include：First processing
Device, the first processor are responsible for the data processing of the front ends Host NVMe；Second processor, the second processor are responsible for flash memory
The data processing of conversion coating；Third processor, the third processor are responsible for the data processing of the rear ends NAND, wherein institute
Stating SSD hard disks further includes：Fourth processor, wherein the fourth processor is responsible for the data processing of non-cpu resource.It solves existing
There is the read-write mode of host in technology very random, when only there are one CPU loading spies under certain read-write mode in host
Not Chong when, host cannot obtain the resources such as the SRAM that another CPU occupies, and the technical issues of resulting in waste of resources, realize
It is optimized for the resource allocation of multi -CPU layer, while being very suitable for the task that some loading are not weighed, it is only necessary to a CPU moneys
Source, but when other resources such as many SRAM of needs, enough non-cpu resources can be obtained and accelerate task processing, it is CPU layers multiple
It can be responsible for scheduling of resource, the technique effect of logical centralization there are one CPU.
Layer where 2. the embodiment of the present application is in the first processor by the fourth processor, and, the described 4th
Processor and the asymmetric setting of the first processor.It further is designed as asymmetric design by every layer, enhancing exists simultaneously more
The resource occupation of wherein 1 CPU of a that layers of CPU, the flexible technique effect of resource allocation.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications can be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (4)
1. the SSD hard disks under a kind of multiple CPU, which is characterized in that the SSD hard disks include：
First processor, the first processor are responsible for the data processing of the front ends Host NVMe；
Second processor, the second processor are responsible for the data processing of flash memory conversion coating；
Third processor, the third processor are responsible for the data processing of the rear ends NAND, wherein
The SSD hard disks further include：
Fourth processor, wherein the fourth processor is responsible for the data processing of non-cpu resource.
2. hard disk as described in claim 1, which is characterized in that the fourth processor is in where the first processor
Layer, and, the fourth processor and the asymmetric setting of the first processor.
3. hard disk as described in claim 1, which is characterized in that the fourth processor is in where the second processor
Layer, and, the fourth processor and the asymmetric setting of the second processor.
4. hard disk as described in claim 1, which is characterized in that the fourth processor is in where the third processor
Layer, and, the fourth processor and the asymmetric setting of third processor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810279120.8A CN108345506A (en) | 2018-03-31 | 2018-03-31 | A kind of SSD hard disks under multiple CPU |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810279120.8A CN108345506A (en) | 2018-03-31 | 2018-03-31 | A kind of SSD hard disks under multiple CPU |
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| CN108345506A true CN108345506A (en) | 2018-07-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109597577A (en) * | 2018-12-03 | 2019-04-09 | 郑州云海信息技术有限公司 | A kind of method, system and relevant apparatus handling NVME agreement read write command |
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2018
- 2018-03-31 CN CN201810279120.8A patent/CN108345506A/en active Pending
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| WO2009154998A1 (en) * | 2008-05-27 | 2009-12-23 | Initio Corporation | Ssd with distributed processors |
| CN104102458A (en) * | 2014-06-27 | 2014-10-15 | 北京兆易创新科技股份有限公司 | Multi-core CPU (Central Processing Unit) load balancing method, multi-core CPU and solid state disk |
| CN104965678A (en) * | 2015-07-01 | 2015-10-07 | 忆正科技（武汉）有限公司 | Solid-state storage control method and apparatus and solid-state storage device |
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| CN109597577A (en) * | 2018-12-03 | 2019-04-09 | 郑州云海信息技术有限公司 | A kind of method, system and relevant apparatus handling NVME agreement read write command |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20190807 Address after: 518067 Dongjiaotou Workshop D24/F-02, Houhai Avenue, Shekou Street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: SHENZHEN UNIONMEMORY INFORMATION SYSTEM Co.,Ltd. Address before: 100176 Beijing Daxing District Beijing Economic and Technological Development Zone No. 58 Jinghai Road, No. 5 Building No. 3, No. 305 Applicant before: BEIJING LENOVO SOFTWARE Ltd. |
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Application publication date: 20180731 |