CN108337507A - Scheduling method for high efficiency video coding device - Google Patents

Abstract

The invention relates to a scheduling method, used for a high-efficiency video coding device, the scheduling method comprises a scheduling module of the high-efficiency video coding device receives a plurality of input frame signals to correspondingly generate a control signal to judge whether each input frame signal carries out an intra-frame/inter-frame coding operation; and when the control signal is determined to perform the intra/inter coding operation, the high efficiency video coding apparatus sequentially performs the first coding operation and a second coding operation on a plurality of frame signals within each duty cycle, wherein each duty cycle performs a time corresponding to any one of the first coding operation or any one of the second coding operation on a single luminance frame signal or a single chrominance frame signal in each input frame signal.

Description

Scheduling method for high-efficiency video encoding device

technical field

The present invention refers to a scheduling method for a high-efficiency video encoding device, especially a scheduling method for adaptively adjusting the scheduling sequence of encoding operations for intra-frame input signals to improve the processing efficiency of a high-efficiency video encoding device .

Background technique

Traditionally, a high-efficiency video encoding device can receive audio-visual data including a plurality of input frame signals, and each frame input signal includes a plurality of luma frame signals and a plurality of chroma frame signals, and each luma frame signal and each A chrominance frame signal corresponds to a matrix signal, so that each luminance frame signal and each chrominance frame signal include a plurality of numbered sub-luminance frame signals and a number of numbered sub-chrominance frame signals. Since each sub-brightness frame signal or each sub-chrominance frame signal has a dependency relationship, that is, the sub-brightness frame signal or sub-chrominance frame signal of the latter needs to refer to the sub-brightness frame signal or sub-color frame signal of the former. Therefore, when the high-efficiency video encoding device intends to perform an intra-frame encoding operation, the high-efficiency video encoding device needs to perform corresponding encoding operations on the sub-luminance frame signals or sub-chrominance frame signals one by one (such as a pixel estimation operation, a discrete cosine transform operation, a quantization operation, an inverse quantization operation, an inverse discrete cosine transform operation, and a pixel reconstruction operation), which will cause most of the hardware resources to be in a waiting input signal situation, and its hardware scheduling cannot be effectively utilized. In addition, when the high-efficiency video coding device intends to perform an intra-frame/inter-frame coding operation, the existing high-efficiency video coding device still has to perform coding operations on multiple input frame signals one by one, and the scheduling of hardware resources is also the same Lack of efficiency.

Therefore, it has become an important subject in the art to provide a scheduling method for a high-efficiency video encoding device to improve the processing efficiency of the intra-frame encoding operation and intra-frame/inter-frame encoding operation performed by the high-efficiency video encoding device.

Contents of the invention

Therefore, the main objective of the present invention is to provide an adaptively adjustable scheduling sequence for encoding operations of intra-frame input signals, so as to correspondingly improve the processing efficiency of a high-efficiency video encoding device.

The present invention discloses a scheduling method for a high-efficiency video coding device. The scheduling method includes receiving a plurality of input frame signals by a scheduling module of the high-efficiency video coding device to generate a control signal correspondingly. judging whether an intra-frame/inter-frame coding operation is performed on each input frame signal, and judging by the scheduling module whether each input frame signal is a luma frame signal or a chrominance frame signal; and when the control signal is judged to perform the During the intra-frame/inter-frame coding operation, the high-efficiency video coding device sequentially performs a first coding operation and a second coding operation on a plurality of frame signals in each working cycle; wherein, the first coding The operation sequentially performs a pixel estimation operation, a discrete cosine transform operation, a quantization operation, an inverse quantization operation, an inverse discrete cosine transform operation and a pixel reconstruction operation, and the second encoding operation is a motion compensation operation in sequence , the discrete cosine transform operation, the quantization operation, the inverse quantization operation, the inverse discrete cosine transform operation and the pixel reconstruction operation, and each duty cycle is a single luma frame signal or a single chrominance frame signal in each input frame signal A time corresponding to any operation in the first encoding operation or any operation in the second encoding operation is performed.

The present invention also discloses a high-efficiency video encoding device, which includes a scheduling module for receiving a plurality of input frame signals and correspondingly generating a control signal to determine whether an intra-frame/inter-frame encoding operation is performed on each input frame signal , and used to determine whether each input frame signal is a luminance frame signal or a chrominance frame signal; and a working loop module, coupled to the scheduling module, including an estimation module, a discrete cosine transform module, and a quantization module , an inverse quantization module, an inverse discrete cosine transform module, and a pixel reconstruction module are sequentially coupled to each other; wherein, when the control signal is judged to perform the intra-frame/inter-frame coding operation, the working loop module The first encoding operation and a second encoding operation are sequentially performed on the plurality of frame signals in each working cycle, and the first encoding operation sequentially performs a pixel estimation operation, a discrete cosine transform operation, A quantization operation, an inverse quantization operation, an inverse discrete cosine transform operation, and a pixel reconstruction operation, the second encoding operation sequentially performs a motion compensation operation, the discrete cosine transform operation, the quantization operation, the inverse quantization operation, the The inverse discrete cosine transform operation and the pixel reconstruction operation, and each duty cycle is that a single luminance frame signal or a single chrominance frame signal in each input frame signal performs either operation in the first encoding operation or in the second encoding operation A time corresponding to any operation.

Description of drawings

FIG. 1 is a schematic diagram of a high-efficiency video encoding device according to an embodiment of the present invention.

FIG. 2 is a flow chart of a scheduling process according to an embodiment of the present invention.

FIG. 3 is a flowchart of an intra-frame encoding process according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a luma frame signal and a plurality of chrominance frame signals according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of execution time of intra-frame encoding operations corresponding to a luma frame signal and a plurality of chrominance frame signals according to the embodiment of FIG. 4 .

FIG. 6 is a flowchart of an intra-frame/inter-frame encoding process according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of execution time of intra-frame/inter-frame coding operations corresponding to luma frame signals of multiple input frame signals in an embodiment of the present invention.

FIG. 8 is a schematic diagram of an embodiment of a scheduling module in FIG. 1 .

Symbol Description

1 High-efficiency video encoding device

10 Scheduling Module

11 Estimation Module

12 discrete cosine transform modules

13 quantization module

14 Inverse quantization module

15 Inverse discrete cosine transform module

16 pixel reconstruction module

17, 18 transfer unit

20 Scheduling process

200, 202, 204, 206, 300, 302, 304, 306, 308, 600, 602, 604, 606, 608 steps

30 Intra-frame encoding process

60 Intra/Inter coding process

LM working loop module

S_L luminance frame signal

S_L_0～S_L_15 sub-luminance frame signal

S_Cb, S_Cr Chroma frame signal

S_Cb_16～S_Cb_19, S_Cr_20～S_Cr_23 sub-chroma frame signal

IAP pixel estimation operation

DCT discrete cosine transform operation

Q quantization operation

IQ dequantization operation

IDCT inverse discrete cosine transform operation

REC pixel reconstruction operation

MC Motion Compensation Operation

T1～T8, S1～S8 time points

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a high-efficiency video encoding device 1 according to an embodiment of the present invention. As shown in FIG. 1 , the high-efficiency video encoding device 1 includes a scheduling module 10 and a working loop module LM. Wherein, the scheduling module 10 can be used to receive a plurality of input frame signals, to generate a corresponding control signal to judge each input frame signal to perform an intra-frame coding operation or an intra-frame/inter-frame coding operation, and to judge each input frame signal The input frame signal is a luma frame signal or a chrominance frame signal. The working loop module LM is coupled to the scheduling module 10, and includes an estimation module 11, a discrete cosine transform module 12, a quantization module 13, an inverse quantization module 14, an inverse discrete cosine transform module 15 and a pixel reconstruction module 16 , and are sequentially coupled to each other, each of which can correspondingly perform a pixel estimation operation/a motion compensation operation, a discrete cosine transform operation, a quantization operation, an inverse quantization operation, an inverse discrete cosine transform operation and a pixel Reconstruction operations, and these operations are well known to those skilled in the art, for the sake of brevity, they are not described in detail one by one.

In addition, the quantization module 13 is also coupled to a transfer unit 17 for receiving and outputting a residual signal generated by the quantization module 13 to an intra-frame luminance register or an intra-frame chrominance register (not shown in the figure ), and the pixel reconstruction module 16 is also coupled to another transfer unit 18 for receiving and outputting a reconstruction signal of the pixel reconstruction module 16 to another intra-frame luminance register or another intra-frame chrominance register ( not shown in the figure), so that the relevant signals temporarily stored in the intra-frame luminance register or the intra-frame chrominance register can be used as the requirements for other operations of the high-efficiency video encoding device 1; The register and another intra-frame luminance register receiving the reconstructed signal are not limited to individual independent registers, and may also be different register blocks of the same memory. Similarly, the intra-frame chrominance register is the same. Moreover, the estimation module 11 , the DCT module 12 , the quantization module 13 , the inverse quantization module 14 , the inverse discrete cosine transformation module 15 and the pixel reconstruction module 16 all include a parser (parser), which can be used to receive the scheduling module 10 The generated control signal is used to determine whether at least one input frame signal has been received for intra-frame coding or intra-frame/inter-frame coding, and can also be used to determine whether the input frame signal is a luma frame signal or a chrominance frame signal.

It is worth noting that each frame input signal in this embodiment includes a plurality of luminance frame signals and a plurality of chrominance frame signals, and each luminance frame signal and each chrominance frame signal correspond to a matrix signal, and each luminance frame signal The frame signal and each chrominance frame signal all include a plurality of numbered sub-luminance frame signals and a plurality of sub-chrominance frame signals, and the numbering method can be a Z-type code (as shown in Figure 4 thereafter), but it is not used To limit the scope of the present invention. In this case, the high-efficiency video encoding device 1 in this embodiment first judges that the received input frame signal will be subjected to an intra-frame encoding operation or an intra-frame/inter-frame encoding operation through the scheduling module 10, and at the same time determines whether the input frame signal The signal is a luminance frame signal or a chrominance frame signal, and the above judgment result is output as a control signal and transmitted to the working loop module LM, and then a first encoding operation is performed on a plurality of sub-luminance frame signals and a plurality of sub-chrominance frame signals and a second encoding operation, wherein the first encoding operation sequentially performs a pixel estimation operation, a discrete cosine transform operation, a quantization operation, an inverse quantization operation, an inverse discrete cosine transform operation, and a pixel reconstruction operation, and the second encoding operation performs sequentially The operation of motion compensation, discrete cosine transform, quantization, inverse quantization, inverse discrete cosine transform and pixel reconstruction will be detailed in the following paragraphs.

Further, the scheduling method applicable to the high-efficiency video encoding device 1 of this embodiment can be summarized into a scheduling process 20, which is compiled into a program code and stored in a storage device of the high-efficiency video encoding device 1, and A processor module of the high-efficiency video encoding device 1 performs corresponding operations, and then controls related operations of the scheduling module 10 and the working loop module LM. As shown in FIG. 2 , the scheduling process 20 includes the following steps.

Step 200: start.

Step 202: The scheduling module 10 receives a plurality of input frame signals, and generates a control signal correspondingly to determine whether each input frame signal performs an intra-frame encoding operation or an intra-frame/inter-frame encoding operation; if it is determined to perform an intra-frame encoding operation, proceed to the step 204. If it is determined that the intra-frame/inter-frame coding operation is performed, go to step 206.

Step 204: When the scheduling module 10 determines to perform an intra-frame encoding operation, the high-efficiency video encoding device 1 sequentially performs one of the plurality of sub-luminance frame signals of each luma frame signal and the plurality of sub-chrominance sub-chroma of each chrominance frame signal One of the frame signals undergoes a first encoding operation.

Step 206: When the scheduling module 10 determines to perform the intra-frame/inter-frame coding operation, the high-efficiency video coding device 1 sequentially performs the first coding operation and the second coding operation on multiple frame signals in each working cycle operate.

The program code corresponding to the scheduling process 20 in this embodiment can be correspondingly stored in the scheduling module 10, the estimation module 11, the discrete cosine transformation module 12, the quantization module 13, the inverse quantization module 14, the inverse discrete cosine transformation module 15 and the The pixel reconstruction module 16 (even the transfer units 17, 18) is used to improve the processing performance of the high-performance video encoding device 1, but it is not intended to limit the scope of the present invention. In addition, each duty cycle in this embodiment is a period corresponding to any operation in the first encoding operation or any operation in the second encoding operation for a single luminance frame signal or a single chrominance frame signal in each input frame signal. Time, for example, each duty cycle can be understood as a minimum time interval, so that the estimation module 11, the discrete cosine transform module 12, the quantization module 13, the inverse quantization module 14, the inverse discrete cosine transform module 15 and the pixel reconstruction module Any one of 16 can complete its related operations on a single luminance frame signal (or a single chrominance frame signal). Accordingly, according to the amount of received input frame signals, the first encoding operation and the second encoding operation can be made to correspond Multiple work cycles and are arranged sequentially.

In step 202, the scheduling module 10 generates a corresponding control signal according to the received multiple input frame signals to determine whether to proceed to step 204 (i.e. perform intra-frame encoding operation) or to perform step 206 (i.e. perform intra-frame/inter-frame encoding operation) ), of course, according to different needs, those skilled in the art can also split the judging mechanism corresponding to step 202 into two parts, so as to independently judge whether to perform intra-frame coding operation and independently judge whether to perform intra-frame/frame In this case, the program code corresponding to step 202 can be divided into two subroutine codes to operate independently, or the judgment operation of the program codes corresponding to the two subroutines can be performed sequentially. to limit the scope of the present invention). The operation content of step 204 and step 206 can be further summarized into an intra-frame encoding process 30 or an intra-frame/inter-frame encoding process 60 , and details can be referred to the following paragraphs.

In this embodiment, the intra-frame coding process 30 can also be compiled into another program code, and stored in the storage device of the high-performance video coding device 1, and correspondingly executed by the processor module of the high-performance video coding device 1, and then controlled The relevant operations of the working loop module LM, as shown in FIG. 3 , the intra-frame encoding process 30 includes the following steps.

Step 300: start.

Step 302: In a first duty cycle, the high-efficiency video encoding device 1 performs a first operation on the first sub-luminance frame signal.

Step 304: In a second working period after the first working period, the high-efficiency video encoding device 1 performs the first operation on the first sub-chroma frame signal, and at the same time, the high-efficiency video encoding device 1 performs the first operation on the first sub-luminance frame signal a second operation.

Step 306: In a third working period after the second working period, the high-efficiency video encoding device 1 performs a second operation on the first sub-chrominance frame signal.

Step 308: end.

In this embodiment, according to the control signal received by the working loop module LM and the input frame signal, the intra-frame encoding process 30 for the working loop module LM is correspondingly started. In addition, the scheduling module 10 notifies the working loop module LM of the judging results of the luminance frame signals or chrominance frame signals corresponding to the multiple input frame signals, so that the working loop module LM sequentially processes the multiple sub-frame signals of the luminance frame signals. A first encoding operation is performed on the luma frame signal and the plurality of sub-chroma frame signals of the chroma frame signal.

For example, in this embodiment, if the luma frame signal includes the first sub-luminance frame signal and the chroma frame signal includes the first sub-chroma frame signal, the scheduling module 10 receives the first sub-luminance frame signal in sequence and the first sub-chroma frame signal, and the first operation and the second operation are the pixel estimation operation, the discrete cosine transform operation, the quantization operation, the inverse quantization operation, the inverse discrete cosine transform operation and the pixel reconstruction operation in the sequence of the encoding operation Both in a row. In this case, in step 302, the working loop module LM of the high-efficiency video coding device 1r will perform the first operation on the first sub-luminance frame signal; in step 304, after the first working period r second working period, The working loop module LM will perform the first operation on the first sub-chroma frame signal, and at the same time, the working loop module LM will also perform the second operation on the second sub-luminance frame signal; in step 306, after the second working cycle Three working cycles, the working loop module LM performs a second operation on the second sub-chroma frame signal.

In other words, since there is no interdependent reference relationship between the first sub-luminance frame signal and the first sub-chroma frame signal, the intra-frame encoding process 30 of this embodiment can perform at least two signals r in a single working cycle. The first encoding operation, that is, the working loop module LM in step 304 performs the first operation on the first sub-chroma frame signal and the second operation on the first sub-luminance frame signal. Of course, the brightness frame signal contained in this embodiment The number of sub-chroma frame signals included in the sub-luminance frame signal and the chroma frame signal is only for exemplary illustration, and the number of times of performing step 304 can also be adjusted correspondingly according to the numbers of the sub-luminance frame signal and the sub-chroma frame signal . Accordingly, the intra-frame encoding process 30 first performs the encoding operation of the sub-luminance frame signal, and after the next working cycle, performs the first encoding operation on the sub-luminance frame signal and the sub-chroma frame signal at the same time until the sub-chroma frame signal After the first encoding operation is completed, the first encoding operations of the remaining sub-luminance frame signals are completed one by one.

For example, please refer to FIG. 4 , which is a schematic diagram of a luma frame signal S_L and a plurality of chrominance frame signals S_Cb and S_Cr according to an embodiment of the present invention. The luminance frame signal S_L in this embodiment includes a plurality of sub-luminance frame signals S_L_0~S_L_15 (that is, coded as 0~15 respectively), and the chroma frame signal S_Cb includes sub-chroma frame signals S_Cb_16~S_Cb_19~ (that is, coded as 16-19), the chroma frame signal S_Cr includes sub-chroma frame signals S_Cr_20-S_Cr_23. In addition, please refer to FIG. 5. FIG. 5 is a schematic diagram of the execution time of the intra-frame encoding operation corresponding to the luma frame signal S_L and the multiple chrominance frame signals S_Cb and S_Cr in the embodiment of FIG. 4, wherein the luma frame signal and the chroma frame signals The first encoding operation performed on the signal can be denoted as pixel estimation operation IAP, discrete cosine transform operation DCT, quantization operation Q, inverse quantization operation IQ, inverse discrete cosine transform operation IDCT, and pixel reconstruction operation REC.

Accordingly, at a first time point T1, the pixel estimation operation IAP is performed by the sub-luminance frame signal S_L_0; at a second time point T2, the discrete cosine transform operation DCT is performed by the sub-luminance frame signal S_L_0, and at the same time, the sub-chrominance frame signal S_Cb_16 also performs the pixel estimation operation IAP; from a third time point T3 to a sixth time point T6, the sub-luminance frame signal S_L_0 successively performs quantization operation Q, inverse quantization operation IQ, inverse discrete cosine transform operation IDCT and pixel reconstruction operation REC, at the same time, sub-chroma frame signal S_Cb_16 also performs discrete cosine transform operation DCT, quantization operation Q, inverse quantization operation IQ and inverse discrete cosine transform operation IDCT, and at the end of the sixth time point T6, sub-luminance frame signal S_L_0 has been The first encoding operation is completed, and the corresponding encoding result can be temporarily stored in the luminance register (not shown in the figure), and it is the turn of the sub-luminance frame signal S_L_1 to start the related encoding operation, that is, at a seventh time point T7 , the sub-luminance frame signal S_L_1 performs the pixel estimation operation IAP, and the sub-chroma frame signal S_Cb_16 also performs the pixel reconstruction operation REC, so that the sub-chroma frame signal S_Cb_16 also completes its first encoding operation, and similarly, its corresponding encoding The result can also be temporarily stored in a chroma register (not shown in the figure). Accordingly, the operation mode of every six time points after the eighth time point T8 is repeated from the second time point T2 to the seventh time point T7, so as to simultaneously control the sub-luminance frame signals S_L_1～S_L_15 and the sub-chroma Frame signals S_Cb_17～S_Cb_19, S_Cr_20～S_Cr_23 carry out the encoding operation until the sub-chroma frame signal S_Cr_23 completes the first encoding operation, and the working loop module LM completes the second encoding operation of the remaining sub-luminance frame signals one by one at each subsequent time point. An encoding operation.

Furthermore, an intra/inter coding process 60 corresponding to the intra/inter coding operation in this embodiment can also be compiled into another program code, and stored in the storage device of the high-performance video coding device 1, and The processor module of the high-efficiency video coding device 1 performs corresponding operations, and then controls the related operations of the working loop module LM. As shown in FIG. 6 , the intra/inter coding process 60 includes the following steps.

Step 600: start.

Step 602: During the first working period, the high-efficiency video encoding device 1 performs a first encoding operation on a first input frame signal among the plurality of input frame signals and lasts for six working periods.

Step 604: In the second working period after the first working period, the high-efficiency video encoding device 1 performs a second encoding operation on a second input frame signal among the plurality of frame signals and lasts for six working periods.

Step 606 : Repeat step 604 to perform a second encoding operation on the sub-luminance frame signals and the plurality of sub-chrominance frame signals of the second input frame signal, and continue to perform the first encoding operation on the first input frame signal.

Step 608: end.

In this embodiment, according to the control signal received by the working loop module LM and the input frame signal, the intra-frame/inter-frame encoding process 60 for the working loop module LM is correspondingly started. In addition, the scheduling module 10 also has multiple input The determination result of the luminance frame signal or the chrominance frame signal corresponding to the frame signal is notified to the working loop module LM, so that the working loop module LM sequentially performs the first encoding operation and the second encoding operation on the plurality of frame signals. For example, the scheduling module 10 of this embodiment receives at least one first input frame signal and one second input frame signal, and both the first input frame signal and the second input frame signal include a plurality of brightness frame signals and a plurality of color frame signals, and the scheduling module 10 sequentially receives the first input frame signal and the second input frame signal. In this case, in step 602, in the first working cycle, the working loop module LM of the high-efficiency video encoding device 1 performs the first encoding operation on the first input frame signal and lasts for six working cycles; in step 604, in In the second working cycle after the first working cycle, the working cycle module LM will perform the second encoding operation on the second input frame signal and last for six working cycles; in step 606, repeat the related operations of step 604 to encode the second input The plurality of sub-luminance frame signals and the plurality of sub-chrominance frame signals of the frame signal are subjected to a second encoding operation, and the first encoding operation of the first input frame signal is continued.

In other words, since there is no interdependent reference relationship between the first input frame signal and the second input frame signal, the intra/inter coding process 60 in this embodiment can perform at least two input frame signals in a single working cycle. The first encoding operation and the second encoding, that is, the operation performed by the intra/inter encoding process 60 can be understood as completing the second encoding of the multiple sub-luminance frame signals and the multiple sub-chrominance frame signals of the second input frame signal Before operation, in each working cycle, the working loop module LM simultaneously performs the first encoding operation on the first input frame signal and the second encoding operation on the second input frame signal; once the multiple sub-brightness of the second input frame signal is completed After the second encoding operation of the frame signal and the plurality of sub-chroma frame signals, the working loop module LM only performs the first encoding operation on the first input frame signal in each working cycle thereafter. Accordingly, in this embodiment, the intra-frame/inter-frame encoding process 60 performs the first encoding operation of the first input frame signal prior to the first working cycle, and in the next working cycle, in addition to continuously performing the first input frame signal In addition to the first encoding operation, the second encoding operation is performed on the second input frame signal at the same time and lasts for multiple work cycles, until the second input frame signal completes the second encoding operation, then the first encoding of the first input frame signal is resumed Operation, until the first encoding operation of the first input frame signal is completed, the intra-frame/inter-frame encoding process 60 can be terminated. Of course, the number of executions of step 606 in this embodiment can also be adjusted according to the number of sub-luminance frame signals and sub-chrominance frame signals included in the plurality of input frame signals, which is not intended to limit the scope of the present invention.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of the execution time of the intra-frame/inter-frame coding operations corresponding to the brightness frame signals S_L0 and S_L1 of the multiple input frame signals in the embodiment of the present invention. In this embodiment, only the working The luminance frame signals S_L0, S_L1 received by the loop module LM, the luminance frame signals S_L0, S_L1 include a plurality of sub-luminance frame signals S_L0_0～S_L0_15, S_L1_0～S_L1_15 (that is, coded as 0～15 respectively), of course, the The working loop module LM also receives multiple chrominance frame signals of multiple input frame signals at the same time. However, for the sake of brevity, the following only uses the sub-luminance frame signal to represent the existing multiple input frame signals, but it is not used to limit scope of the invention. From a first time point S1 to a sixth time point S6 in this embodiment, the sub-luminance frame signal S_L0_0 sequentially performs the first encoding operation (i.e. pixel prediction operation IAP, discrete cosine transform operation DCT, quantization operation Q, inverse Quantization operation IQ and inverse discrete cosine transform operation IDCT and pixel reconstruction operation REC); From a second time point S2 to a seventh time point S7, the second encoding operation (that is, the motion compensation operation MC) is performed sequentially from the sub-luminance frame signal S_L1_0 , discrete cosine transform operation DCT, quantization operation Q, inverse quantization operation IQ and inverse discrete cosine transform operation IDCT and pixel reconstruction operation REC); similarly, from the third time point S3 to the fifth time point S5, the sub-brightness frame signal S_L1_1 ~S_L1_3 performs the second coding operation in sequence and lasts for six time points, until a sixth time point S6, the sub-luminance frame signal S_L_0 completes its coding operation, and at a seventh time point S7, the sub-luminance frame signal S_L0_1 continues Its first encoding operation. After the luminance frame signal S_L1 completes the second encoding operation, the working loop module LM then continues to perform the first encoding operation on the luminance frame signal S_L0 until the first encoding operation of the luminance frame signal S_L0 is completed, and then the intra/inter-frame encoding is completed Related operations of process 60. Of course, in different embodiments, the operating timing of multiple chrominance frame signals of different input frame signals can also be adaptively added after the operating timing of the luma frame signals S_L0 and S_L1 in the embodiment in FIG. 7 , or according to different requirements. Correspondingly arranging the operation timing of the chrominance frame signals at the waiting timing of the hardware resources of the working loop module LM also belongs to the scope of the present invention.

Compared with the known technology, the intra-frame encoding process 30 and the intra-frame/inter-frame encoding process 60 in this embodiment can control multiple components of the working loop module LM to simultaneously perform sub-luminance frame signals of different input frame signals Or the first/second encoding operation of the sub-chroma frame signal, so as to make full use of the waiting time spent by the multiple components of the working loop module LM in the prior known technology, and then greatly improve the execution of the high-efficiency video encoding device 1 efficiency. Furthermore, the present embodiment also adds operation modes of the transfer units 17 and 18 and the intra-frame luma register and the intra-frame chrominance register, which can also greatly increase the application space of the high-efficiency video encoding device 1 .

It should be noted that the present invention improves the processing efficiency by adjusting the scheduling sequence of the encoding operation of the intra-frame input signal. Those skilled in the art can make appropriate changes according to the foregoing embodiments, but are not limited thereto. For example, please refer to FIG. 8 , which is a schematic diagram of an embodiment of the scheduling module 10 . As shown in FIG. 8 , the scheduling module 10 may include an intra-frame luma job queue, an intra-frame chroma job queue, an inter-frame job queue and a logic module. The logic module is used for judging the dependency relationship between frame signals, deciding to start or output the contents of intra-frame luminance work queue, intra-frame chroma work queue or inter-frame work queue, and then output control signals to the work loop module LM. After the working loop module LM receives the control signal from the scheduling module 10, it can perform the corresponding encoding operation. FIG. 8 is an illustration of one implementation of the scheduling module 10 , and those skilled in the art can make appropriate adjustments according to the needs of the system, and are not limited thereto.

In summary, the embodiment of the present invention teaches a scheduling method for a high-efficiency video encoding device. Through the scheduling module and its corresponding analyzer, it is determined whether the current input frame signal is to be intra-frame encoded or not. Intra-frame/inter-frame coding operations, and correspondingly transmit control signals to the estimation module, discrete cosine transformation module, quantization module, inverse quantization module, inverse discrete cosine transformation module and pixel reconstruction module of the working loop module, to respectively perform different input The luminance frame signal and the chrominance frame signal of the frame signal are correlated with encoding operation, thereby saving the waiting time wasted by hardware resources in the prior art.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (19)

1. a kind of scheduling method, is used for a high efficiency video coding apparatus, which includes：

Multiple input frame signal is received by an arranging module of the high efficiency video coding apparatus, a control signal is generated with corresponding Judge whether each input frame signal carries out an encoding operation within the frame/frames, and each input frame is judged by the arranging module Signal is a brightness frame signal or a coloration frame signal；And

When the control signal is judged to carry out the encoding operation within the frame/frames, the high efficiency video coding apparatus is in each One first encoding operation and one second encoding operation sequentially are carried out to more persons of multiple frame signals in work period；

Wherein, which is sequentially to carry out a pixel to estimate operation, discrete cosine transform operation, a quantization behaviour Work, an inverse quantization operation, an anti-discrete cosine conversion operation and a pixel reconstruction operation, which is sequentially to carry out The operation of one motion compensation, discrete cosine transform operation, the quantization operation, the inverse quantization operation, the anti-discrete cosine conversion behaviour Work and the pixel reconstruction operation, and each work period is single brightness frame signal or single chrominance frames in each input frame signal Signal carries out the time corresponding to any operation in any operation in first encoding operation or second encoding operation.

2. scheduling method as described in claim 1, which is characterized in that also include：

When the control signal is judged without the encoding operation within the frame/frames, the high efficiency video coding apparatus is sequentially right In multiple sub- brightness frame signals of each brightness frame signal one in multiple sub- coloration frame signals of one and each coloration frame signal Person carries out first encoding operation.

3. scheduling method as claimed in claim 2, which is characterized in that each brightness frame signal includes that at least one first son is bright Spend frame signal, each coloration frame signal includes at least one first sub- coloration frame signal, and when the control signal be judged not into Row this within the frame/frames encoding operation when, the high efficiency video coding apparatus is sequentially bright to multiple son of each brightness frame signal One carries out first encoding operation with one in multiple sub- coloration frame signal of each coloration frame signal in degree frame signal Step also includes：

In one first work period, which carries out one first operation to the first sub- brightness frame signal；

One second work period after first work period, the high efficiency video coding apparatus believe the first sub- chrominance frames First operation number is carried out, while the high efficiency video coding apparatus carries out one second operation to the first sub- brightness frame signal； And

A third work period after second work period, the high efficiency video coding apparatus believe the first sub- chrominance frames Number carry out second operation；

Wherein, the arranging module received in sequence first sub- brightness frame signal and the first sub- coloration frame signal, and first behaviour Make with second operation to be sequentially that the pixel estimates operation, discrete cosine transform operation, the quantization operation, the inverse quantization behaviour Make, is both continuous in the anti-discrete cosine conversion operation and the pixel reconstruction operation.

4. scheduling method as described in claim 1, which is characterized in that compiled within the frame/frames when arranging module judgement carries out this When code operation, the high efficiency video coding apparatus sequentially to more persons of multiple frame signal carry out first encoding operation with this The step of two encoding operations also includes：

In one first work period, the high efficiency video coding apparatus is to one first input frame signal in multiple input frame signal It carries out first encoding operation and continues six work periods；

One second work period after first work period, the high efficiency video coding apparatus is to multiple input frame signal In one second input frame signal carry out second encoding operation and continue six work periods；And

It repeats above operation and multiple sub- brightness frame signals of the second input frame signal is carried out with multiple sub- coloration frame signals Second encoding operation, and continue first encoding operation of the first input frame signal.

5. scheduling method as claimed in claim 4, which is characterized in that also include：

In second volume for the multiple sub- brightness frame signal and multiple sub- coloration frame signal for completing the second input frame signal Code operation before, in each work period, the high efficiency video coding apparatus simultaneously to this first input frame signal carry out this first Encoding operation and to this second input frame signal carry out second encoding operation.

6. scheduling method as claimed in claim 4, which is characterized in that also include：

Once complete multiple sub- brightness frame signal and the multiple sub- coloration frame signal of the second input frame signal this second After encoding operation, in each work period later, which is somebody's turn to do the first input frame signal First encoding operation.

7. scheduling method as described in claim 1, which is characterized in that the high efficiency video coding apparatus also includes to estimate To carry out, the pixel estimates operation to module or motion compensation operation, a discrete cosine transform module turn to carry out the discrete cosine Change operation, a quantization modules carry out the inverse quantization operation, an anti-discrete cosine to carry out the quantization operation, an inverse quantization module Conversion module rebuilds module carrying out the anti-discrete cosine conversion operation and a pixel and carries out the pixel reconstruction operation, and this is pre- Estimate module, the discrete cosine transform module, the quantization modules, the inverse quantization module, the anti-discrete cosine conversion module and the picture It is sequentially to couple to form a work loop module that element, which rebuilds module,.

8. scheduling method as claimed in claim 7, which is characterized in that this estimates module, the discrete cosine transform module, the amount It all includes a parser to change module, the inverse quantization module, the anti-discrete cosine conversion module and the pixel to rebuild module, is used for The control signal for receiving the arranging module judges whether to the encoding operation within the frame/frames with corresponding, while also judging should It is the brightness frame signal or the coloration frame signal to input frame signal.

9. scheduling method as claimed in claim 7, which is characterized in that the quantization modules are also coupled to one turn of leaflet member, are used for defeated Go out in a residual signal a to frame for the quantization modules coloration buffer in brightness buffer or a frame.

10. scheduling method as claimed in claim 7, which is characterized in that the pixel rebuilds module and is also coupled to one turn of leaflet member, uses Coloration buffer in brightness buffer or a frame is rebuild in a reconstruction signal a to frame for module to export the pixel.

11. a kind of high efficiency video coding apparatus, includes：

One arranging module controls signal to judge that each input frame is believed for receiving multiple input frame signal with corresponding generation one An encoding operation within the frame/frames number whether is carried out, and for judging each input frame signal for a brightness frame signal or a coloration Frame signal；And

One work loop module, couples the arranging module, includes to estimate module, a discrete cosine transform module, a quantization Module, an inverse quantization module, an anti-discrete cosine conversion module rebuild module with a pixel and are sequentially to couple each other；

Wherein, when the control signal is judged to carry out the encoding operation within the frame/frames, the work loop module is in each work Make sequentially to carry out one first encoding operation and one second encoding operation to more persons of multiple frame signal in the period, first coding Operation is sequentially to carry out a pixel to estimate operation, discrete cosine transform operation, a quantization operation, an inverse quantization operation, one instead Discrete cosine transform is operated sequentially carries out that a motion compensation operation, this is discrete with a pixel reconstruction operation, second encoding operation Cosine conversion operation, the quantization operation, the inverse quantization operation, the anti-discrete cosine conversion operation and the pixel reconstruction operation, and Each work period is that single brightness frame signal or single coloration frame signal carry out first coding behaviour in each input frame signal A time in work in any operation or second encoding operation corresponding to any operation.

12. high efficiency video coding apparatus as claimed in claim 11, which is characterized in that this estimates module, the discrete cosine Conversion module, the quantization modules, the inverse quantization module, the anti-discrete cosine conversion module and the pixel rebuild module One parser, for receiving the control signal of the arranging module, carried out in the intra-encoding operations or the frame with corresponding to judgement/ Interframe encode operates, while also judging each input frame signal for the brightness frame signal or the coloration frame signal.

13. high efficiency video coding apparatus as claimed in claim 11, which is characterized in that the quantization modules are also coupled to one turn of biography Unit, coloration buffer in brightness buffer or a frame in the residual signal a to frame for exporting the quantization modules.

14. high efficiency video coding apparatus as claimed in claim 11, which is characterized in that the pixel rebuilds module and is also coupled to one Turn leaflet member, rebuilds in a reconstruction signal a to frame for module that coloration is temporary in brightness buffer or a frame for exporting the pixel Device.

15. high efficiency video coding apparatus as claimed in claim 11, which is characterized in that when the control signal be judged not into Row this within the frame/frames encoding operation when, the work loop module is sequentially to multiple sub- brightness frame signals of each brightness frame signal Middle one carries out first encoding operation with one in multiple sub- coloration frame signals of each coloration frame signal.

16. high efficiency video coding apparatus as claimed in claim 15, which is characterized in that each brightness frame signal include to Few one first sub- brightness frame signal, each coloration frame signal includes at least one first sub- coloration frame signal, and when the control is believed Number be judged without this within the frame/frames encoding operation when, also include following steps：

In one first work period, which carries out one first operation to the first sub- brightness frame signal；

One second work period after first work period, the work loop module carry out the first sub- coloration frame signal First operation, while the work loop module carries out one second operation to the first sub- brightness frame signal；And

A third work period after second work period, the work loop module carry out the first sub- coloration frame signal Second operation；

Wherein, the arranging module received in sequence first sub- brightness frame signal and the first sub- coloration frame signal, and first behaviour Make with second operation to be sequentially that the pixel estimates operation, discrete cosine transform operation, the quantization operation, the inverse quantization behaviour Make, is both continuous in the anti-discrete cosine conversion operation and the pixel reconstruction operation.

17. high efficiency video coding apparatus as claimed in claim 11, which is characterized in that when the control signal is judged progress This within the frame/frames encoding operation when, also include following steps：

In one first work period, which carries out one first input frame signal in multiple frame signal First encoding operation and continue six work periods；

One second work period after first work period, the high efficiency video coding apparatus is in multiple frame signal one Second input frame signal carries out second encoding operation and continues six work periods；And

It repeats above operation and multiple sub- brightness frame signals of the second input frame signal is carried out with multiple sub- coloration frame signals Second encoding operation, and continue first encoding operation of the first input frame signal.

18. high efficiency video coding apparatus as claimed in claim 17, which is characterized in that when the control signal is judged progress This within the frame/frames encoding operation when, also include following steps：

In second volume for the multiple sub- brightness frame signal and multiple sub- coloration frame signal for completing the second input frame signal Code operation before, in each work period, the high efficiency video coding apparatus simultaneously to this first input frame signal carry out this first Encoding operation and to this second input frame signal carry out second encoding operation.

19. high efficiency video coding apparatus as claimed in claim 17, which is characterized in that when the control signal is judged progress This within the frame/frames encoding operation when, also include following steps：

Complete multiple sub- brightness frame signal of the second input frame signal and second coding of multiple sub- coloration frame signal After operation, in each work period, which only carries out first coding to the first input frame signal Operation.